| Qflow static timing analysis logfile created on Fri Jan 10 20:57:52 EST 2020 |
| Creating OpenSTA input file striVe_spi.conf |
| Running OpenSTA static timing analysis |
| sta < striVe_spi.conf |
| OpenSTA Copyright (c) 2018, Parallax Software, Inc. |
| License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html> |
| |
| This is free software, and you are free to change and redistribute it |
| under certain conditions; type `show_copying' for details. |
| This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'. |
| Error: history.tcl, 306 invoked "return" outside of a proc. |
| Warning: /home/tim/projects/efabless/tech/SkyWater/EFS8A/libs.ref/liberty/scs8ms/scs8ms_tt_1.80v_25C.lib, line 387 axis type normalized_voltage not supported. |
| Warning: /home/tim/projects/efabless/tech/SkyWater/EFS8A/libs.ref/liberty/scs8ms/scs8ms_tt_1.80v_25C.lib, line 384 missing variable_2 attribute. |
| Warning: /home/tim/projects/efabless/tech/SkyWater/EFS8A/libs.ref/liberty/scs8ms/scs8ms_tt_1.80v_25C.lib, line 23 library scs8ms_tt_1.80v_25C already exists. |
| Warning: /home/tim/projects/efabless/tech/SkyWater/EFS8A/libs.ref/liberty/scs8ms/scs8ms_tt_1.80v_25C.lib, line 387 axis type normalized_voltage not supported. |
| Warning: /home/tim/projects/efabless/tech/SkyWater/EFS8A/libs.ref/liberty/scs8ms/scs8ms_tt_1.80v_25C.lib, line 384 missing variable_2 attribute. |
| Warning: striVe_spi.rtlnopwr.v, line 339 module scs8ms_fill_4 not found. Creating black box for SFILL11760x8029. |
| Warning: striVe_spi.rtlnopwr.v, line 342 module scs8ms_fill_2 not found. Creating black box for FILL14448x11359. |
| Warning: striVe_spi.rtlnopwr.v, line 356 module scs8ms_tapvpwrvgnd_1 not found. Creating black box for scs8ms_tapvpwrvgnd_1_0__534_. |
| Warning: striVe_spi.rtlnopwr.v, line 507 module scs8ms_diode_2 not found. Creating black box for scs8ms_diode_2_0__421_. |
| Warning: striVe_spi.rtlnopwr.v, line 711 module scs8ms_fill_1 not found. Creating black box for FILL14544x4699. |
| Warning: striVe_spi.sdc, 1 port 'clock' not found. |
| Warning: There are 9 input ports missing set_input_delay. |
| Warning: There are 39 output ports missing set_output_delay. |
| Warning: There are 47 unclocked register/latch pins. |
| Warning: There are 86 unconstrained endpoints. |
| Not |
| Check type Total Annotated Annotated |
| ---------------------------------------------------------------- |
| cell setup arcs 47 0 47 |
| cell hold arcs 47 0 47 |
| cell recovery arcs 47 0 47 |
| cell removal arcs 47 0 47 |
| cell width arcs 94 0 94 |
| ---------------------------------------------------------------- |
| 282 0 282 |
| Not |
| Delay type Total Annotated Annotated |
| ---------------------------------------------------------------- |
| cell arcs 1179 0 1179 |
| internal net arcs 825 0 825 |
| net arcs from primary inputs 38 0 38 |
| net arcs to primary outputs 39 0 39 |
| ---------------------------------------------------------------- |
| 2081 0 2081 |
| No constrained paths. |
