lef/striVe_soc.lef

VERSION 5.3 ;
   NAMESCASESENSITIVE ON ;
   NOWIREEXTENSIONATPIN ON ;
   DIVIDERCHAR "/" ;
   BUSBITCHARS "[]" ;
UNITS
   DATABASE MICRONS 1000 ;
END UNITS

MACRO striVe_soc
   CLASS BLOCK ;
   FOREIGN striVe_soc ;
   ORIGIN -0.0000 -0.0000 ;
   SIZE 1844.9650 BY 1844.9650 ;
   PIN pll_clk
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1496.9500 0.0000 1497.5100 2.1200 ;
      END
   END pll_clk
   PIN ext_clk
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 536.2200 2.2000 537.4200 ;
      END
   END ext_clk
   PIN ext_clk_sel
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1640.5399 2.2000 1641.7400 ;
      END
   END ext_clk_sel
   PIN clk
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1110.5499 0.0000 1111.1100 2.1200 ;
      END
   END clk
   PIN resetn
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 714.3800 2.2000 715.5800 ;
      END
   END resetn
   PIN gpio_out_pad[15]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 652.3900 0.0000 652.9500 2.1200 ;
      END
   END gpio_out_pad[15]
   PIN gpio_out_pad[14]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 915.6600 1844.9650 916.8600 ;
      END
   END gpio_out_pad[14]
   PIN gpio_out_pad[13]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1191.5100 1842.8450 1192.0699 1844.9650 ;
      END
   END gpio_out_pad[13]
   PIN gpio_out_pad[12]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 97.6300 0.0000 98.1900 2.1200 ;
      END
   END gpio_out_pad[12]
   PIN gpio_out_pad[11]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1129.1799 1844.9650 1130.3800 ;
      END
   END gpio_out_pad[11]
   PIN gpio_out_pad[10]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 363.5100 0.0000 364.0700 2.1200 ;
      END
   END gpio_out_pad[10]
   PIN gpio_out_pad[9]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1665.3099 0.0000 1665.8700 2.1200 ;
      END
   END gpio_out_pad[9]
   PIN gpio_out_pad[8]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 9.3100 1842.8450 9.8700 1844.9650 ;
      END
   END gpio_out_pad[8]
   PIN gpio_out_pad[7]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1600.9099 1842.8450 1601.4700 1844.9650 ;
      END
   END gpio_out_pad[7]
   PIN gpio_out_pad[6]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 630.0600 1844.9650 631.2600 ;
      END
   END gpio_out_pad[6]
   PIN gpio_out_pad[5]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 594.7000 1844.9650 595.9000 ;
      END
   END gpio_out_pad[5]
   PIN gpio_out_pad[4]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1215.4299 1842.8450 1215.9900 1844.9650 ;
      END
   END gpio_out_pad[4]
   PIN gpio_out_pad[3]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 460.1100 0.0000 460.6700 2.1200 ;
      END
   END gpio_out_pad[3]
   PIN gpio_out_pad[2]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 250.6200 2.2000 251.8200 ;
      END
   END gpio_out_pad[2]
   PIN gpio_out_pad[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 72.4600 2.2000 73.6600 ;
      END
   END gpio_out_pad[1]
   PIN gpio_out_pad[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1183.2300 0.0000 1183.7899 2.1200 ;
      END
   END gpio_out_pad[0]
   PIN gpio_in_pad[15]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1414.7800 1844.9650 1415.9800 ;
      END
   END gpio_in_pad[15]
   PIN gpio_in_pad[14]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1480.3900 1842.8450 1480.9500 1844.9650 ;
      END
   END gpio_in_pad[14]
   PIN gpio_in_pad[13]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1335.9500 1842.8450 1336.5100 1844.9650 ;
      END
   END gpio_in_pad[13]
   PIN gpio_in_pad[12]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 122.4700 0.0000 123.0300 2.1200 ;
      END
   END gpio_in_pad[12]
   PIN gpio_in_pad[11]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 107.8200 2.2000 109.0200 ;
      END
   END gpio_in_pad[11]
   PIN gpio_in_pad[10]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1529.1500 1842.8450 1529.7100 1844.9650 ;
      END
   END gpio_in_pad[10]
   PIN gpio_in_pad[9]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1284.2200 2.2000 1285.4199 ;
      END
   END gpio_in_pad[9]
   PIN gpio_in_pad[8]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1236.6200 1844.9650 1237.8199 ;
      END
   END gpio_in_pad[8]
   PIN gpio_in_pad[7]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 273.7400 1844.9650 274.9400 ;
      END
   END gpio_in_pad[7]
   PIN gpio_in_pad[6]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 428.7800 2.2000 429.9800 ;
      END
   END gpio_in_pad[6]
   PIN gpio_in_pad[5]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 918.2700 0.0000 918.8300 2.1200 ;
      END
   END gpio_in_pad[5]
   PIN gpio_in_pad[4]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 285.9800 2.2000 287.1800 ;
      END
   END gpio_in_pad[4]
   PIN gpio_in_pad[3]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 451.9000 1844.9650 453.1000 ;
      END
   END gpio_in_pad[3]
   PIN gpio_in_pad[2]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 167.6600 1844.9650 168.8600 ;
      END
   END gpio_in_pad[2]
   PIN gpio_in_pad[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1231.0699 0.0000 1231.6300 2.1200 ;
      END
   END gpio_in_pad[1]
   PIN gpio_in_pad[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1013.9500 0.0000 1014.5099 2.1200 ;
      END
   END gpio_in_pad[0]
   PIN gpio_mode0_pad[15]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1359.8700 1842.8450 1360.4299 1844.9650 ;
      END
   END gpio_mode0_pad[15]
   PIN gpio_mode0_pad[14]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1617.4700 0.0000 1618.0299 2.1200 ;
      END
   END gpio_mode0_pad[14]
   PIN gpio_mode0_pad[13]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 25.8700 0.0000 26.4300 2.1200 ;
      END
   END gpio_mode0_pad[13]
   PIN gpio_mode0_pad[12]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 748.9900 0.0000 749.5500 2.1200 ;
      END
   END gpio_mode0_pad[12]
   PIN gpio_mode0_pad[11]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 998.3100 1842.8450 998.8700 1844.9650 ;
      END
   END gpio_mode0_pad[11]
   PIN gpio_mode0_pad[10]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 701.1500 0.0000 701.7100 2.1200 ;
      END
   END gpio_mode0_pad[10]
   PIN gpio_mode0_pad[9]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1022.2300 1842.8450 1022.7900 1844.9650 ;
      END
   END gpio_mode0_pad[9]
   PIN gpio_mode0_pad[8]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 702.1400 1844.9650 703.3400 ;
      END
   END gpio_mode0_pad[8]
   PIN gpio_mode0_pad[7]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1663.6599 1844.9650 1664.8600 ;
      END
   END gpio_mode0_pad[7]
   PIN gpio_mode0_pad[6]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1093.8199 1844.9650 1095.0200 ;
      END
   END gpio_mode0_pad[6]
   PIN gpio_mode0_pad[5]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 419.6300 1842.8450 420.1900 1844.9650 ;
      END
   END gpio_mode0_pad[5]
   PIN gpio_mode0_pad[4]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 880.3000 1844.9650 881.5000 ;
      END
   END gpio_mode0_pad[4]
   PIN gpio_mode0_pad[3]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 371.7900 1842.8450 372.3500 1844.9650 ;
      END
   END gpio_mode0_pad[3]
   PIN gpio_mode0_pad[2]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1771.1000 1844.9650 1772.2999 ;
      END
   END gpio_mode0_pad[2]
   PIN gpio_mode0_pad[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 612.8300 1842.8450 613.3900 1844.9650 ;
      END
   END gpio_mode0_pad[1]
   PIN gpio_mode0_pad[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1809.7500 0.0000 1810.3099 2.1200 ;
      END
   END gpio_mode0_pad[0]
   PIN gpio_mode1_pad[15]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 679.0200 2.2000 680.2200 ;
      END
   END gpio_mode1_pad[15]
   PIN gpio_mode1_pad[14]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1592.9399 1844.9650 1594.1400 ;
      END
   END gpio_mode1_pad[14]
   PIN gpio_mode1_pad[13]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 606.9400 2.2000 608.1400 ;
      END
   END gpio_mode1_pad[13]
   PIN gpio_mode1_pad[12]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1841.9500 1842.8450 1842.5100 1844.9650 ;
      END
   END gpio_mode1_pad[12]
   PIN gpio_mode1_pad[11]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 636.7500 1842.8450 637.3100 1844.9650 ;
      END
   END gpio_mode1_pad[11]
   PIN gpio_mode1_pad[10]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1058.4600 1844.9650 1059.6600 ;
      END
   END gpio_mode1_pad[10]
   PIN gpio_mode1_pad[9]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 299.1100 1842.8450 299.6700 1844.9650 ;
      END
   END gpio_mode1_pad[9]
   PIN gpio_mode1_pad[8]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1625.7500 1842.8450 1626.3099 1844.9650 ;
      END
   END gpio_mode1_pad[8]
   PIN gpio_mode1_pad[7]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 202.5100 1842.8450 203.0700 1844.9650 ;
      END
   END gpio_mode1_pad[7]
   PIN gpio_mode1_pad[6]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1432.5499 1842.8450 1433.1100 1844.9650 ;
      END
   END gpio_mode1_pad[6]
   PIN gpio_mode1_pad[5]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 275.1900 1842.8450 275.7500 1844.9650 ;
      END
   END gpio_mode1_pad[5]
   PIN gpio_mode1_pad[4]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1485.5000 1844.9650 1486.7000 ;
      END
   END gpio_mode1_pad[4]
   PIN gpio_mode1_pad[3]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1141.4199 2.2000 1142.6200 ;
      END
   END gpio_mode1_pad[3]
   PIN gpio_mode1_pad[2]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1035.3400 2.2000 1036.5399 ;
      END
   END gpio_mode1_pad[2]
   PIN gpio_mode1_pad[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1142.7500 1842.8450 1143.3099 1844.9650 ;
      END
   END gpio_mode1_pad[1]
   PIN gpio_mode1_pad[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1094.9100 1842.8450 1095.4700 1844.9650 ;
      END
   END gpio_mode1_pad[0]
   PIN gpio_outenb_pad[15]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1534.4600 2.2000 1535.6599 ;
      END
   END gpio_outenb_pad[15]
   PIN gpio_outenb_pad[14]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 757.2700 1842.8450 757.8300 1844.9650 ;
      END
   END gpio_outenb_pad[14]
   PIN gpio_outenb_pad[13]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 516.2300 1842.8450 516.7900 1844.9650 ;
      END
   END gpio_outenb_pad[13]
   PIN gpio_outenb_pad[12]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 467.4700 1842.8450 468.0300 1844.9650 ;
      END
   END gpio_outenb_pad[12]
   PIN gpio_outenb_pad[11]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1520.8700 0.0000 1521.4299 2.1200 ;
      END
   END gpio_outenb_pad[11]
   PIN gpio_outenb_pad[10]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1675.8999 2.2000 1677.1000 ;
      END
   END gpio_outenb_pad[10]
   PIN gpio_outenb_pad[9]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 829.9500 1842.8450 830.5100 1844.9650 ;
      END
   END gpio_outenb_pad[9]
   PIN gpio_outenb_pad[8]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1312.0300 1842.8450 1312.5900 1844.9650 ;
      END
   END gpio_outenb_pad[8]
   PIN gpio_outenb_pad[7]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 309.1000 1844.9650 310.3000 ;
      END
   END gpio_outenb_pad[7]
   PIN gpio_outenb_pad[6]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 877.7900 1842.8450 878.3500 1844.9650 ;
      END
   END gpio_outenb_pad[6]
   PIN gpio_outenb_pad[5]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1747.9800 2.2000 1749.1799 ;
      END
   END gpio_outenb_pad[5]
   PIN gpio_outenb_pad[4]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1344.0599 1844.9650 1345.2600 ;
      END
   END gpio_outenb_pad[4]
   PIN gpio_outenb_pad[3]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 733.3500 1842.8450 733.9100 1844.9650 ;
      END
   END gpio_outenb_pad[3]
   PIN gpio_outenb_pad[2]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 580.6300 0.0000 581.1900 2.1200 ;
      END
   END gpio_outenb_pad[2]
   PIN gpio_outenb_pad[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1497.7400 2.2000 1498.9399 ;
      END
   END gpio_outenb_pad[1]
   PIN gpio_outenb_pad[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 927.9000 2.2000 929.1000 ;
      END
   END gpio_outenb_pad[0]
   PIN gpio_inenb_pad[15]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1700.3800 1844.9650 1701.5800 ;
      END
   END gpio_inenb_pad[15]
   PIN gpio_inenb_pad[14]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1689.2300 0.0000 1689.7899 2.1200 ;
      END
   END gpio_inenb_pad[14]
   PIN gpio_inenb_pad[13]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1279.8300 0.0000 1280.3900 2.1200 ;
      END
   END gpio_inenb_pad[13]
   PIN gpio_inenb_pad[12]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 154.6700 1842.8450 155.2300 1844.9650 ;
      END
   END gpio_inenb_pad[12]
   PIN gpio_inenb_pad[11]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 323.0300 1842.8450 323.5900 1844.9650 ;
      END
   END gpio_inenb_pad[11]
   PIN gpio_inenb_pad[10]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 435.2700 0.0000 435.8300 2.1200 ;
      END
   END gpio_inenb_pad[10]
   PIN gpio_inenb_pad[9]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1721.4299 1842.8450 1721.9900 1844.9650 ;
      END
   END gpio_inenb_pad[9]
   PIN gpio_inenb_pad[8]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1456.4700 1842.8450 1457.0299 1844.9650 ;
      END
   END gpio_inenb_pad[8]
   PIN gpio_inenb_pad[7]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1070.7000 2.2000 1071.9000 ;
      END
   END gpio_inenb_pad[7]
   PIN gpio_inenb_pad[6]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 34.1500 1842.8450 34.7100 1844.9650 ;
      END
   END gpio_inenb_pad[6]
   PIN gpio_inenb_pad[5]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1213.5000 2.2000 1214.7000 ;
      END
   END gpio_inenb_pad[5]
   PIN gpio_inenb_pad[4]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1427.0200 2.2000 1428.2200 ;
      END
   END gpio_inenb_pad[4]
   PIN gpio_inenb_pad[3]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1794.1100 1842.8450 1794.6699 1844.9650 ;
      END
   END gpio_inenb_pad[3]
   PIN gpio_inenb_pad[2]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 358.0600 2.2000 359.2600 ;
      END
   END gpio_inenb_pad[2]
   PIN gpio_inenb_pad[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 143.1800 2.2000 144.3800 ;
      END
   END gpio_inenb_pad[1]
   PIN gpio_inenb_pad[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1450.1400 1844.9650 1451.3400 ;
      END
   END gpio_inenb_pad[0]
   PIN adc0_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1783.3400 2.2000 1784.5399 ;
      END
   END adc0_ena
   PIN adc0_convert
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1462.3800 2.2000 1463.5800 ;
      END
   END adc0_convert
   PIN adc0_data[9]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 986.3800 1844.9650 987.5800 ;
      END
   END adc0_data[9]
   PIN adc0_data[8]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 443.5500 1842.8450 444.1100 1844.9650 ;
      END
   END adc0_data[8]
   PIN adc0_data[7]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 411.3500 0.0000 411.9100 2.1200 ;
      END
   END adc0_data[7]
   PIN adc0_data[6]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1351.5900 0.0000 1352.1500 2.1200 ;
      END
   END adc0_data[6]
   PIN adc0_data[5]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 869.5100 0.0000 870.0700 2.1200 ;
      END
   END adc0_data[5]
   PIN adc0_data[4]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 387.4300 0.0000 387.9900 2.1200 ;
      END
   END adc0_data[4]
   PIN adc0_data[3]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 464.1400 2.2000 465.3400 ;
      END
   END adc0_data[3]
   PIN adc0_data[2]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1649.6699 1842.8450 1650.2300 1844.9650 ;
      END
   END adc0_data[2]
   PIN adc0_data[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 338.6700 0.0000 339.2300 2.1200 ;
      END
   END adc0_data[1]
   PIN adc0_data[0]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 559.3400 1844.9650 560.5400 ;
      END
   END adc0_data[0]
   PIN adc0_done
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 37.1000 2.2000 38.3000 ;
      END
   END adc0_done
   PIN adc0_clk
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 642.3000 2.2000 643.5000 ;
      END
   END adc0_clk
   PIN adc0_inputsrc[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1164.5399 1844.9650 1165.7400 ;
      END
   END adc0_inputsrc[1]
   PIN adc0_inputsrc[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 966.1100 0.0000 966.6700 2.1200 ;
      END
   END adc0_inputsrc[0]
   PIN adc1_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 942.1900 0.0000 942.7500 2.1200 ;
      END
   END adc1_ena
   PIN adc1_convert
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 266.9100 0.0000 267.4700 2.1200 ;
      END
   END adc1_convert
   PIN adc1_clk
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 218.1500 0.0000 218.7100 2.1200 ;
      END
   END adc1_clk
   PIN adc1_inputsrc[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1557.5800 1844.9650 1558.7799 ;
      END
   END adc1_inputsrc[1]
   PIN adc1_inputsrc[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 194.2300 0.0000 194.7900 2.1200 ;
      END
   END adc1_inputsrc[0]
   PIN adc1_data[9]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 531.8700 0.0000 532.4300 2.1200 ;
      END
   END adc1_data[9]
   PIN adc1_data[8]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1070.9900 1842.8450 1071.5499 1844.9650 ;
      END
   END adc1_data[8]
   PIN adc1_data[7]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1544.7899 0.0000 1545.3500 2.1200 ;
      END
   END adc1_data[7]
   PIN adc1_data[6]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 381.1800 1844.9650 382.3800 ;
      END
   END adc1_data[6]
   PIN adc1_data[5]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 772.9100 0.0000 773.4700 2.1200 ;
      END
   END adc1_data[5]
   PIN adc1_data[4]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1761.9099 0.0000 1762.4700 2.1200 ;
      END
   END adc1_data[4]
   PIN adc1_data[3]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1159.3099 0.0000 1159.8700 2.1200 ;
      END
   END adc1_data[3]
   PIN adc1_data[2]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 499.5000 2.2000 500.7000 ;
      END
   END adc1_data[2]
   PIN adc1_data[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 484.0300 0.0000 484.5900 2.1200 ;
      END
   END adc1_data[1]
   PIN adc1_data[0]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 24.8600 1844.9650 26.0600 ;
      END
   END adc1_data[0]
   PIN adc1_done
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 58.0700 1842.8450 58.6300 1844.9650 ;
      END
   END adc1_done
   PIN dac_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1713.1499 0.0000 1713.7100 2.1200 ;
      END
   END dac_ena
   PIN dac_value[9]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1383.7899 1842.8450 1384.3500 1844.9650 ;
      END
   END dac_value[9]
   PIN dac_value[8]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 73.7100 0.0000 74.2700 2.1200 ;
      END
   END dac_value[8]
   PIN dac_value[7]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 564.0700 1842.8450 564.6300 1844.9650 ;
      END
   END dac_value[7]
   PIN dac_value[6]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 492.3100 1842.8450 492.8700 1844.9650 ;
      END
   END dac_value[6]
   PIN dac_value[5]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 901.7100 1842.8450 902.2700 1844.9650 ;
      END
   END dac_value[5]
   PIN dac_value[4]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 853.8700 1842.8450 854.4300 1844.9650 ;
      END
   END dac_value[4]
   PIN dac_value[3]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 487.2600 1844.9650 488.4600 ;
      END
   END dac_value[3]
   PIN dac_value[2]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1400.3500 0.0000 1400.9099 2.1200 ;
      END
   END dac_value[2]
   PIN dac_value[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 844.9400 1844.9650 846.1400 ;
      END
   END dac_value[1]
   PIN dac_value[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 588.9100 1842.8450 589.4700 1844.9650 ;
      END
   END dac_value[0]
   PIN analog_out_sel
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1806.4600 1844.9650 1807.6599 ;
      END
   END analog_out_sel
   PIN opamp_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1023.1000 1844.9650 1024.2999 ;
      END
   END opamp_ena
   PIN opamp_bias_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1248.8600 2.2000 1250.0599 ;
      END
   END opamp_bias_ena
   PIN bg_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 507.9500 0.0000 508.5100 2.1200 ;
      END
   END bg_ena
   PIN comp_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1.9500 0.0000 2.5100 2.1200 ;
      END
   END comp_ena
   PIN comp_ninputsrc[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1569.8199 2.2000 1571.0200 ;
      END
   END comp_ninputsrc[1]
   PIN comp_ninputsrc[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1576.9900 1842.8450 1577.5499 1844.9650 ;
      END
   END comp_ninputsrc[0]
   PIN comp_pinputsrc[1]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1379.4199 1844.9650 1380.6200 ;
      END
   END comp_pinputsrc[1]
   PIN comp_pinputsrc[0]
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 925.6300 1842.8450 926.1900 1844.9650 ;
      END
   END comp_pinputsrc[0]
   PIN rcosc_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1770.1899 1842.8450 1770.7500 1844.9650 ;
      END
   END rcosc_ena
   PIN overtemp_ena
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1167.5900 1842.8450 1168.1500 1844.9650 ;
      END
   END overtemp_ena
   PIN overtemp
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1086.6300 0.0000 1087.1899 2.1200 ;
      END
   END overtemp
   PIN rcosc_in
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 395.7100 1842.8450 396.2700 1844.9650 ;
      END
   END rcosc_in
   PIN xtal_in
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1735.7400 1844.9650 1736.9399 ;
      END
   END xtal_in
   PIN comp_in
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 540.1500 1842.8450 540.7100 1844.9650 ;
      END
   END comp_in
   PIN spi_sck
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 781.1900 1842.8450 781.7500 1844.9650 ;
      END
   END spi_sck
   PIN spi_ro_config[7]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 950.4700 1842.8450 951.0300 1844.9650 ;
      END
   END spi_ro_config[7]
   PIN spi_ro_config[6]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1239.3500 1842.8450 1239.9099 1844.9650 ;
      END
   END spi_ro_config[6]
   PIN spi_ro_config[5]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 604.5500 0.0000 605.1100 2.1200 ;
      END
   END spi_ro_config[5]
   PIN spi_ro_config[4]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1737.9900 0.0000 1738.5499 2.1200 ;
      END
   END spi_ro_config[4]
   PIN spi_ro_config[3]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1697.5100 1842.8450 1698.0699 1844.9650 ;
      END
   END spi_ro_config[3]
   PIN spi_ro_config[2]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 857.1800 2.2000 858.3800 ;
      END
   END spi_ro_config[2]
   PIN spi_ro_config[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1472.1100 0.0000 1472.6699 2.1200 ;
      END
   END spi_ro_config[1]
   PIN spi_ro_config[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1038.7899 0.0000 1039.3500 2.1200 ;
      END
   END spi_ro_config[0]
   PIN spi_ro_xtal_ena
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1288.1100 1842.8450 1288.6699 1844.9650 ;
      END
   END spi_ro_xtal_ena
   PIN spi_ro_reg_ena
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 290.8300 0.0000 291.3900 2.1200 ;
      END
   END spi_ro_reg_ena
   PIN spi_ro_pll_dco_ena
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1376.4299 0.0000 1376.9900 2.1200 ;
      END
   END spi_ro_pll_dco_ena
   PIN spi_ro_pll_div[4]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1134.4700 0.0000 1135.0300 2.1200 ;
      END
   END spi_ro_pll_div[4]
   PIN spi_ro_pll_div[3]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 660.6700 1842.8450 661.2300 1844.9650 ;
      END
   END spi_ro_pll_div[3]
   PIN spi_ro_pll_div[2]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 130.7500 1842.8450 131.3100 1844.9650 ;
      END
   END spi_ro_pll_div[2]
   PIN spi_ro_pll_div[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1818.0299 1842.8450 1818.5900 1844.9650 ;
      END
   END spi_ro_pll_div[1]
   PIN spi_ro_pll_div[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 49.7900 0.0000 50.3500 2.1200 ;
      END
   END spi_ro_pll_div[0]
   PIN spi_ro_pll_sel[2]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 242.9900 0.0000 243.5500 2.1200 ;
      END
   END spi_ro_pll_sel[2]
   PIN spi_ro_pll_sel[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 684.5900 1842.8450 685.1500 1844.9650 ;
      END
   END spi_ro_pll_sel[1]
   PIN spi_ro_pll_sel[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1785.8300 0.0000 1786.3900 2.1200 ;
      END
   END spi_ro_pll_sel[0]
   PIN spi_ro_pll_trim[25]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 821.6700 0.0000 822.2300 2.1200 ;
      END
   END spi_ro_pll_trim[25]
   PIN spi_ro_pll_trim[24]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 203.0200 1844.9650 204.2200 ;
      END
   END spi_ro_pll_trim[24]
   PIN spi_ro_pll_trim[23]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1201.2600 1844.9650 1202.4600 ;
      END
   END spi_ro_pll_trim[23]
   PIN spi_ro_pll_trim[22]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1408.6300 1842.8450 1409.1899 1844.9650 ;
      END
   END spi_ro_pll_trim[22]
   PIN spi_ro_pll_trim[21]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 796.8300 0.0000 797.3900 2.1200 ;
      END
   END spi_ro_pll_trim[21]
   PIN spi_ro_pll_trim[20]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 963.2599 2.2000 964.4600 ;
      END
   END spi_ro_pll_trim[20]
   PIN spi_ro_pll_trim[19]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1818.7000 2.2000 1819.8999 ;
      END
   END spi_ro_pll_trim[19]
   PIN spi_ro_pll_trim[18]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 845.5900 0.0000 846.1500 2.1200 ;
      END
   END spi_ro_pll_trim[18]
   PIN spi_ro_pll_trim[17]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 170.3100 0.0000 170.8700 2.1200 ;
      END
   END spi_ro_pll_trim[17]
   PIN spi_ro_pll_trim[16]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 314.7500 0.0000 315.3100 2.1200 ;
      END
   END spi_ro_pll_trim[16]
   PIN spi_ro_pll_trim[15]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1271.9800 1844.9650 1273.1799 ;
      END
   END spi_ro_pll_trim[15]
   PIN spi_ro_pll_trim[14]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 226.4300 1842.8450 226.9900 1844.9650 ;
      END
   END spi_ro_pll_trim[14]
   PIN spi_ro_pll_trim[13]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1424.2700 0.0000 1424.8300 2.1200 ;
      END
   END spi_ro_pll_trim[13]
   PIN spi_ro_pll_trim[12]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 808.2200 1844.9650 809.4200 ;
      END
   END spi_ro_pll_trim[12]
   PIN spi_ro_pll_trim[11]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1641.3900 0.0000 1641.9500 2.1200 ;
      END
   END spi_ro_pll_trim[11]
   PIN spi_ro_pll_trim[10]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1592.6300 0.0000 1593.1899 2.1200 ;
      END
   END spi_ro_pll_trim[10]
   PIN spi_ro_pll_trim[9]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1834.5900 0.0000 1835.1499 2.1200 ;
      END
   END spi_ro_pll_trim[9]
   PIN spi_ro_pll_trim[8]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1673.5900 1842.8450 1674.1499 1844.9650 ;
      END
   END spi_ro_pll_trim[8]
   PIN spi_ro_pll_trim[7]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 805.1100 1842.8450 805.6700 1844.9650 ;
      END
   END spi_ro_pll_trim[7]
   PIN spi_ro_pll_trim[6]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 571.5800 2.2000 572.7800 ;
      END
   END spi_ro_pll_trim[6]
   PIN spi_ro_pll_trim[5]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 676.3100 0.0000 676.8700 2.1200 ;
      END
   END spi_ro_pll_trim[5]
   PIN spi_ro_pll_trim[4]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1047.0699 1842.8450 1047.6300 1844.9650 ;
      END
   END spi_ro_pll_trim[4]
   PIN spi_ro_pll_trim[3]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 893.4300 0.0000 893.9900 2.1200 ;
      END
   END spi_ro_pll_trim[3]
   PIN spi_ro_pll_trim[2]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 749.7400 2.2000 750.9400 ;
      END
   END spi_ro_pll_trim[2]
   PIN spi_ro_pll_trim[1]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 215.2600 2.2000 216.4600 ;
      END
   END spi_ro_pll_trim[1]
   PIN spi_ro_pll_trim[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 628.4700 0.0000 629.0300 2.1200 ;
      END
   END spi_ro_pll_trim[0]
   PIN spi_ro_mfgr_id[11]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1356.2999 2.2000 1357.5000 ;
      END
   END spi_ro_mfgr_id[11]
   PIN spi_ro_mfgr_id[10]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 346.9500 1842.8450 347.5100 1844.9650 ;
      END
   END spi_ro_mfgr_id[10]
   PIN spi_ro_mfgr_id[9]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1263.2700 1842.8450 1263.8300 1844.9650 ;
      END
   END spi_ro_mfgr_id[9]
   PIN spi_ro_mfgr_id[8]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 238.3800 1844.9650 239.5800 ;
      END
   END spi_ro_mfgr_id[8]
   PIN spi_ro_mfgr_id[7]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 523.9800 1844.9650 525.1800 ;
      END
   END spi_ro_mfgr_id[7]
   PIN spi_ro_mfgr_id[6]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 737.5000 1844.9650 738.7000 ;
      END
   END spi_ro_mfgr_id[6]
   PIN spi_ro_mfgr_id[5]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1307.3400 1844.9650 1308.5399 ;
      END
   END spi_ro_mfgr_id[5]
   PIN spi_ro_mfgr_id[4]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1746.2700 1842.8450 1746.8300 1844.9650 ;
      END
   END spi_ro_mfgr_id[4]
   PIN spi_ro_mfgr_id[3]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 393.4200 2.2000 394.6200 ;
      END
   END spi_ro_mfgr_id[3]
   PIN spi_ro_mfgr_id[2]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1448.1899 0.0000 1448.7500 2.1200 ;
      END
   END spi_ro_mfgr_id[2]
   PIN spi_ro_mfgr_id[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1207.1500 0.0000 1207.7100 2.1200 ;
      END
   END spi_ro_mfgr_id[1]
   PIN spi_ro_mfgr_id[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 725.0700 0.0000 725.6300 2.1200 ;
      END
   END spi_ro_mfgr_id[0]
   PIN spi_ro_prod_id[7]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 951.0200 1844.9650 952.2200 ;
      END
   END spi_ro_prod_id[7]
   PIN spi_ro_prod_id[6]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 321.3400 2.2000 322.5400 ;
      END
   END spi_ro_prod_id[6]
   PIN spi_ro_prod_id[5]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 785.1000 2.2000 786.3000 ;
      END
   END spi_ro_prod_id[5]
   PIN spi_ro_prod_id[4]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 60.2200 1844.9650 61.4200 ;
      END
   END spi_ro_prod_id[4]
   PIN spi_ro_prod_id[3]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 345.8200 1844.9650 347.0200 ;
      END
   END spi_ro_prod_id[3]
   PIN spi_ro_prod_id[2]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1712.6200 2.2000 1713.8199 ;
      END
   END spi_ro_prod_id[2]
   PIN spi_ro_prod_id[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1327.6699 0.0000 1328.2300 2.1200 ;
      END
   END spi_ro_prod_id[1]
   PIN spi_ro_prod_id[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 178.5900 1842.8450 179.1500 1844.9650 ;
      END
   END spi_ro_prod_id[0]
   PIN spi_ro_mask_rev[3]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 709.4300 1842.8450 709.9900 1844.9650 ;
      END
   END spi_ro_mask_rev[3]
   PIN spi_ro_mask_rev[2]
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 95.5800 1844.9650 96.7800 ;
      END
   END spi_ro_mask_rev[2]
   PIN spi_ro_mask_rev[1]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 251.2700 1842.8450 251.8300 1844.9650 ;
      END
   END spi_ro_mask_rev[1]
   PIN spi_ro_mask_rev[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1118.8300 1842.8450 1119.3900 1844.9650 ;
      END
   END spi_ro_mask_rev[0]
   PIN ser_tx
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1106.0599 2.2000 1107.2600 ;
      END
   END ser_tx
   PIN ser_rx
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1522.2200 1844.9650 1523.4199 ;
      END
   END ser_rx
   PIN irq_pin
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 179.9000 2.2000 181.1000 ;
      END
   END irq_pin
   PIN irq_spi
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1254.9900 0.0000 1255.5499 2.1200 ;
      END
   END irq_spi
   PIN trap
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 105.9100 1842.8450 106.4700 1844.9650 ;
      END
   END trap
   PIN flash_csb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1553.0699 1842.8450 1553.6300 1844.9650 ;
      END
   END flash_csb
   PIN flash_clk
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 1628.2999 1844.9650 1629.5000 ;
      END
   END flash_clk
   PIN flash_csb_oeb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1319.5800 2.2000 1320.7800 ;
      END
   END flash_csb_oeb
   PIN flash_clk_oeb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 990.0300 0.0000 990.5900 2.1200 ;
      END
   END flash_clk_oeb
   PIN flash_io0_oeb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1176.7800 2.2000 1177.9800 ;
      END
   END flash_io0_oeb
   PIN flash_io1_oeb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 998.6200 2.2000 999.8200 ;
      END
   END flash_io1_oeb
   PIN flash_io2_oeb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 1568.7100 0.0000 1569.2700 2.1200 ;
      END
   END flash_io2_oeb
   PIN flash_io3_oeb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1605.1799 2.2000 1606.3800 ;
      END
   END flash_io3_oeb
   PIN flash_csb_ieb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 146.3900 0.0000 146.9500 2.1200 ;
      END
   END flash_csb_ieb
   PIN flash_clk_ieb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 892.5400 2.2000 893.7400 ;
      END
   END flash_clk_ieb
   PIN flash_io0_ieb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 130.9400 1844.9650 132.1400 ;
      END
   END flash_io0_ieb
   PIN flash_io1_ieb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 1391.6599 2.2000 1392.8600 ;
      END
   END flash_io1_ieb
   PIN flash_io2_ieb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 416.5400 1844.9650 417.7400 ;
      END
   END flash_io2_ieb
   PIN flash_io3_ieb
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 81.9900 1842.8450 82.5500 1844.9650 ;
      END
   END flash_io3_ieb
   PIN flash_io0_do
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 772.8600 1844.9650 774.0600 ;
      END
   END flash_io0_do
   PIN flash_io1_do
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 555.7900 0.0000 556.3500 2.1200 ;
      END
   END flash_io1_do
   PIN flash_io2_do
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met3 ;
	    RECT 1842.7650 666.7800 1844.9650 667.9800 ;
      END
   END flash_io2_do
   PIN flash_io3_do
      DIRECTION OUTPUT TRISTATE ;
      PORT
         LAYER met2 ;
	    RECT 974.3900 1842.8450 974.9500 1844.9650 ;
      END
   END flash_io3_do
   PIN flash_io0_di
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1062.7100 0.0000 1063.2700 2.1200 ;
      END
   END flash_io0_di
   PIN flash_io1_di
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1303.7500 0.0000 1304.3099 2.1200 ;
      END
   END flash_io1_di
   PIN flash_io2_di
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
	    RECT 1505.2300 1842.8450 1505.7899 1844.9650 ;
      END
   END flash_io2_di
   PIN flash_io3_di
      DIRECTION INPUT ;
      PORT
         LAYER met3 ;
	    RECT 0.0000 820.4600 2.2000 821.6600 ;
      END
   END flash_io3_di
   OBS
         LAYER li1 ;
	    RECT 7.5200 2.0850 1839.0950 1839.2749 ;
         LAYER met1 ;
	    RECT 2.5300 2.0400 1842.3900 1843.0599 ;
         LAYER met2 ;
	    RECT 2.0900 1842.7050 9.1700 1843.0900 ;
	    RECT 10.0100 1842.7050 34.0100 1843.0900 ;
	    RECT 34.8500 1842.7050 57.9300 1843.0900 ;
	    RECT 58.7700 1842.7050 81.8500 1843.0900 ;
	    RECT 82.6900 1842.7050 105.7700 1843.0900 ;
	    RECT 106.6100 1842.7050 130.6100 1843.0900 ;
	    RECT 131.4500 1842.7050 154.5300 1843.0900 ;
	    RECT 155.3700 1842.7050 178.4500 1843.0900 ;
	    RECT 179.2900 1842.7050 202.3700 1843.0900 ;
	    RECT 203.2100 1842.7050 226.2900 1843.0900 ;
	    RECT 227.1300 1842.7050 251.1300 1843.0900 ;
	    RECT 251.9700 1842.7050 275.0500 1843.0900 ;
	    RECT 275.8900 1842.7050 298.9700 1843.0900 ;
	    RECT 299.8100 1842.7050 322.8900 1843.0900 ;
	    RECT 323.7300 1842.7050 346.8100 1843.0900 ;
	    RECT 347.6500 1842.7050 371.6500 1843.0900 ;
	    RECT 372.4900 1842.7050 395.5700 1843.0900 ;
	    RECT 396.4100 1842.7050 419.4900 1843.0900 ;
	    RECT 420.3300 1842.7050 443.4100 1843.0900 ;
	    RECT 444.2500 1842.7050 467.3300 1843.0900 ;
	    RECT 468.1700 1842.7050 492.1700 1843.0900 ;
	    RECT 493.0100 1842.7050 516.0900 1843.0900 ;
	    RECT 516.9300 1842.7050 540.0100 1843.0900 ;
	    RECT 540.8500 1842.7050 563.9300 1843.0900 ;
	    RECT 564.7700 1842.7050 588.7700 1843.0900 ;
	    RECT 589.6100 1842.7050 612.6900 1843.0900 ;
	    RECT 613.5300 1842.7050 636.6100 1843.0900 ;
	    RECT 637.4500 1842.7050 660.5300 1843.0900 ;
	    RECT 661.3700 1842.7050 684.4500 1843.0900 ;
	    RECT 685.2900 1842.7050 709.2900 1843.0900 ;
	    RECT 710.1300 1842.7050 733.2100 1843.0900 ;
	    RECT 734.0500 1842.7050 757.1300 1843.0900 ;
	    RECT 757.9700 1842.7050 781.0500 1843.0900 ;
	    RECT 781.8900 1842.7050 804.9700 1843.0900 ;
	    RECT 805.8100 1842.7050 829.8100 1843.0900 ;
	    RECT 830.6500 1842.7050 853.7300 1843.0900 ;
	    RECT 854.5700 1842.7050 877.6500 1843.0900 ;
	    RECT 878.4900 1842.7050 901.5700 1843.0900 ;
	    RECT 902.4100 1842.7050 925.4900 1843.0900 ;
	    RECT 926.3300 1842.7050 950.3300 1843.0900 ;
	    RECT 951.1700 1842.7050 974.2500 1843.0900 ;
	    RECT 975.0900 1842.7050 998.1700 1843.0900 ;
	    RECT 999.0099 1842.7050 1022.0900 1843.0900 ;
	    RECT 1022.9300 1842.7050 1046.9299 1843.0900 ;
	    RECT 1047.7700 1842.7050 1070.8500 1843.0900 ;
	    RECT 1071.6899 1842.7050 1094.7700 1843.0900 ;
	    RECT 1095.6100 1842.7050 1118.6899 1843.0900 ;
	    RECT 1119.5300 1842.7050 1142.6100 1843.0900 ;
	    RECT 1143.4500 1842.7050 1167.4500 1843.0900 ;
	    RECT 1168.2899 1842.7050 1191.3700 1843.0900 ;
	    RECT 1192.2100 1842.7050 1215.2899 1843.0900 ;
	    RECT 1216.1300 1842.7050 1239.2100 1843.0900 ;
	    RECT 1240.0499 1842.7050 1263.1300 1843.0900 ;
	    RECT 1263.9700 1842.7050 1287.9700 1843.0900 ;
	    RECT 1288.8099 1842.7050 1311.8900 1843.0900 ;
	    RECT 1312.7300 1842.7050 1335.8099 1843.0900 ;
	    RECT 1336.6500 1842.7050 1359.7300 1843.0900 ;
	    RECT 1360.5699 1842.7050 1383.6500 1843.0900 ;
	    RECT 1384.4900 1842.7050 1408.4900 1843.0900 ;
	    RECT 1409.3300 1842.7050 1432.4099 1843.0900 ;
	    RECT 1433.2500 1842.7050 1456.3300 1843.0900 ;
	    RECT 1457.1699 1842.7050 1480.2500 1843.0900 ;
	    RECT 1481.0900 1842.7050 1505.0900 1843.0900 ;
	    RECT 1505.9299 1842.7050 1529.0100 1843.0900 ;
	    RECT 1529.8500 1842.7050 1552.9299 1843.0900 ;
	    RECT 1553.7700 1842.7050 1576.8500 1843.0900 ;
	    RECT 1577.6899 1842.7050 1600.7700 1843.0900 ;
	    RECT 1601.6100 1842.7050 1625.6100 1843.0900 ;
	    RECT 1626.4500 1842.7050 1649.5299 1843.0900 ;
	    RECT 1650.3700 1842.7050 1673.4500 1843.0900 ;
	    RECT 1674.2899 1842.7050 1697.3700 1843.0900 ;
	    RECT 1698.2100 1842.7050 1721.2899 1843.0900 ;
	    RECT 1722.1300 1842.7050 1746.1300 1843.0900 ;
	    RECT 1746.9700 1842.7050 1770.0499 1843.0900 ;
	    RECT 1770.8900 1842.7050 1793.9700 1843.0900 ;
	    RECT 1794.8099 1842.7050 1817.8900 1843.0900 ;
	    RECT 1818.7300 1842.7050 1841.8099 1843.0900 ;
	    RECT 2.0900 2.2600 1842.3600 1842.7050 ;
	    RECT 2.6500 1.9900 25.7300 2.2600 ;
	    RECT 26.5700 1.9900 49.6500 2.2600 ;
	    RECT 50.4900 1.9900 73.5700 2.2600 ;
	    RECT 74.4100 1.9900 97.4900 2.2600 ;
	    RECT 98.3300 1.9900 122.3300 2.2600 ;
	    RECT 123.1700 1.9900 146.2500 2.2600 ;
	    RECT 147.0900 1.9900 170.1700 2.2600 ;
	    RECT 171.0100 1.9900 194.0900 2.2600 ;
	    RECT 194.9300 1.9900 218.0100 2.2600 ;
	    RECT 218.8500 1.9900 242.8500 2.2600 ;
	    RECT 243.6900 1.9900 266.7700 2.2600 ;
	    RECT 267.6100 1.9900 290.6900 2.2600 ;
	    RECT 291.5300 1.9900 314.6100 2.2600 ;
	    RECT 315.4500 1.9900 338.5300 2.2600 ;
	    RECT 339.3700 1.9900 363.3700 2.2600 ;
	    RECT 364.2100 1.9900 387.2900 2.2600 ;
	    RECT 388.1300 1.9900 411.2100 2.2600 ;
	    RECT 412.0500 1.9900 435.1300 2.2600 ;
	    RECT 435.9700 1.9900 459.9700 2.2600 ;
	    RECT 460.8100 1.9900 483.8900 2.2600 ;
	    RECT 484.7300 1.9900 507.8100 2.2600 ;
	    RECT 508.6500 1.9900 531.7300 2.2600 ;
	    RECT 532.5700 1.9900 555.6500 2.2600 ;
	    RECT 556.4900 1.9900 580.4900 2.2600 ;
	    RECT 581.3300 1.9900 604.4100 2.2600 ;
	    RECT 605.2500 1.9900 628.3300 2.2600 ;
	    RECT 629.1700 1.9900 652.2500 2.2600 ;
	    RECT 653.0900 1.9900 676.1700 2.2600 ;
	    RECT 677.0100 1.9900 701.0100 2.2600 ;
	    RECT 701.8500 1.9900 724.9300 2.2600 ;
	    RECT 725.7700 1.9900 748.8500 2.2600 ;
	    RECT 749.6900 1.9900 772.7700 2.2600 ;
	    RECT 773.6100 1.9900 796.6900 2.2600 ;
	    RECT 797.5300 1.9900 821.5300 2.2600 ;
	    RECT 822.3700 1.9900 845.4500 2.2600 ;
	    RECT 846.2900 1.9900 869.3700 2.2600 ;
	    RECT 870.2100 1.9900 893.2900 2.2600 ;
	    RECT 894.1300 1.9900 918.1300 2.2600 ;
	    RECT 918.9700 1.9900 942.0500 2.2600 ;
	    RECT 942.8900 1.9900 965.9700 2.2600 ;
	    RECT 966.8100 1.9900 989.8900 2.2600 ;
	    RECT 990.7300 1.9900 1013.8100 2.2600 ;
	    RECT 1014.6500 1.9900 1038.6500 2.2600 ;
	    RECT 1039.4900 1.9900 1062.5699 2.2600 ;
	    RECT 1063.4100 1.9900 1086.4900 2.2600 ;
	    RECT 1087.3300 1.9900 1110.4100 2.2600 ;
	    RECT 1111.2500 1.9900 1134.3300 2.2600 ;
	    RECT 1135.1699 1.9900 1159.1699 2.2600 ;
	    RECT 1160.0100 1.9900 1183.0900 2.2600 ;
	    RECT 1183.9299 1.9900 1207.0100 2.2600 ;
	    RECT 1207.8500 1.9900 1230.9299 2.2600 ;
	    RECT 1231.7700 1.9900 1254.8500 2.2600 ;
	    RECT 1255.6899 1.9900 1279.6899 2.2600 ;
	    RECT 1280.5300 1.9900 1303.6100 2.2600 ;
	    RECT 1304.4500 1.9900 1327.5300 2.2600 ;
	    RECT 1328.3700 1.9900 1351.4500 2.2600 ;
	    RECT 1352.2899 1.9900 1376.2899 2.2600 ;
	    RECT 1377.1300 1.9900 1400.2100 2.2600 ;
	    RECT 1401.0499 1.9900 1424.1300 2.2600 ;
	    RECT 1424.9700 1.9900 1448.0499 2.2600 ;
	    RECT 1448.8900 1.9900 1471.9700 2.2600 ;
	    RECT 1472.8099 1.9900 1496.8099 2.2600 ;
	    RECT 1497.6500 1.9900 1520.7300 2.2600 ;
	    RECT 1521.5699 1.9900 1544.6500 2.2600 ;
	    RECT 1545.4900 1.9900 1568.5699 2.2600 ;
	    RECT 1569.4099 1.9900 1592.4900 2.2600 ;
	    RECT 1593.3300 1.9900 1617.3300 2.2600 ;
	    RECT 1618.1699 1.9900 1641.2500 2.2600 ;
	    RECT 1642.0900 1.9900 1665.1699 2.2600 ;
	    RECT 1666.0100 1.9900 1689.0900 2.2600 ;
	    RECT 1689.9299 1.9900 1713.0100 2.2600 ;
	    RECT 1713.8500 1.9900 1737.8500 2.2600 ;
	    RECT 1738.6899 1.9900 1761.7700 2.2600 ;
	    RECT 1762.6100 1.9900 1785.6899 2.2600 ;
	    RECT 1786.5299 1.9900 1809.6100 2.2600 ;
	    RECT 1810.4500 1.9900 1834.4500 2.2600 ;
	    RECT 1835.2899 1.9900 1842.3600 2.2600 ;
         LAYER met3 ;
	    RECT 1.9100 1820.2000 1842.7650 1835.6000 ;
	    RECT 2.5000 1818.3999 1842.7650 1820.2000 ;
	    RECT 1.9100 1807.9600 1842.7650 1818.3999 ;
	    RECT 1.9100 1806.1599 1842.4650 1807.9600 ;
	    RECT 1.9100 1784.8400 1842.7650 1806.1599 ;
	    RECT 2.5000 1783.0399 1842.7650 1784.8400 ;
	    RECT 1.9100 1772.6000 1842.7650 1783.0399 ;
	    RECT 1.9100 1770.7999 1842.4650 1772.6000 ;
	    RECT 1.9100 1749.4800 1842.7650 1770.7999 ;
	    RECT 2.5000 1747.6799 1842.7650 1749.4800 ;
	    RECT 1.9100 1737.2400 1842.7650 1747.6799 ;
	    RECT 1.9100 1735.4399 1842.4650 1737.2400 ;
	    RECT 1.9100 1714.1200 1842.7650 1735.4399 ;
	    RECT 2.5000 1712.3199 1842.7650 1714.1200 ;
	    RECT 1.9100 1701.8800 1842.7650 1712.3199 ;
	    RECT 1.9100 1700.0800 1842.4650 1701.8800 ;
	    RECT 1.9100 1677.3999 1842.7650 1700.0800 ;
	    RECT 2.5000 1675.6000 1842.7650 1677.3999 ;
	    RECT 1.9100 1665.1599 1842.7650 1675.6000 ;
	    RECT 1.9100 1663.3600 1842.4650 1665.1599 ;
	    RECT 1.9100 1642.0399 1842.7650 1663.3600 ;
	    RECT 2.5000 1640.2400 1842.7650 1642.0399 ;
	    RECT 1.9100 1629.7999 1842.7650 1640.2400 ;
	    RECT 1.9100 1628.0000 1842.4650 1629.7999 ;
	    RECT 1.9100 1606.6799 1842.7650 1628.0000 ;
	    RECT 2.5000 1604.8800 1842.7650 1606.6799 ;
	    RECT 1.9100 1594.4399 1842.7650 1604.8800 ;
	    RECT 1.9100 1592.6400 1842.4650 1594.4399 ;
	    RECT 1.9100 1571.3199 1842.7650 1592.6400 ;
	    RECT 2.5000 1569.5200 1842.7650 1571.3199 ;
	    RECT 1.9100 1559.0800 1842.7650 1569.5200 ;
	    RECT 1.9100 1557.2799 1842.4650 1559.0800 ;
	    RECT 1.9100 1535.9600 1842.7650 1557.2799 ;
	    RECT 2.5000 1534.1599 1842.7650 1535.9600 ;
	    RECT 1.9100 1523.7200 1842.7650 1534.1599 ;
	    RECT 1.9100 1521.9199 1842.4650 1523.7200 ;
	    RECT 1.9100 1499.2400 1842.7650 1521.9199 ;
	    RECT 2.5000 1497.4399 1842.7650 1499.2400 ;
	    RECT 1.9100 1487.0000 1842.7650 1497.4399 ;
	    RECT 1.9100 1485.2000 1842.4650 1487.0000 ;
	    RECT 1.9100 1463.8800 1842.7650 1485.2000 ;
	    RECT 2.5000 1462.0800 1842.7650 1463.8800 ;
	    RECT 1.9100 1451.6400 1842.7650 1462.0800 ;
	    RECT 1.9100 1449.8400 1842.4650 1451.6400 ;
	    RECT 1.9100 1428.5200 1842.7650 1449.8400 ;
	    RECT 2.5000 1426.7200 1842.7650 1428.5200 ;
	    RECT 1.9100 1416.2800 1842.7650 1426.7200 ;
	    RECT 1.9100 1414.4800 1842.4650 1416.2800 ;
	    RECT 1.9100 1393.1599 1842.7650 1414.4800 ;
	    RECT 2.5000 1391.3600 1842.7650 1393.1599 ;
	    RECT 1.9100 1380.9199 1842.7650 1391.3600 ;
	    RECT 1.9100 1379.1200 1842.4650 1380.9199 ;
	    RECT 1.9100 1357.7999 1842.7650 1379.1200 ;
	    RECT 2.5000 1356.0000 1842.7650 1357.7999 ;
	    RECT 1.9100 1345.5599 1842.7650 1356.0000 ;
	    RECT 1.9100 1343.7600 1842.4650 1345.5599 ;
	    RECT 1.9100 1321.0800 1842.7650 1343.7600 ;
	    RECT 2.5000 1319.2800 1842.7650 1321.0800 ;
	    RECT 1.9100 1308.8400 1842.7650 1319.2800 ;
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   END
END striVe_soc