| /root/zero_to_asic_course_group_submission_mpw5/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/docs/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/docs/environment.yml |
| /root/zero_to_asic_course_group_submission_mpw5/docs/source/conf.py |
| /root/zero_to_asic_course_group_submission_mpw5/docs/source/index.rst |
| /root/zero_to_asic_course_group_submission_mpw5/docs/source/quickstart.rst |
| /root/zero_to_asic_course_group_submission_mpw5/openlane/user_project_wrapper/config.json |
| /root/zero_to_asic_course_group_submission_mpw5/openlane/user_project_wrapper/config.tcl |
| /root/zero_to_asic_course_group_submission_mpw5/openlane/user_project_wrapper/extra_lef_gds.tcl |
| /root/zero_to_asic_course_group_submission_mpw5/openlane/user_project_wrapper/obstruction.tcl |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/user_proj_example.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/user_project_wrapper.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wb_bridge_2way.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wb_openram_wrapper.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_acorn_prng.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_alu74181.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_frequency_counter.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_function_generator.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_hack_soc_dffram.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_hsv_mixer.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_rgb_mixer.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_teras.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_vga_clock.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdc/wrapped_vgademo_on_fpga.sdc |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/user_proj_example.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/user_project_wrapper.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wb_bridge_2way.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wb_openram_wrapper.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_acorn_prng.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_alu74181.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_frequency_counter.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_function_generator.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_hack_soc_dffram.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_hsv_mixer.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_rgb_mixer.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_teras.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_vga_clock.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/sdf/wrapped_vgademo_on_fpga.sdf |
| /root/zero_to_asic_course_group_submission_mpw5/spef/user_proj_example.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/user_project_wrapper.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wb_bridge_2way.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wb_openram_wrapper.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_acorn_prng.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_alu74181.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_frequency_counter.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_function_generator.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_hack_soc_dffram.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_hsv_mixer.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_rgb_mixer.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_teras.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_vga_clock.spef |
| /root/zero_to_asic_course_group_submission_mpw5/spef/wrapped_vgademo_on_fpga.spef |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/io_ports/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/io_ports/io_ports.c |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/io_ports/io_ports_tb.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/la_test1/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/la_test1/la_test1.c |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/la_test1/la_test1_tb.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/la_test2/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/la_test2/la_test2.c |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/la_test2/la_test2_tb.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/mprj_stimulus/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/wb_port/Makefile |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/wb_port/wb_port.c |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/dv/wb_port/wb_port_tb.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/includes/includes.gl.caravel_user_project |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/includes/includes.rtl.caravel_user_project |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/rtl/uprj_netlists.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/rtl/user_proj_example.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/rtl/user_project_includes.v |
| /root/zero_to_asic_course_group_submission_mpw5/verilog/rtl/user_project_wrapper.v |