)]}'
{
  "commit": "c5ae4a487fd9e03a9d1b7e6c5c9bbe3961a92979",
  "tree": "776fc9ec6d3a6b211b8db78e9869861625eeea56",
  "parents": [
    "87403da9df454e3201a1d7eca2cd01cbfcc41ab7"
  ],
  "author": {
    "name": "Thorsten Knoll",
    "email": "thorsten_knoll@yahoo.de",
    "time": "Sat Dec 31 18:50:54 2022 +0000"
  },
  "committer": {
    "name": "Thorsten Knoll",
    "email": "thorsten_knoll@yahoo.de",
    "time": "Sat Dec 31 19:03:45 2022 +0000"
  },
  "message": "added verilog. update info.yaml\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "baccf021718ad678ed9042cd6b32cbf90e48446e",
      "old_mode": 33188,
      "old_path": "info.yaml",
      "new_id": "10be67a390e8026bc5d7a20e6e7e2652656235e0",
      "new_mode": 33188,
      "new_path": "info.yaml"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8707136a6ab21fbaeb3d49f945114b5cf65bfe3f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/vga_clock.v"
    }
  ]
}