)]}'
{
  "commit": "03cf93722ed28bf6efc20f3254640309583b81a4",
  "tree": "a6bc6c9c308387b1e2461009a90b7e6619a284d7",
  "parents": [
    "4d5f066660476fc9bf80c047e8113375a96540cb"
  ],
  "author": {
    "name": "Thorsten Knoll",
    "email": "thorsten_knoll@yahoo.de",
    "time": "Sat Dec 31 20:03:11 2022 +0000"
  },
  "committer": {
    "name": "Thorsten Knoll",
    "email": "thorsten_knoll@yahoo.de",
    "time": "Sat Dec 31 20:03:11 2022 +0000"
  },
  "message": "update config.json\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8707136a6ab21fbaeb3d49f945114b5cf65bfe3f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/vga_clock.v",
      "new_id": "0bc62fba71d67795cfbe1371850a8935576cf1ce",
      "new_mode": 33188,
      "new_path": "verilog/rtl/vga_clock.v"
    }
  ]
}