sdc/int_ram.sdc

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# Created by write_sdc
# Sat Dec 31 00:22:04 2022
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current_design int_ram
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# Timing Constraints
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create_clock -name i_clk -period 10.0000 [get_ports {i_clk}]
set_clock_transition 0.1500 [get_clocks {i_clk}]
set_clock_uncertainty 0.2500 i_clk
set_propagated_clock [get_clocks {i_clk}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[0]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[10]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[11]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[12]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[13]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[14]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[15]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[1]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[2]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[3]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[4]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[5]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[6]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[7]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[8]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_data[9]}]
set_input_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {i_we}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[0]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[10]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[11]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[12]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[13]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[14]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[15]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[1]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[2]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[3]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[4]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[5]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[6]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[7]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[8]}]
set_output_delay 2.0000 -clock [get_clocks {i_clk}] -add_delay [get_ports {o_data[9]}]
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# Environment
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set_load -pin_load 0.0334 [get_ports {o_data[15]}]
set_load -pin_load 0.0334 [get_ports {o_data[14]}]
set_load -pin_load 0.0334 [get_ports {o_data[13]}]
set_load -pin_load 0.0334 [get_ports {o_data[12]}]
set_load -pin_load 0.0334 [get_ports {o_data[11]}]
set_load -pin_load 0.0334 [get_ports {o_data[10]}]
set_load -pin_load 0.0334 [get_ports {o_data[9]}]
set_load -pin_load 0.0334 [get_ports {o_data[8]}]
set_load -pin_load 0.0334 [get_ports {o_data[7]}]
set_load -pin_load 0.0334 [get_ports {o_data[6]}]
set_load -pin_load 0.0334 [get_ports {o_data[5]}]
set_load -pin_load 0.0334 [get_ports {o_data[4]}]
set_load -pin_load 0.0334 [get_ports {o_data[3]}]
set_load -pin_load 0.0334 [get_ports {o_data[2]}]
set_load -pin_load 0.0334 [get_ports {o_data[1]}]
set_load -pin_load 0.0334 [get_ports {o_data[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_data[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
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# Design Rules
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set_max_fanout 10.0000 [current_design]