CVC: Circuit Validation Check  Version 1.1.4
CVC: Log output to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/reports/signoff/core.rpt
CVC: Error output to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/reports/signoff/core.rpt.error.gz
CVC: Debug output to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/reports/signoff/core.rpt.debug.gz
CVC: Start: Mon Dec 26 18:33:28 2022

Using the following parameters for CVC (Circuit Validation Check) from /home/piotro/opt/silicon/pdks/sky130A/libs.tech/openlane/cvc/cvcrc
CVC_TOP = 'core'
CVC_NETLIST = '/home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/signoff/core.cdl'
CVC_MODE = 'core'
CVC_MODEL_FILE = '/home/piotro/opt/silicon/pdks/sky130A/libs.tech/openlane/cvc/models'
CVC_POWER_FILE = '/home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/signoff/core.power'
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = '/home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/reports/signoff/core.rpt'
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters

CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/signoff/core.cdl

Cdl fixed data size 573404
Usage CDL: Time: 0  Memory: 31652  I/O: 8  Swap: 0
CVC: Counting and linking...
Fatal error:could not find subcircuit: XFILLER_79_380(sky130_ef_sc_hd__decap_12) in core