{
    "DESIGN_NAME": "user_project_wrapper",
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/user_project_wrapper.v",
        "dir::../../verilog/rtl/ppcpu/rtl/top.v"
    ],
    "CLOCK_PERIOD": 12,
    "CLOCK_PORT": "user_clock2",
    "CLOCK_NET": "mprj.clk",
    "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
    "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
    
    "VERILOG_FILES_BLACKBOX": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/ppcpu/rtl/core/core.v",
        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/interconnect_inner.v",
        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/interconnect_outer.v",
        "dir::../../verilog/rtl/ppcpu/rtl/dcache/dcache.v",
        "dir::../../verilog/rtl/ppcpu/rtl/icache/icache.v",
        "pdk_dir::libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
    ],
    "EXTRA_LEFS": [
        "dir::../../lef/core0.lef",
        "dir::../../lef/core1.lef",
        "dir::../../lef/dcache.lef",
        "dir::../../lef/icache.lef",
        "dir::../../lef/interconnect_inner.lef",
        "dir::../../lef/interconnect_outer.lef",
        "pdk_dir::libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
    ], 
    "EXTRA_S_FILES": [
        "dir::../../gds/core0.gds",
        "dir::../../gds/core1.gds",
        "dir::../../gds/dcache.gds",
        "dir::../../gds/icache.gds",
        "dir::../../gds/interconnect_inner.gds",
        "dir::../../gds/interconnect_outer.gds",
        "pdk_dir::libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
    ],
    "EXTRA_LIBS": [
        "dir::../../lib/core0.lib",
        "dir::../../lib/core1.lib",
        "dir::../../lib/dcache.lib",
        "dir::../../lib/icache.lib",
        "dir::../../lib/interconnect_inner.lib",
        "dir::../../lib/interconnect_outer.lib",
        "pdk_dir::libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8.lib"
    ],
    
    "FP_PDN_CHECK_NODES": 0,
    "SYNTH_ELABORATE_ONLY": 1,
    "PL_RANDOM_GLB_PLACEMENT": 1,
    "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
    "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
    "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
    "FP_PDN_ENABLE_RAILS": 0,
    "DIODE_INSERTION_STRATEGY": 0,
    "RUN_FILL_INSERTION": 0,
    "RUN_TAP_DECAP_INSERTION": 0,
    "FP_PDN_VPITCH": 180,
    "FP_PDN_HPITCH": 180,
    "CLOCK_TREE_SYNTH": 0,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "MAGIC_ZEROIZE_ORIGIN": 0,
    "FP_SIZING": "absolute",
    "RUN_CVC": 0,
    "UNIT": "2.4",
    "FP_IO_VEXTEND": "expr::2 * $UNIT",
    "FP_IO_HEXTEND": "expr::2 * $UNIT",
    "FP_IO_VLENGTH": "ref::$UNIT",
    "FP_IO_HLENGTH": "ref::$UNIT",
    "FP_IO_VTHICKNESS_MULT": 4,
    "FP_IO_HTHICKNESS_MULT": 4,
    "FP_PDN_CORE_RING": 1,
    "FP_PDN_CORE_RING_VWIDTH": 3.1,
    "FP_PDN_CORE_RING_HWIDTH": 3.1,
    "FP_PDN_CORE_RING_VOFFSET": 12.45,
    "FP_PDN_CORE_RING_HOFFSET": 12.45,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "FP_PDN_VWIDTH": 3.1,
    "FP_PDN_HWIDTH": 3.1,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
    "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
    "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "pdk::sky130*": {
        "RT_MAX_LAYER": "met4",
        "DIE_AREA": "0 0 2920 3520",
        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hdll": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 8
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 10,
            "SYNTH_MAX_FANOUT": 5
        },
        "scl::sky130_fd_sc_ms": {
            "CLOCK_PERIOD": 10
        }
    },
   "ROUTING_CORES": 6
}