diff --git a/openlane/core0/config.json b/openlane/core0/config.json
new file mode 100644
index 0000000..28b74f3
--- /dev/null
+++ b/openlane/core0/config.json
@@ -0,0 +1,53 @@
+{
+    "DESIGN_NAME": "core0",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/core.v",
+
+        "dir::../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/alu.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/decode.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/execute.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/fetch.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/memwb.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/pc.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/rf.v"
+    ],
+    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": "i_clk",
+    "CLOCK_NET": "i_clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 400 800",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.26,
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
+    "pdk::sky130*": {
+        "FP_CORE_UTIL": 45,
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "PL_RESIZER_SETUP_SLACK_MARGIN": 0.2,
+    "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.8,
+    "ROUTING_CORES": 6
+}
diff --git a/openlane/core0/pin_order.cfg b/openlane/core0/pin_order.cfg
new file mode 100644
index 0000000..56d3119
--- /dev/null
+++ b/openlane/core0/pin_order.cfg
@@ -0,0 +1,4 @@
+#BUS_SORT
+
+#E
+.*
diff --git a/openlane/core1/config.json b/openlane/core1/config.json
new file mode 100644
index 0000000..dc6ef79
--- /dev/null
+++ b/openlane/core1/config.json
@@ -0,0 +1,53 @@
+{
+    "DESIGN_NAME": "core1",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/core.v",
+
+        "dir::../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/alu.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/decode.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/execute.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/fetch.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/memwb.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/pc.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/rf.v"
+    ],
+    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": "i_clk",
+    "CLOCK_NET": "i_clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 400 800",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.26,
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
+    "pdk::sky130*": {
+        "FP_CORE_UTIL": 45,
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "PL_RESIZER_SETUP_SLACK_MARGIN": 0.2,
+    "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.8,
+    "ROUTING_CORES": 6
+}
diff --git a/openlane/core1/pin_order.cfg b/openlane/core1/pin_order.cfg
new file mode 100644
index 0000000..56d3119
--- /dev/null
+++ b/openlane/core1/pin_order.cfg
@@ -0,0 +1,4 @@
+#BUS_SORT
+
+#E
+.*
diff --git a/openlane/dcache/config.json b/openlane/dcache/config.json
new file mode 100644
index 0000000..37da70a
--- /dev/null
+++ b/openlane/dcache/config.json
@@ -0,0 +1,31 @@
+{
+    "DESIGN_NAME": "dcache",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v", 
+        "dir::../../verilog/rtl/ppcpu/rtl/dcache/dcache.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/dcache/dcache_ram.v"
+    ],
+    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
+    "CLOCK_PERIOD": 12,
+    "CLOCK_PORT": "i_clk",
+    "CLOCK_NET": "i_clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 1450 1400",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.26,
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
+    "RT_MAX_LAYER": "met4",
+    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.8,
+    "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.8,
+    "PL_RESIZER_SETUP_SLACK_MARGIN": 3,
+    "GLB_RESIZER_SETUP_SLACK_MARGIN": 3,
+    "PL_RESIZER_SETUP_MAX_BUFFER_PERCENT": 80,
+    "GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT": 80,
+    "SYNTH_STRATEGY": "DELAY 4",
+    "ROUTING_CORES": 6
+}
diff --git a/openlane/dcache/pin_order.cfg b/openlane/dcache/pin_order.cfg
new file mode 100644
index 0000000..912bc61
--- /dev/null
+++ b/openlane/dcache/pin_order.cfg
@@ -0,0 +1,4 @@
+#BUS_SORT
+
+#W
+.*
diff --git a/openlane/icache/config.json b/openlane/icache/config.json
new file mode 100644
index 0000000..0a06059
--- /dev/null
+++ b/openlane/icache/config.json
@@ -0,0 +1,47 @@
+{
+    "DESIGN_NAME": "icache",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v", 
+        "dir::../../verilog/rtl/ppcpu/rtl/icache/icache.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/icache/icache_ram.v"
+    ],
+    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": "i_clk",
+    "CLOCK_NET": "i_clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 1600 600",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.30,
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
+    "pdk::sky130*": {
+        "FP_CORE_UTIL": 45,
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.7,
+    "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.7,
+    "PL_RESIZER_SETUP_SLACK_MARGIN": 1.5,
+    "GLB_RESIZER_SETUP_SLACK_MARGIN": 2,
+    "ROUTING_CORES": 6
+}
diff --git a/openlane/icache/pin_order.cfg b/openlane/icache/pin_order.cfg
new file mode 100644
index 0000000..912bc61
--- /dev/null
+++ b/openlane/icache/pin_order.cfg
@@ -0,0 +1,4 @@
+#BUS_SORT
+
+#W
+.*
diff --git a/openlane/interconnect_inner/config.json b/openlane/interconnect_inner/config.json
new file mode 100644
index 0000000..38938a5
--- /dev/null
+++ b/openlane/interconnect_inner/config.json
@@ -0,0 +1,48 @@
+{
+    "DESIGN_NAME": "interconnect_inner",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/interconnect_inner.v",
+
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/inner/dmmu.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/inner/immu.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/inner/intercore_sregs.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/inner/mem_dcache_arb.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/inner/wishbone_arbiter.v"
+    ],
+    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": "core_clock",
+    "CLOCK_NET": "core_clock",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 300 800",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.25,
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
+    "pdk::sky130*": {
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "ROUTING_CORES": 6
+}
diff --git a/openlane/interconnect_inner/pin_order.cfg b/openlane/interconnect_inner/pin_order.cfg
new file mode 100644
index 0000000..74b1bf4
--- /dev/null
+++ b/openlane/interconnect_inner/pin_order.cfg
@@ -0,0 +1,16 @@
+#BUS_SORT
+
+#N
+core.*
+inner.*
+
+#W
+c0.*
+c1.*
+
+#E
+ic0.*
+ic1.*
+
+#S
+dcache.*
diff --git a/openlane/interconnect_outer/config.json b/openlane/interconnect_outer/config.json
new file mode 100644
index 0000000..856a967
--- /dev/null
+++ b/openlane/interconnect_outer/config.json
@@ -0,0 +1,53 @@
+{
+    "DESIGN_NAME": "interconnect_outer",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v", 
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/interconnect_outer.v",
+
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/outer/clk_div.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/outer/ff_mb_sync.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/outer/reset_sync.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/outer/wb_compressor.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/outer/wb_cross_clk.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/embed/gpio.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/embed/sspi.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/inner/wishbone_arbiter.v"
+    ],
+    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": "user_clock2",
+    "CLOCK_NET": "user_clock2 soc_clock cw_clk core_clock",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 300 400",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.35,
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
+    "pdk::sky130*": {
+        "FP_CORE_UTIL": 45,
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.5,
+    "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.5,
+    "ROUTING_CORES": 6
+}
diff --git a/openlane/interconnect_outer/pin_order.cfg b/openlane/interconnect_outer/pin_order.cfg
new file mode 100644
index 0000000..51d57b6
--- /dev/null
+++ b/openlane/interconnect_outer/pin_order.cfg
@@ -0,0 +1,14 @@
+#BUS_SORT
+
+#N
+mgt.*
+m_io.*
+la.*
+irq.*
+user.*
+
+#S
+inner.*
+
+#E
+iram.*
\ No newline at end of file
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
deleted file mode 100644
index 370d74c..0000000
--- a/openlane/user_proj_example/config.json
+++ /dev/null
@@ -1,45 +0,0 @@
-{
-    "DESIGN_NAME": "user_proj_example",
-    "DESIGN_IS_CORE": 0,
-    "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
-    "CLOCK_PERIOD": 10,
-    "CLOCK_PORT": "wb_clk_i",
-    "CLOCK_NET": "counter.clk",
-    "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 900 600",
-    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
-    "PL_BASIC_PLACEMENT": 0,
-    "PL_TARGET_DENSITY": 0.55,
-    "VDD_NETS": ["vccd1"],
-    "GND_NETS": ["vssd1"],
-    "DIODE_INSERTION_STRATEGY": 4,
-    "RUN_CVC": 1,
-    "pdk::sky130*": {
-        "FP_CORE_UTIL": 45,
-        "RT_MAX_LAYER": "met4",
-        "scl::sky130_fd_sc_hd": {
-            "CLOCK_PERIOD": 10
-        },
-        "scl::sky130_fd_sc_hdll": {
-            "CLOCK_PERIOD": 10
-        },
-        "scl::sky130_fd_sc_hs": {
-            "CLOCK_PERIOD": 8
-        },
-        "scl::sky130_fd_sc_ls": {
-            "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5
-        },
-        "scl::sky130_fd_sc_ms": {
-            "CLOCK_PERIOD": 10
-        }
-    },
-    "pdk::gf180mcuC": {
-        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
-        "CLOCK_PERIOD": 24.0,
-        "FP_CORE_UTIL": 40,
-        "RT_MAX_LAYER": "Metal4",
-        "SYNTH_MAX_FANOUT": 4,
-        "PL_TARGET_DENSITY": 0.45
-    }
-}
\ No newline at end of file
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
deleted file mode 100644
index 2fda806..0000000
--- a/openlane/user_proj_example/pin_order.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#BUS_SORT
-
-#S
-wb_.*
-wbs_.*
-la_.*
-irq.*
-
-#N
-io_.*
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..cdd8dfb 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -1,14 +1,54 @@
 {
     "DESIGN_NAME": "user_project_wrapper",
-    "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
-    "CLOCK_PERIOD": 10,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/user_project_wrapper.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/top.v"
+    ],
+    "CLOCK_PERIOD": 12,
     "CLOCK_PORT": "user_clock2",
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
     "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
-    "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
-    "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
-    "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
+    
+    "VERILOG_FILES_BLACKBOX": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/core/core.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/interconnect_inner.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/interconnect/interconnect_outer.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/dcache/dcache.v",
+        "dir::../../verilog/rtl/ppcpu/rtl/icache/icache.v",
+        "pdk_dir::libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+    ],
+    "EXTRA_LEFS": [
+        "dir::../../lef/core0.lef",
+        "dir::../../lef/core1.lef",
+        "dir::../../lef/dcache.lef",
+        "dir::../../lef/icache.lef",
+        "dir::../../lef/interconnect_inner.lef",
+        "dir::../../lef/interconnect_outer.lef",
+        "pdk_dir::libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
+    ], 
+    "EXTRA_S_FILES": [
+        "dir::../../gds/core0.gds",
+        "dir::../../gds/core1.gds",
+        "dir::../../gds/dcache.gds",
+        "dir::../../gds/icache.gds",
+        "dir::../../gds/interconnect_inner.gds",
+        "dir::../../gds/interconnect_outer.gds",
+        "pdk_dir::libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
+    ],
+    "EXTRA_LIBS": [
+        "dir::../../lib/core0.lib",
+        "dir::../../lib/core1.lib",
+        "dir::../../lib/dcache.lib",
+        "dir::../../lib/icache.lib",
+        "dir::../../lib/interconnect_inner.lib",
+        "dir::../../lib/interconnect_outer.lib",
+        "pdk_dir::libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8.lib"
+    ],
+    
     "FP_PDN_CHECK_NODES": 0,
     "SYNTH_ELABORATE_ONLY": 1,
     "PL_RANDOM_GLB_PLACEMENT": 1,
@@ -68,18 +108,6 @@
         "scl::sky130_fd_sc_ms": {
             "CLOCK_PERIOD": 10
         }
-     },
-    "pdk::gf180mcuC": {
-        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
-        "FP_PDN_CHECK_NODES": 0,
-        "FP_PDN_ENABLE_RAILS": 0,
-        "RT_MAX_LAYER": "Metal4",
-        "DIE_AREA": "0 0 3000 3000",
-        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
-        "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
-        "DIODE_INSERTION_STRATEGY": 0,
-        "FP_PDN_CHECK_NODES": 0,
-        "MAGIC_WRITE_FULL_LEF": 0,
-        "FP_PDN_ENABLE_RAILS": 0
-   }
+    },
+   "ROUTING_CORES": 6
 }
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..9a84a0e 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,8 @@
-mprj 1175 1690 N
+mprj/core0 150 400 N
+mprj/core1 150 1800 N
+mprj/dcache 1360 190 N
+mprj/icache_0 1270 1900 N
+mprj/icache_1 1270 2650 N
+mprj/interconnect_inner 770 1250 N
+mprj/interconnect_outer 770 2500 N
+mprj/int_ram 150 2800 N