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# Created by write_sdc
# Fri Dec 30 09:39:09 2022
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current_design interconnect_inner
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# Timing Constraints
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create_clock -name core_clock -period 10.0000 [get_ports {core_clock}]
set_clock_transition 0.1500 [get_clocks {core_clock}]
set_clock_uncertainty 0.2500 core_clock
set_propagated_clock [get_clocks {core_clock}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_pc[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_dbg_r0[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_c_data_page}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_c_instr_long}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_c_instr_page}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_icache_flush}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_instr_long_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_data[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_high_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_long_mode}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_req}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_sel[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_sel[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_mem_we}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_active}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_o_req_ppl_submit}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_data_o[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_sr_bus_we}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_pc[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_dbg_r0[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_c_data_page}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_c_instr_long}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_c_instr_page}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_icache_flush}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_instr_long_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_data[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_high_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_long_mode}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_req}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_sel[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_sel[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_mem_we}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_active}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_o_req_ppl_submit}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_data_o[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_sr_bus_we}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {core_reset}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_ack}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_exception}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_o_data[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_4_burst}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_adr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_cyc}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_o_dat[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_sel[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_sel[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_stb}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_we}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_ack}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_data[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_adr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_cyc}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_sel[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_sel[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_stb}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_we}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_ack}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_data[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_adr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_cyc}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_sel[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_sel[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_stb}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_we}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_disable}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_embed_mode}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_ext_irq}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_ack}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_err}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_i_dat[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_clk}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_disable}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_core_int_sreg[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_irq}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mc_core_int}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_ack}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_data[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_mem_exception}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[16]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[17]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[18]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[19]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[20]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[21]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[22]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[23]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[24]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[25]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[26]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[27]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[28]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[29]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[30]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[31]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_i_req_data_valid}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c0_rst}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_clk}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_disable}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_core_int_sreg[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_irq}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mc_core_int}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_ack}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_data[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_mem_exception}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[16]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[17]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[18]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[19]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[20]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[21]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[22]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[23]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[24]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[25]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[26]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[27]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[28]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[29]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[30]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[31]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_i_req_data_valid}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {c1_rst}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_clk}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[16]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[17]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[18]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[19]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[20]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[21]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[22]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[23]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_addr[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_cache_enable}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_i_data[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_req}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_sel[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_sel[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_mem_we}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_rst}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_ack}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_err}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dcache_wb_i_dat[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_clk}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_addr[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_cache_flush}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_ppl_submit}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_mem_req}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_rst}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_ack}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_err}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic0_wb_i_dat[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_clk}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_addr[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_cache_flush}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_ppl_submit}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_mem_req}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_rst}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_ack}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_err}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ic1_wb_i_dat[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_4_burst}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_8_burst}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[16]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[17]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[18]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[19]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[20]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[21]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[22]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[23]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_adr[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_cyc}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_o_dat[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_sel[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_sel[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_stb}]
set_output_delay 2.0000 -clock [get_clocks {core_clock}] -add_delay [get_ports {inner_wb_we}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {c0_clk}]
set_load -pin_load 0.0334 [get_ports {c0_disable}]
set_load -pin_load 0.0334 [get_ports {c0_i_irq}]
set_load -pin_load 0.0334 [get_ports {c0_i_mc_core_int}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_ack}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_exception}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data_valid}]
set_load -pin_load 0.0334 [get_ports {c0_rst}]
set_load -pin_load 0.0334 [get_ports {c1_clk}]
set_load -pin_load 0.0334 [get_ports {c1_disable}]
set_load -pin_load 0.0334 [get_ports {c1_i_irq}]
set_load -pin_load 0.0334 [get_ports {c1_i_mc_core_int}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_ack}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_exception}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data_valid}]
set_load -pin_load 0.0334 [get_ports {c1_rst}]
set_load -pin_load 0.0334 [get_ports {dcache_clk}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_cache_enable}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_req}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_we}]
set_load -pin_load 0.0334 [get_ports {dcache_rst}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_ack}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_err}]
set_load -pin_load 0.0334 [get_ports {ic0_clk}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_cache_flush}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_ppl_submit}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_req}]
set_load -pin_load 0.0334 [get_ports {ic0_rst}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_ack}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_err}]
set_load -pin_load 0.0334 [get_ports {ic1_clk}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_cache_flush}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_ppl_submit}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_req}]
set_load -pin_load 0.0334 [get_ports {ic1_rst}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_ack}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_err}]
set_load -pin_load 0.0334 [get_ports {inner_wb_4_burst}]
set_load -pin_load 0.0334 [get_ports {inner_wb_8_burst}]
set_load -pin_load 0.0334 [get_ports {inner_wb_cyc}]
set_load -pin_load 0.0334 [get_ports {inner_wb_stb}]
set_load -pin_load 0.0334 [get_ports {inner_wb_we}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[15]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[14]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[13]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[12]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[11]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[10]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[9]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[8]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[7]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[6]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[5]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[4]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[3]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[2]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[1]}]
set_load -pin_load 0.0334 [get_ports {c0_i_core_int_sreg[0]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[15]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[14]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[13]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[12]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[11]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[10]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[9]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[8]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[7]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[6]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[5]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[4]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[3]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[2]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[1]}]
set_load -pin_load 0.0334 [get_ports {c0_i_mem_data[0]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[31]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[30]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[29]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[28]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[27]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[26]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[25]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[24]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[23]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[22]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[21]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[20]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[19]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[18]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[17]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[16]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[15]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[14]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[13]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[12]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[11]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[10]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[9]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[8]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[7]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[6]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[5]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[4]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[3]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[2]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[1]}]
set_load -pin_load 0.0334 [get_ports {c0_i_req_data[0]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[15]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[14]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[13]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[12]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[11]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[10]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[9]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[8]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[7]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[6]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[5]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[4]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[3]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[2]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[1]}]
set_load -pin_load 0.0334 [get_ports {c1_i_core_int_sreg[0]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[15]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[14]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[13]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[12]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[11]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[10]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[9]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[8]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[7]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[6]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[5]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[4]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[3]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[2]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[1]}]
set_load -pin_load 0.0334 [get_ports {c1_i_mem_data[0]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[31]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[30]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[29]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[28]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[27]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[26]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[25]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[24]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[23]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[22]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[21]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[20]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[19]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[18]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[17]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[16]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[15]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[14]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[13]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[12]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[11]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[10]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[9]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[8]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[7]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[6]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[5]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[4]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[3]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[2]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[1]}]
set_load -pin_load 0.0334 [get_ports {c1_i_req_data[0]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[23]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[22]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[21]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[20]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[19]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[18]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[17]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[16]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[15]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[14]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[13]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[12]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[11]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[10]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[9]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[8]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[7]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[6]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[5]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[4]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[3]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[2]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[1]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_addr[0]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[15]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[14]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[13]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[12]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[11]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[10]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[9]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[8]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[7]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[6]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[5]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[4]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[3]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[2]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[1]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_i_data[0]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_sel[1]}]
set_load -pin_load 0.0334 [get_ports {dcache_mem_sel[0]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[15]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[14]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[13]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[12]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[11]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[10]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[9]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[8]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[7]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[6]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[5]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[4]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[3]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[2]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[1]}]
set_load -pin_load 0.0334 [get_ports {dcache_wb_i_dat[0]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[15]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[14]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[13]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[12]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[11]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[10]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[9]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[8]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[7]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[6]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[5]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[4]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[3]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[2]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[1]}]
set_load -pin_load 0.0334 [get_ports {ic0_mem_addr[0]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[15]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[14]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[13]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[12]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[11]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[10]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[9]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[8]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[7]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[6]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[5]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[4]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[3]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[2]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[1]}]
set_load -pin_load 0.0334 [get_ports {ic0_wb_i_dat[0]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[15]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[14]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[13]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[12]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[11]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[10]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[9]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[8]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[7]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[6]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[5]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[4]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[3]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[2]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[1]}]
set_load -pin_load 0.0334 [get_ports {ic1_mem_addr[0]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[15]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[14]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[13]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[12]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[11]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[10]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[9]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[8]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[7]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[6]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[5]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[4]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[3]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[2]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[1]}]
set_load -pin_load 0.0334 [get_ports {ic1_wb_i_dat[0]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[23]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[22]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[21]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[20]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[19]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[18]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[17]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[16]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[15]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[14]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[13]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[12]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[11]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[10]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[9]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[8]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[7]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[6]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[5]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[4]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[3]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[2]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[1]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_adr[0]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[15]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[14]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[13]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[12]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[11]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[10]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[9]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[8]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[7]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[6]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[5]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[4]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[3]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[2]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[1]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_o_dat[0]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_sel[1]}]
set_load -pin_load 0.0334 [get_ports {inner_wb_sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_c_data_page}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_c_instr_long}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_c_instr_page}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_icache_flush}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_long_mode}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_req}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_active}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_ppl_submit}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_c_data_page}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_c_instr_long}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_c_instr_page}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_icache_flush}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_long_mode}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_req}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_active}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_ppl_submit}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clock}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_reset}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_ack}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_exception}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_4_burst}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_cyc}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_stb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_ack}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_cyc}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_stb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_ack}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_cyc}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_stb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_disable}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_embed_mode}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_ext_irq}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_ack}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_err}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_pc[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_dbg_r0[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_instr_long_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_data[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_high_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_sel[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_mem_sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_o_req_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c0_sr_bus_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_pc[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_dbg_r0[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_instr_long_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_data[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_high_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_sel[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_mem_sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_o_req_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {c1_sr_bus_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_o_data[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_adr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_o_dat[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_sel[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_wb_sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_mem_data[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_adr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_sel[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic0_wb_sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_mem_data[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_adr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_sel[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ic1_wb_sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {inner_wb_i_dat[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 10.0000 [current_design]