[INFO]: Run Directory: /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[INFO]: Running Synthesis (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/synthesis/1-synthesis.log)...
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/synthesis/2-sta.log)...
[INFO]: Running Initial Floorplanning (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 488.52 and height 476.0.
[INFO]: Running IO Placement (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/floorplan/4-place_io.log)...
[INFO]: Running Tap/Decap Insertion (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {vccd1} and ground {vssd1}...
[INFO]: Generating PDN (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/floorplan/6-pdn.log)...
[INFO]: Running Global Placement (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/placement/7-global.log)...
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/placement/8-resizer.log)...
[INFO]: Running Detailed Placement (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/placement/9-detailed.log)...
[INFO]: Running Clock Tree Synthesis (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/cts/10-cts.log)...
[INFO]: Running Placement Resizer Timing Optimizations (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/cts/11-resizer.log)...
[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/12-resizer.log)...
[INFO]: Running Diode Insertion (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/13-diodes.log)...
[INFO]: Running Detailed Placement (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/14-diode_legalization.log)...
[INFO]: Running Fill Insertion (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/15-fill.log)...
[INFO]: Running Global Routing (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/16-global.log)...
[INFO]: Writing Verilog (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/16-global_write_netlist.log)...
[INFO]: Running Detailed Routing (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/18-detailed.log)...
[INFO]: No DRC violations after detailed routing.
[INFO]: Checking Wire Lengths (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/routing/19-wire_lengths.log)...
[INFO]: Running SPEF Extraction at the min process corner (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/20-parasitics_extraction.min.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/21-rcx_mcsta.min.log)...
[INFO]: Running SPEF Extraction at the max process corner (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/22-parasitics_extraction.max.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/23-rcx_mcsta.max.log)...
[INFO]: Running SPEF Extraction at the nom process corner (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/24-parasitics_extraction.nom.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/25-rcx_mcsta.nom.log)...
[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/26-rcx_sta.log)...
[INFO]: Creating IR Drop Report (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/27-irdrop.log)...
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDSII with Magic (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/28-gdsii.log)...
[INFO]: Generating MAGLEF views...
[INFO]: Streaming out GDSII with KLayout (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/29-gdsii-klayout.log)...
[INFO]: Running XOR on the layouts using KLayout (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/30-xor.log)...
[INFO]: Running Magic Spice Export from LEF (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/31-spice.log)...
[INFO]: Writing Powered Verilog (logs: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/32-write_powered_def.log, ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/32-write_powered_verilog.log)...
[INFO]: Writing Verilog (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/32-write_powered_verilog.log)...
[INFO]: Running LVS (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/34-lvs.lef.log)...
[INFO]: Running Magic DRC (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/35-drc.log)...
[INFO]: Converting Magic DRC database to various tool-readable formats...
[INFO]: No DRC violations after GDS streaming out.
[INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/36-antenna.log)...
[INFO]: Running Circuit Validity Checker ERC (log: ../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/logs/signoff/37-erc_screen.log)...
[INFO]: Saving current set of views in '../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/results/final'...
[INFO]: Saving current set of views in '../home/piotro/caravel_user_project'...
[INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/reports/metrics.csv'.
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/reports/signoff/26-rcx_sta.slew.rpt'.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
[INFO]: Note that the following warnings have been generated: