
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/core.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/core.v' to AST representation.
Generating RTLIL representation for module `\core'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v' to AST representation.
Generating RTLIL representation for module `\alu_mul_div'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v' to AST representation.
Generating RTLIL representation for module `\alu'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v' to AST representation.
Generating RTLIL representation for module `\decode'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v' to AST representation.
Generating RTLIL representation for module `\execute'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v' to AST representation.
Generating RTLIL representation for module `\fetch'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v' to AST representation.
Generating RTLIL representation for module `\memwb'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v' to AST representation.
Generating RTLIL representation for module `\pc'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v
Parsing SystemVerilog input from `/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v' to AST representation.
Generating RTLIL representation for module `\rf'.
Generating RTLIL representation for module `\register'.
Successfully finished Verilog frontend.

11. Generating Graphviz representation of design.
Writing dot description to `/home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/synthesis/hierarchy.dot'.
Dumping module core to page 1.
Warning: WIDTHLABEL \dbg_out [35] 1
Warning: WIDTHLABEL \dbg_in [3] 1
Warning: WIDTHLABEL \dbg_in [2:0] 3
Warning: WIDTHLABEL \dbg_out [32:0] 33
Warning: WIDTHLABEL \dbg_out [34] 1
Warning: WIDTHLABEL \fetch_decode_d_instr [31:16] 16
Warning: WIDTHLABEL \fetch_decode_d_instr [15:0] 16
Warning: WIDTHLABEL \dbg_out [33] 1

12. Executing HIERARCHY pass (managing design hierarchy).

12.1. Analyzing design hierarchy..
Top module:  \core
Used module:     \memwb
Used module:     \execute
Used module:         \register
Used module:         \pc
Used module:         \alu_mul_div
Used module:         \alu
Used module:         \rf
Used module:     \decode
Used module:     \fetch
Parameter \CORENO = 0
Parameter \INT_VEC = 1

12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\execute'.
Parameter \CORENO = 0
Parameter \INT_VEC = 1
Generating RTLIL representation for module `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute'.
Parameter \N = 8
Parameter \RESET_VAL = 8'10000000

12.3. Executing AST frontend in derive mode using pre-parsed AST for module `\register'.
Parameter \N = 8
Parameter \RESET_VAL = 8'10000000
Generating RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000'.
Parameter \N = 8
Parameter \RESET_VAL = 8'10000000
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000'.
Parameter \N = 5

12.4. Executing AST frontend in derive mode using pre-parsed AST for module `\register'.
Parameter \N = 5
Generating RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000101'.
Parameter \N = 3
Parameter \RESET_VAL = 3'001

12.5. Executing AST frontend in derive mode using pre-parsed AST for module `\register'.
Parameter \N = 3
Parameter \RESET_VAL = 3'001
Generating RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001'.
Parameter \N = 3
Parameter \RESET_VAL = 3'001
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001'.
Parameter \RESET_VAL = 16'0000000000000001

12.6. Executing AST frontend in derive mode using pre-parsed AST for module `\register'.
Parameter \RESET_VAL = 16'0000000000000001
Generating RTLIL representation for module `$paramod\register\RESET_VAL=16'0000000000000001'.
Parameter \N = 5
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000101'.
Parameter \INT_VEC = 1

12.7. Executing AST frontend in derive mode using pre-parsed AST for module `\pc'.
Parameter \INT_VEC = 1
Generating RTLIL representation for module `$paramod\pc\INT_VEC=s32'00000000000000000000000000000001'.
Reprocessing module rf because instantiated module register has become available.
Generating RTLIL representation for module `\rf'.

12.8. Analyzing design hierarchy..
Top module:  \core
Used module:     \memwb
Used module:     $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute
Used module:         \register
Used module:         \pc
Used module:         \alu_mul_div
Used module:         \alu
Used module:         \rf
Used module:     \decode
Used module:     \fetch
Parameter \N = 8
Parameter \RESET_VAL = 8'10000000
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000'.
Parameter \N = 8
Parameter \RESET_VAL = 8'10000000
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000'.
Parameter \N = 5
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000101'.
Parameter \N = 3
Parameter \RESET_VAL = 3'001
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001'.
Parameter \N = 3
Parameter \RESET_VAL = 3'001
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001'.
Parameter \RESET_VAL = 16'0000000000000001
Found cached RTLIL representation for module `$paramod\register\RESET_VAL=16'0000000000000001'.
Parameter \N = 5
Found cached RTLIL representation for module `$paramod\register\N=s32'00000000000000000000000000000101'.
Parameter \INT_VEC = 1
Found cached RTLIL representation for module `$paramod\pc\INT_VEC=s32'00000000000000000000000000000001'.

12.9. Analyzing design hierarchy..
Top module:  \core
Used module:     \memwb
Used module:     $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute
Used module:         $paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000
Used module:         $paramod\register\N=s32'00000000000000000000000000000101
Used module:         \register
Used module:         $paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001
Used module:         $paramod\register\RESET_VAL=16'0000000000000001
Used module:         $paramod\pc\INT_VEC=s32'00000000000000000000000000000001
Used module:         \alu_mul_div
Used module:         \alu
Used module:         \rf
Used module:     \decode
Used module:     \fetch

12.10. Analyzing design hierarchy..
Top module:  \core
Used module:     \memwb
Used module:     $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute
Used module:         $paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000
Used module:         $paramod\register\N=s32'00000000000000000000000000000101
Used module:         \register
Used module:         $paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001
Used module:         $paramod\register\RESET_VAL=16'0000000000000001
Used module:         $paramod\pc\INT_VEC=s32'00000000000000000000000000000001
Used module:         \alu_mul_div
Used module:         \alu
Used module:         \rf
Used module:     \decode
Used module:     \fetch
Removing unused module `\pc'.
Removing unused module `\execute'.
Removed 2 unused modules.

13. Executing TRIBUF pass.

14. Executing SYNTH pass.

14.1. Executing HIERARCHY pass (managing design hierarchy).

14.1.1. Analyzing design hierarchy..
Top module:  \core
Used module:     \memwb
Used module:     $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute
Used module:         $paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000
Used module:         $paramod\register\N=s32'00000000000000000000000000000101
Used module:         \register
Used module:         $paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001
Used module:         $paramod\register\RESET_VAL=16'0000000000000001
Used module:         $paramod\pc\INT_VEC=s32'00000000000000000000000000000001
Used module:         \alu_mul_div
Used module:         \alu
Used module:         \rf
Used module:     \decode
Used module:     \fetch

14.1.2. Analyzing design hierarchy..
Top module:  \core
Used module:     \memwb
Used module:     $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute
Used module:         $paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000
Used module:         $paramod\register\N=s32'00000000000000000000000000000101
Used module:         \register
Used module:         $paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001
Used module:         $paramod\register\RESET_VAL=16'0000000000000001
Used module:         $paramod\pc\INT_VEC=s32'00000000000000000000000000000001
Used module:         \alu_mul_div
Used module:         \alu
Used module:         \rf
Used module:     \decode
Used module:     \fetch
Removed 0 unused modules.

14.2. Executing PROC pass (convert processes to netlists).

14.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

14.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1085 in module $paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1084 in module $paramod\register\N=s32'00000000000000000000000000000101.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1083 in module $paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:470$1074 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:429$1053 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 3 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:286$1015 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:277$1013 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 2 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:266$1011 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 2 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:211$994 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:106$957 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 2 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:96$955 in module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$919 in module register.
Marked 3 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:21$1087 in module $paramod\pc\INT_VEC=s32'00000000000000000000000000000001.
Removed 1 dead cases from process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1133 in module rf.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1133 in module rf.
Removed 1 dead cases from process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1128 in module rf.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1128 in module rf.
Removed 1 dead cases from process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1125 in module rf.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1125 in module rf.
Removed 1 dead cases from process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1122 in module rf.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1122 in module rf.
Marked 2 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:58$884 in module memwb.
Marked 3 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:134$855 in module fetch.
Marked 5 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:104$844 in module fetch.
Marked 2 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:60$821 in module fetch.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:52$816 in module fetch.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:44$814 in module fetch.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:35$813 in module fetch.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1086 in module $paramod\register\RESET_VAL=16'0000000000000001.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623 in module decode.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170 in module decode.
Marked 1 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:21$57 in module alu.
Marked 3 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19 in module alu_mul_div.
Marked 2 switch rules as full_case in process $proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5 in module alu_mul_div.
Removed a total of 4 dead cases.

14.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 6 redundant assignments.
Promoted 147 assignments to connections.

14.2.4. Executing PROC_INIT pass (extract init attributes).

14.2.5. Executing PROC_ARST pass (detect async resets in processes).

14.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~75 debug messages>

14.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1085'.
     1/1: $0\o_d[2:0]
Creating decoders for process `$paramod\register\N=s32'00000000000000000000000000000101.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1084'.
     1/1: $0\o_d[4:0]
Creating decoders for process `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1083'.
     1/1: $0\o_d[7:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:470$1074'.
     1/1: $0\prev_pc_high[7:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:429$1053'.
     1/1: $0\o_c_data_page[0:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:423$1050'.
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
     1/11: $3\sreg_out[15:0]
     2/11: $2\sreg_out[15:0]
     3/11: $1\pc_sreg_ie[0:0]
     4/11: $1\sreg_out[15:0]
     5/11: $1\sreg_pc_high_buff_ie[0:0]
     6/11: $1\sreg_pc_high_ie[0:0]
     7/11: $1\sreg_scratch_ie[0:0]
     8/11: $1\sreg_jtr_ie[0:0]
     9/11: $1\alu_flags_sreg_ie[0:0]
    10/11: $1\sreg_irq_pc_ie[0:0]
    11/11: $1\sreg_priv_control_ie[0:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:286$1015'.
     1/1: $0\mem_stage_pc[15:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:277$1013'.
     1/1: $0\trap_exception[0:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:266$1011'.
     1/1: $0\prev_sys[0:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
     1/9: $0\o_submit[0:0]
     2/9: $0\o_mem_long_mode[0:0]
     3/9: $0\o_mem_width[0:0]
     4/9: $0\o_mem_access[0:0]
     5/9: $0\o_reg_ie[7:0]
     6/9: $0\o_addr[15:0]
     7/9: $0\o_data[15:0]
     8/9: $0\o_mem_addr_high[7:0]
     9/9: $0\o_mem_we[0:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:211$994'.
     1/1: $1\jump_dec_en[0:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:194$988'.
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:106$957'.
     1/1: $0\next_ready_delayed[0:0]
Creating decoders for process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:96$955'.
     1/1: $0\hold_valid[0:0]
Creating decoders for process `\register.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$919'.
     1/1: $0\o_d[15:0]
Creating decoders for process `$paramod\pc\INT_VEC=s32'00000000000000000000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:21$1087'.
     1/1: $0\o_pc[15:0]
Creating decoders for process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
Creating decoders for process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1133'.
     1/1: $1$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:34$1113_DATA[15:0]$1135
Creating decoders for process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1128'.
     1/1: $1$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:31$1112_DATA[15:0]$1130
Creating decoders for process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1125'.
     1/1: $1$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:30$1111_DATA[15:0]$1127
Creating decoders for process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1122'.
     1/1: $1$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:29$1110_DATA[15:0]$1124
Creating decoders for process `\memwb.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:58$884'.
     1/1: $0\o_mem_req[0:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:134$855'.
     1/3: $0\out_buffer_valid[0:0]
     2/3: $0\out_buffer_data_pred[0:0]
     3/3: $0\out_buffer_data_instr[31:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:104$844'.
     1/5: $5\branch_pred_res[0:0]
     2/5: $4\branch_pred_res[0:0]
     3/5: $3\branch_pred_res[0:0]
     4/5: $2\branch_pred_res[0:0]
     5/5: $1\branch_pred_res[0:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:89$832'.
     1/1: $0\prev_req_branch_pred[0:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:82$830'.
     1/1: $0\prev_request_pc[15:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:73$829'.
     1/2: $0\o_jmp_predict[0:0]
     2/2: $0\o_instr[31:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:60$821'.
     1/1: $0\instr_wait[0:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:52$816'.
     1/1: $0\flush_event_invalidate[0:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:44$814'.
     1/1: $0\pc_flush_override[0:0]
Creating decoders for process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:35$813'.
     1/1: $0\pc_reset_override[0:0]
Creating decoders for process `$paramod\register\RESET_VAL=16'0000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1086'.
     1/1: $0\o_d[15:0]
Creating decoders for process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
     1/24: $0\o_submit[0:0]
     2/24: $0\input_valid[0:0]
     3/24: $0\oc_mem_long[0:0]
     4/24: $0\oc_mem_width[0:0]
     5/24: $0\oc_sys[0:0]
     6/24: $0\oc_sreg_irt[0:0]
     7/24: $0\oc_sreg_jal_over[0:0]
     8/24: $0\oc_sreg_store[0:0]
     9/24: $0\oc_sreg_load[0:0]
    10/24: $0\oc_used_operands[1:0]
    11/24: $0\oc_mem_we[0:0]
    12/24: $0\oc_mem_access[0:0]
    13/24: $0\o_jmp_pred_pass[0:0]
    14/24: $0\oc_jump_cond_code[4:0]
    15/24: $0\oc_rf_ie[7:0]
    16/24: $0\oc_r_reg_sel[2:0]
    17/24: $0\oc_l_reg_sel[2:0]
    18/24: $0\oc_alu_carry_en[0:0]
    19/24: $0\oc_alu_flags_ie[0:0]
    20/24: $0\oc_alu_mode[3:0]
    21/24: $0\oc_r_bus_imm[0:0]
    22/24: $0\oc_pc_ie[0:0]
    23/24: $0\oc_pc_inc[0:0]
    24/24: $0\o_imm_pass[15:0]
Creating decoders for process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
     1/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:459$169[2:0]$350
     2/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:459$168[7:0]$349
     3/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:459$167[7:0]$348
     4/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:438$166[2:0]$347
     5/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:438$165[7:0]$346
     6/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:438$164[7:0]$345
     7/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:419$163[2:0]$344
     8/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:419$162[7:0]$343
     9/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:419$161[7:0]$342
    10/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:411$160[2:0]$341
    11/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:411$159[7:0]$340
    12/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:411$158[7:0]$339
    13/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:404$157[2:0]$338
    14/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:404$156[7:0]$337
    15/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:404$155[7:0]$336
    16/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:396$154[2:0]$335
    17/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:396$153[7:0]$334
    18/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:396$152[7:0]$333
    19/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:388$151[2:0]$332
    20/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:388$150[7:0]$331
    21/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:388$149[7:0]$330
    22/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:380$148[2:0]$329
    23/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:380$147[7:0]$328
    24/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:380$146[7:0]$327
    25/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:352$145[2:0]$326
    26/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:352$144[7:0]$325
    27/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:352$143[7:0]$324
    28/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:344$142[2:0]$323
    29/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:344$141[7:0]$322
    30/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:344$140[7:0]$321
    31/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:330$139[2:0]$320
    32/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:330$138[7:0]$319
    33/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:330$137[7:0]$318
    34/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:323$136[2:0]$317
    35/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:323$135[7:0]$316
    36/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:323$134[7:0]$315
    37/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:308$133[2:0]$314
    38/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:308$132[7:0]$313
    39/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:308$131[7:0]$312
    40/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:300$130[2:0]$311
    41/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:300$129[7:0]$310
    42/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:300$128[7:0]$309
    43/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:292$127[2:0]$308
    44/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:292$126[7:0]$307
    45/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:292$125[7:0]$306
    46/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:284$124[2:0]$305
    47/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:284$123[7:0]$304
    48/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:284$122[7:0]$303
    49/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:276$121[2:0]$302
    50/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:276$120[7:0]$301
    51/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:276$119[7:0]$300
    52/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:268$118[2:0]$299
    53/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:268$117[7:0]$298
    54/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:268$116[7:0]$297
    55/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:260$115[2:0]$296
    56/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:260$114[7:0]$295
    57/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:260$113[7:0]$294
    58/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:252$112[2:0]$293
    59/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:252$111[7:0]$292
    60/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:252$110[7:0]$291
    61/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:241$109[2:0]$290
    62/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:241$108[7:0]$289
    63/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:241$107[7:0]$288
    64/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:235$106[2:0]$287
    65/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:235$105[7:0]$286
    66/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:235$104[7:0]$285
    67/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:192$103[2:0]$284
    68/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:192$102[7:0]$283
    69/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:192$101[7:0]$282
    70/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:184$100[2:0]$281
    71/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:184$99[7:0]$280
    72/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:184$98[7:0]$279
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    81/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:144$89[7:0]$270
    82/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:137$88[2:0]$269
    83/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:137$87[7:0]$268
    84/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:137$86[7:0]$267
    85/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:130$85[2:0]$266
    86/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:130$84[7:0]$265
    87/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:130$83[7:0]$264
    88/110: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:124$82[2:0]$263
    89/110: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:124$81[7:0]$262
    90/110: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:124$80[7:0]$261
    91/110: $1\c_mem_long[0:0]
    92/110: $1\c_mem_width[0:0]
    93/110: $1\c_sys[0:0]
    94/110: $1\c_sreg_irt[0:0]
    95/110: $1\c_sreg_jal_over[0:0]
    96/110: $1\c_sreg_store[0:0]
    97/110: $1\c_sreg_load[0:0]
    98/110: $1\c_used_operands[1:0]
    99/110: $1\c_mem_we[0:0]
   100/110: $1\c_mem_access[0:0]
   101/110: $1\c_jump_cond_code[4:0]
   102/110: $1\c_rf_ie[7:0]
   103/110: $1\c_r_reg_sel[2:0]
   104/110: $1\c_l_reg_sel[2:0]
   105/110: $1\c_alu_carry_en[0:0]
   106/110: $1\c_alu_flags_ie[0:0]
   107/110: $1\c_alu_mode[3:0]
   108/110: $1\c_r_bus_imm[0:0]
   109/110: $1\c_pc_ie[0:0]
   110/110: $1\c_pc_inc[0:0]
Creating decoders for process `\alu.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:21$57'.
     1/1: $1\outc[16:0]
Creating decoders for process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
     1/9: $2$lookahead\div_res$18[15:0]$34
     2/9: $2$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$3[15:0]$32
     3/9: $2$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$2[15:0]$31
     4/9: $2$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$4[31:0]$33
     5/9: $1$lookahead\div_res$18[15:0]$29
     6/9: $1$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$4[31:0]$28
     7/9: $1$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$3[15:0]$27
     8/9: $1$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$2[15:0]$26
     9/9: $1\div_cur[15:0]
Creating decoders for process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:49$11'.
     1/1: $1\mul_res[15:0]
Creating decoders for process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
     1/5: $0\div_cur[15:0]
     2/5: $0\div_res[15:0]
     3/5: $0\mul_res[15:0]
     4/5: $0\comp[0:0]
     5/5: $0\cbit[3:0]

14.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\sreg_out' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\pc_sreg_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\sreg_priv_control_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\sreg_irq_pc_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\alu_flags_sreg_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\sreg_jtr_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\sreg_scratch_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\sreg_pc_high_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\sreg_pc_high_buff_ie' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
No latch inferred for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\jump_dec_en' from process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:211$994'.
No latch inferred for signal `\rf.\reg_outputs[0]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.\reg_outputs[1]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.\reg_outputs[2]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.\reg_outputs[3]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.\reg_outputs[4]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.\reg_outputs[5]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.\reg_outputs[6]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.\reg_outputs[7]' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
No latch inferred for signal `\rf.$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:34$1113_DATA' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1133'.
No latch inferred for signal `\rf.$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:31$1112_DATA' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1128'.
No latch inferred for signal `\rf.$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:30$1111_DATA' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1125'.
No latch inferred for signal `\rf.$mem2reg_rd$\reg_outputs$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:29$1110_DATA' from process `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1122'.
No latch inferred for signal `\fetch.\branch_pred_res' from process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:104$844'.
No latch inferred for signal `\decode.\c_pc_inc' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_pc_ie' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_r_bus_imm' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_alu_mode' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_alu_flags_ie' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_alu_carry_en' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_l_reg_sel' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_r_reg_sel' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_rf_ie' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_jump_cond_code' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_mem_access' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_mem_we' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_used_operands' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_sreg_load' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_sreg_store' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_sreg_jal_over' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_sreg_irt' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_sys' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_mem_width' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.\c_mem_long' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:124$80' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:124$81' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:124$82' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:130$83' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:130$84' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:130$85' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:137$86' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:137$87' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:137$88' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:144$89' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:144$90' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:144$91' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:167$92' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:167$93' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:167$94' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:175$95' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:175$96' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:175$97' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:184$98' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:184$99' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:184$100' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:192$101' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:192$102' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:192$103' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:235$104' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:235$105' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:235$106' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:241$107' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:241$108' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:241$109' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:252$110' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:252$111' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:252$112' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:260$113' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:260$114' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:260$115' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:268$116' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:268$117' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:268$118' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:276$119' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:276$120' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:276$121' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:284$122' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:284$123' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:284$124' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:292$125' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:292$126' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:292$127' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:300$128' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:300$129' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:300$130' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:308$131' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:308$132' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:308$133' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:323$134' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:323$135' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:323$136' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:330$137' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:330$138' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:330$139' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:344$140' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:344$141' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:344$142' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:352$143' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:352$144' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:352$145' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:380$146' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:380$147' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:380$148' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:388$149' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:388$150' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:388$151' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:396$152' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:396$153' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:396$154' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:404$155' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:404$156' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:404$157' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:411$158' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:411$159' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:411$160' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:419$161' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:419$162' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:419$163' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:438$164' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:438$165' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:438$166' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:459$167' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:459$168' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\decode.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:459$169' from process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
No latch inferred for signal `\alu.\o_flags' from process `\alu.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:21$57'.
No latch inferred for signal `\alu.\outc' from process `\alu.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:21$57'.

14.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.\o_d' using process `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1085'.
  created $dff cell `$procdff$4467' with positive edge clock.
Creating register for signal `$paramod\register\N=s32'00000000000000000000000000000101.\o_d' using process `$paramod\register\N=s32'00000000000000000000000000000101.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1084'.
  created $dff cell `$procdff$4468' with positive edge clock.
Creating register for signal `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.\o_d' using process `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1083'.
  created $dff cell `$procdff$4469' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\prev_pc_high' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:470$1074'.
  created $dff cell `$procdff$4470' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_c_data_page' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:429$1053'.
  created $dff cell `$procdff$4471' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_icache_flush' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:423$1050'.
  created $dff cell `$procdff$4472' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\mem_stage_pc' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:286$1015'.
  created $dff cell `$procdff$4473' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\trap_exception' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:277$1013'.
  created $dff cell `$procdff$4474' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\prev_sys' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:266$1011'.
  created $dff cell `$procdff$4475' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_mem_we' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4476' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_mem_addr_high' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4477' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_submit' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4478' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_data' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4479' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_addr' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4480' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_reg_ie' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4481' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_mem_access' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4482' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_mem_width' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4483' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_mem_long_mode' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
  created $dff cell `$procdff$4484' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\o_flush' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:194$988'.
  created $dff cell `$procdff$4485' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\next_ready_delayed' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:106$957'.
  created $dff cell `$procdff$4486' with positive edge clock.
Creating register for signal `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.\hold_valid' using process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:96$955'.
  created $dff cell `$procdff$4487' with positive edge clock.
Creating register for signal `\register.\o_d' using process `\register.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$919'.
  created $dff cell `$procdff$4488' with positive edge clock.
Creating register for signal `$paramod\pc\INT_VEC=s32'00000000000000000000000000000001.\o_pc' using process `$paramod\pc\INT_VEC=s32'00000000000000000000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:21$1087'.
  created $dff cell `$procdff$4489' with positive edge clock.
Creating register for signal `\memwb.\o_mem_req' using process `\memwb.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:58$884'.
  created $dff cell `$procdff$4490' with positive edge clock.
Creating register for signal `\fetch.\out_buffer_data_instr' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:134$855'.
  created $dff cell `$procdff$4491' with positive edge clock.
Creating register for signal `\fetch.\out_buffer_data_pred' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:134$855'.
  created $dff cell `$procdff$4492' with positive edge clock.
Creating register for signal `\fetch.\out_buffer_valid' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:134$855'.
  created $dff cell `$procdff$4493' with positive edge clock.
Creating register for signal `\fetch.\prev_req_branch_pred' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:89$832'.
  created $dff cell `$procdff$4494' with positive edge clock.
Creating register for signal `\fetch.\prev_request_pc' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:82$830'.
  created $dff cell `$procdff$4495' with positive edge clock.
Creating register for signal `\fetch.\o_submit' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:73$829'.
  created $dff cell `$procdff$4496' with positive edge clock.
Creating register for signal `\fetch.\o_instr' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:73$829'.
  created $dff cell `$procdff$4497' with positive edge clock.
Creating register for signal `\fetch.\o_jmp_predict' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:73$829'.
  created $dff cell `$procdff$4498' with positive edge clock.
Creating register for signal `\fetch.\instr_wait' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:60$821'.
  created $dff cell `$procdff$4499' with positive edge clock.
Creating register for signal `\fetch.\flush_event_invalidate' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:52$816'.
  created $dff cell `$procdff$4500' with positive edge clock.
Creating register for signal `\fetch.\pc_flush_override' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:44$814'.
  created $dff cell `$procdff$4501' with positive edge clock.
Creating register for signal `\fetch.\pc_reset_override' using process `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:35$813'.
  created $dff cell `$procdff$4502' with positive edge clock.
Creating register for signal `$paramod\register\RESET_VAL=16'0000000000000001.\o_d' using process `$paramod\register\RESET_VAL=16'0000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1086'.
  created $dff cell `$procdff$4503' with positive edge clock.
Creating register for signal `\decode.\o_submit' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4504' with positive edge clock.
Creating register for signal `\decode.\o_imm_pass' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4505' with positive edge clock.
Creating register for signal `\decode.\oc_pc_inc' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4506' with positive edge clock.
Creating register for signal `\decode.\oc_pc_ie' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4507' with positive edge clock.
Creating register for signal `\decode.\oc_r_bus_imm' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4508' with positive edge clock.
Creating register for signal `\decode.\oc_alu_mode' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4509' with positive edge clock.
Creating register for signal `\decode.\oc_alu_flags_ie' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4510' with positive edge clock.
Creating register for signal `\decode.\oc_alu_carry_en' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4511' with positive edge clock.
Creating register for signal `\decode.\oc_l_reg_sel' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4512' with positive edge clock.
Creating register for signal `\decode.\oc_r_reg_sel' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4513' with positive edge clock.
Creating register for signal `\decode.\oc_rf_ie' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4514' with positive edge clock.
Creating register for signal `\decode.\oc_jump_cond_code' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4515' with positive edge clock.
Creating register for signal `\decode.\o_jmp_pred_pass' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4516' with positive edge clock.
Creating register for signal `\decode.\oc_mem_access' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4517' with positive edge clock.
Creating register for signal `\decode.\oc_mem_we' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4518' with positive edge clock.
Creating register for signal `\decode.\oc_used_operands' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4519' with positive edge clock.
Creating register for signal `\decode.\oc_sreg_load' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4520' with positive edge clock.
Creating register for signal `\decode.\oc_sreg_store' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4521' with positive edge clock.
Creating register for signal `\decode.\oc_sreg_jal_over' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4522' with positive edge clock.
Creating register for signal `\decode.\oc_sreg_irt' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4523' with positive edge clock.
Creating register for signal `\decode.\oc_sys' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4524' with positive edge clock.
Creating register for signal `\decode.\oc_mem_width' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4525' with positive edge clock.
Creating register for signal `\decode.\oc_mem_long' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4526' with positive edge clock.
Creating register for signal `\decode.\input_valid' using process `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
  created $dff cell `$procdff$4527' with positive edge clock.
Creating register for signal `\alu_mul_div.\div_res' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
  created $dff cell `$procdff$4528' with positive edge clock.
Creating register for signal `\alu_mul_div.\div_cur' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
  created $dff cell `$procdff$4529' with positive edge clock.
Creating register for signal `\alu_mul_div.$bitselwrite$mask$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$2' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
  created $dff cell `$procdff$4530' with positive edge clock.
Creating register for signal `\alu_mul_div.$bitselwrite$data$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$3' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
  created $dff cell `$procdff$4531' with positive edge clock.
Creating register for signal `\alu_mul_div.$bitselwrite$sel$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$4' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
  created $dff cell `$procdff$4532' with positive edge clock.
Creating register for signal `\alu_mul_div.$lookahead\div_res$18' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
  created $dff cell `$procdff$4533' with positive edge clock.
Creating register for signal `\alu_mul_div.\mul_res' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:49$11'.
  created $dff cell `$procdff$4534' with positive edge clock.
Creating register for signal `\alu_mul_div.\cbit' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
  created $dff cell `$procdff$4535' with positive edge clock.
Creating register for signal `\alu_mul_div.\comp' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
  created $dff cell `$procdff$4536' with positive edge clock.
Creating register for signal `\alu_mul_div.\mul_res' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
  created $dff cell `$procdff$4537' with positive edge clock.
Creating register for signal `\alu_mul_div.\div_res' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
  created $dff cell `$procdff$4538' with positive edge clock.
Creating register for signal `\alu_mul_div.\div_cur' using process `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
  created $dff cell `$procdff$4539' with positive edge clock.

14.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

14.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 2 empty switches in `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1085'.
Removing empty process `$paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1085'.
Found and cleaned up 2 empty switches in `$paramod\register\N=s32'00000000000000000000000000000101.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1084'.
Removing empty process `$paramod\register\N=s32'00000000000000000000000000000101.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1084'.
Found and cleaned up 2 empty switches in `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1083'.
Removing empty process `$paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1083'.
Found and cleaned up 1 empty switch in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:470$1074'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:470$1074'.
Found and cleaned up 2 empty switches in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:429$1053'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:429$1053'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:423$1050'.
Found and cleaned up 3 empty switches in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:309$1016'.
Found and cleaned up 2 empty switches in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:286$1015'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:286$1015'.
Found and cleaned up 1 empty switch in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:277$1013'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:277$1013'.
Found and cleaned up 2 empty switches in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:266$1011'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:266$1011'.
Found and cleaned up 2 empty switches in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:245$1004'.
Found and cleaned up 1 empty switch in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:211$994'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:211$994'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:194$988'.
Found and cleaned up 1 empty switch in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:106$957'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:106$957'.
Found and cleaned up 3 empty switches in `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:96$955'.
Removing empty process `$paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:96$955'.
Found and cleaned up 2 empty switches in `\register.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$919'.
Removing empty process `register.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$919'.
Found and cleaned up 4 empty switches in `$paramod\pc\INT_VEC=s32'00000000000000000000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:21$1087'.
Removing empty process `$paramod\pc\INT_VEC=s32'00000000000000000000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:21$1087'.
Removing empty process `rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1136'.
Found and cleaned up 1 empty switch in `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1133'.
Removing empty process `rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1133'.
Found and cleaned up 1 empty switch in `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1128'.
Removing empty process `rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1128'.
Found and cleaned up 1 empty switch in `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1125'.
Removing empty process `rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1125'.
Found and cleaned up 1 empty switch in `\rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1122'.
Removing empty process `rf.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:0$1122'.
Found and cleaned up 3 empty switches in `\memwb.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:58$884'.
Removing empty process `memwb.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:58$884'.
Found and cleaned up 4 empty switches in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:134$855'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:134$855'.
Found and cleaned up 5 empty switches in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:104$844'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:104$844'.
Found and cleaned up 1 empty switch in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:89$832'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:89$832'.
Found and cleaned up 1 empty switch in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:82$830'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:82$830'.
Found and cleaned up 1 empty switch in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:73$829'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:73$829'.
Found and cleaned up 3 empty switches in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:60$821'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:60$821'.
Found and cleaned up 2 empty switches in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:52$816'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:52$816'.
Found and cleaned up 2 empty switches in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:44$814'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:44$814'.
Found and cleaned up 2 empty switches in `\fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:35$813'.
Removing empty process `fetch.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:35$813'.
Found and cleaned up 2 empty switches in `$paramod\register\RESET_VAL=16'0000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1086'.
Removing empty process `$paramod\register\RESET_VAL=16'0000000000000001.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:67$1086'.
Found and cleaned up 4 empty switches in `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
Removing empty process `decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:474$623'.
Found and cleaned up 1 empty switch in `\decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
Removing empty process `decode.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:106$170'.
Found and cleaned up 1 empty switch in `\alu.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:21$57'.
Removing empty process `alu.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:21$57'.
Found and cleaned up 4 empty switches in `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
Removing empty process `alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:58$19'.
Found and cleaned up 1 empty switch in `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:49$11'.
Removing empty process `alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:49$11'.
Found and cleaned up 4 empty switches in `\alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
Removing empty process `alu_mul_div.$proc$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:29$5'.
Cleaned up 75 empty switches.

14.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.
Optimizing module $paramod\register\N=s32'00000000000000000000000000000101.
Optimizing module $paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.
Optimizing module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
<suppressed ~2 debug messages>
Optimizing module register.
Optimizing module $paramod\pc\INT_VEC=s32'00000000000000000000000000000001.
Optimizing module rf.
<suppressed ~4 debug messages>
Optimizing module memwb.
<suppressed ~4 debug messages>
Optimizing module fetch.
<suppressed ~1 debug messages>
Optimizing module $paramod\register\RESET_VAL=16'0000000000000001.
Optimizing module decode.
Optimizing module alu.
Optimizing module alu_mul_div.
Optimizing module core.

14.3. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod\register\N=s32'00000000000000000000000000000011\RESET_VAL=3'001.
Deleting now unused module $paramod\register\N=s32'00000000000000000000000000000101.
Deleting now unused module $paramod\register\N=s32'00000000000000000000000000001000\RESET_VAL=8'10000000.
Deleting now unused module $paramod$b03ac35607b1812cc385f575a3516157e56f8b65\execute.
Deleting now unused module register.
Deleting now unused module $paramod\pc\INT_VEC=s32'00000000000000000000000000000001.
Deleting now unused module rf.
Deleting now unused module memwb.
Deleting now unused module fetch.
Deleting now unused module $paramod\register\RESET_VAL=16'0000000000000001.
Deleting now unused module decode.
Deleting now unused module alu.
Deleting now unused module alu_mul_div.
<suppressed ~25 debug messages>

14.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~70 debug messages>

14.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 193 unused cells and 1042 unused wires.
<suppressed ~257 debug messages>

14.6. Executing CHECK pass (checking for obvious problems).
Checking module core...
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [15]:
    port Q[15] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[15] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [14]:
    port Q[14] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[14] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [13]:
    port Q[13] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[13] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [12]:
    port Q[12] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[12] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [11]:
    port Q[11] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[11] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [10]:
    port Q[10] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[10] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [9]:
    port Q[9] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[9] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [8]:
    port Q[8] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[8] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [7]:
    port Q[7] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[7] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [6]:
    port Q[6] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[6] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [5]:
    port Q[5] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[5] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [4]:
    port Q[4] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[4] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [3]:
    port Q[3] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[3] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [2]:
    port Q[2] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[2] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [1]:
    port Q[1] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[1] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [0]:
    port Q[0] of cell $flatten\execute.\alu_mul_div.$procdff$4534 ($dff)
    port Q[0] of cell $flatten\execute.\alu_mul_div.$procdff$4537 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [15]:
    port Q[15] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[15] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [14]:
    port Q[14] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[14] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [13]:
    port Q[13] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[13] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [12]:
    port Q[12] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[12] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [11]:
    port Q[11] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[11] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [10]:
    port Q[10] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[10] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [9]:
    port Q[9] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[9] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [8]:
    port Q[8] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[8] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [7]:
    port Q[7] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[7] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [6]:
    port Q[6] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[6] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [5]:
    port Q[5] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[5] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [4]:
    port Q[4] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[4] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [3]:
    port Q[3] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[3] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [2]:
    port Q[2] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[2] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [1]:
    port Q[1] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[1] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [0]:
    port Q[0] of cell $flatten\execute.\alu_mul_div.$procdff$4529 ($dff)
    port Q[0] of cell $flatten\execute.\alu_mul_div.$procdff$4539 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [15]:
    port Q[15] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[15] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [14]:
    port Q[14] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[14] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [13]:
    port Q[13] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[13] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [12]:
    port Q[12] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[12] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [11]:
    port Q[11] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[11] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [10]:
    port Q[10] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[10] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [9]:
    port Q[9] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[9] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [8]:
    port Q[8] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[8] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [7]:
    port Q[7] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[7] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [6]:
    port Q[6] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[6] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [5]:
    port Q[5] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[5] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [4]:
    port Q[4] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[4] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [3]:
    port Q[3] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[3] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [2]:
    port Q[2] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[2] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [1]:
    port Q[1] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[1] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_res [0]:
    port Q[0] of cell $flatten\execute.\alu_mul_div.$procdff$4528 ($dff)
    port Q[0] of cell $flatten\execute.\alu_mul_div.$procdff$4538 ($dff)
Found and reported 48 problems.

14.7. Executing OPT pass (performing simple optimizations).

14.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
<suppressed ~1326 debug messages>
Removed a total of 442 cells.

14.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $flatten\execute.\alu_mul_div.$procmux$4451: \execute.alu_mul_div.comp -> 1'0
      Replacing known input bits on port A of cell $flatten\execute.\alu_mul_div.$procmux$4449: \execute.alu_mul_div.comp -> 1'1
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\execute.\alu_mul_div.$procmux$4386.
    dead port 1/2 on $mux $flatten\fetch.$procmux$1441.
    dead port 1/2 on $mux $flatten\fetch.$procmux$1444.
    dead port 1/2 on $mux $flatten\fetch.$procmux$1451.
    dead port 2/2 on $mux $flatten\fetch.$procmux$1453.
    dead port 1/2 on $mux $flatten\fetch.$procmux$1456.
    dead port 2/2 on $mux $flatten\fetch.$procmux$1462.
    dead port 1/2 on $mux $flatten\fetch.$procmux$1465.
    dead port 1/2 on $mux $flatten\fetch.$procmux$1471.
Removed 9 multiplexer ports.
<suppressed ~106 debug messages>

14.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4277: $auto$opt_reduce.cc:134:opt_pmux$4541
    New ctrl vector for $pmux cell $flatten\decode.$procmux$3842: $auto$opt_reduce.cc:134:opt_pmux$4543
    New ctrl vector for $pmux cell $flatten\decode.$procmux$3849: $auto$opt_reduce.cc:134:opt_pmux$4545
    New ctrl vector for $pmux cell $flatten\decode.$procmux$3985: { $auto$opt_reduce.cc:134:opt_pmux$4551 $auto$opt_reduce.cc:134:opt_pmux$4549 $auto$opt_reduce.cc:134:opt_pmux$4547 }
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4364: $auto$opt_reduce.cc:134:opt_pmux$4553
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4024: $auto$opt_reduce.cc:134:opt_pmux$4555
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4033: $auto$opt_reduce.cc:134:opt_pmux$4557
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4203: $auto$opt_reduce.cc:134:opt_pmux$4559
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4212: $auto$opt_reduce.cc:134:opt_pmux$4561
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4080: $auto$opt_reduce.cc:134:opt_pmux$4563
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4135: { $auto$opt_reduce.cc:134:opt_pmux$4567 $auto$opt_reduce.cc:134:opt_pmux$4565 }
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4235: { $auto$opt_reduce.cc:134:opt_pmux$4585 $auto$opt_reduce.cc:134:opt_pmux$4583 $auto$opt_reduce.cc:134:opt_pmux$4581 $auto$opt_reduce.cc:134:opt_pmux$4579 $flatten\decode.$procmux$4000_CMP $flatten\decode.$procmux$3999_CMP $auto$opt_reduce.cc:134:opt_pmux$4577 $auto$opt_reduce.cc:134:opt_pmux$4575 $auto$opt_reduce.cc:134:opt_pmux$4573 $auto$opt_reduce.cc:134:opt_pmux$4571 $flatten\decode.$procmux$3991_CMP $auto$opt_reduce.cc:134:opt_pmux$4569 $flatten\decode.$procmux$3986_CMP }
    New ctrl vector for $pmux cell $flatten\decode.$procmux$4112: { $auto$opt_reduce.cc:134:opt_pmux$4589 $auto$opt_reduce.cc:134:opt_pmux$4587 }
  Optimizing cells in module \core.
Performed a total of 13 changes.

14.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

14.7.6. Executing OPT_DFF pass (perform DFF optimizations).

14.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 0 unused cells and 452 unused wires.
<suppressed ~1 debug messages>

14.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.7.9. Rerunning OPT passes. (Maybe there is more to do..)

14.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~105 debug messages>

14.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

14.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.7.13. Executing OPT_DFF pass (perform DFF optimizations).

14.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.7.16. Finished OPT passes. (There is nothing left to do.)

14.8. Executing FSM pass (extract and optimize FSM).

14.8.1. Executing FSM_DETECT pass (finding FSMs in design).
Found FSM state register core.decode.oc_alu_mode.
Not marking core.decode.oc_used_operands as FSM state register:
    Users of register don't seem to benefit from recoding.

14.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\decode.oc_alu_mode' from module `\core'.
  found $dff cell for state register: $flatten\decode.$procdff$4509
  root of input selection tree: $flatten\decode.$0\oc_alu_mode[3:0]
  found ctrl input: \i_rst
  found ctrl input: $flatten\decode.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:482$627_Y
  found ctrl input: $flatten\decode.$procmux$3986_CMP
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4569
  found ctrl input: $flatten\decode.$procmux$3991_CMP
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4571
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4573
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4575
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4577
  found ctrl input: $flatten\decode.$procmux$3999_CMP
  found ctrl input: $flatten\decode.$procmux$4000_CMP
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4579
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4581
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4583
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$4585
  found state code: 4'0000
  found state code: 4'1101
  found state code: 4'0010
  found state code: 4'1100
  found state code: 4'1011
  found state code: 4'1000
  found state code: 4'0111
  found state code: 4'0001
  found state code: 4'1010
  found state code: 4'1001
  found state code: 4'0100
  found state code: 4'0110
  found state code: 4'0101
  found state code: 4'0011
  found ctrl output: $flatten\execute.\alu.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:54$74_Y
  found ctrl output: $flatten\execute.\alu.$procmux$4370_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4371_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4374_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4375_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4376_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4377_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4378_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4380_CMP
  found ctrl output: $flatten\execute.\alu.$procmux$4381_CMP
  found ctrl output: \execute.alu_mul_div.i_mod
  found ctrl output: \execute.alu_mul_div.i_div
  found ctrl output: \execute.alu_mul_div.i_mul
  ctrl inputs: { $auto$opt_reduce.cc:134:opt_pmux$4573 $auto$opt_reduce.cc:134:opt_pmux$4571 $auto$opt_reduce.cc:134:opt_pmux$4569 $auto$opt_reduce.cc:134:opt_pmux$4585 $auto$opt_reduce.cc:134:opt_pmux$4583 $auto$opt_reduce.cc:134:opt_pmux$4581 $auto$opt_reduce.cc:134:opt_pmux$4579 $auto$opt_reduce.cc:134:opt_pmux$4577 $auto$opt_reduce.cc:134:opt_pmux$4575 $flatten\decode.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:482$627_Y $flatten\decode.$procmux$3986_CMP $flatten\decode.$procmux$3991_CMP $flatten\decode.$procmux$3999_CMP $flatten\decode.$procmux$4000_CMP \i_rst }
  ctrl outputs: { $flatten\execute.\alu.$procmux$4381_CMP $flatten\execute.\alu.$procmux$4380_CMP $flatten\execute.\alu.$procmux$4378_CMP $flatten\execute.\alu.$procmux$4377_CMP $flatten\execute.\alu.$procmux$4376_CMP $flatten\execute.\alu.$procmux$4375_CMP $flatten\execute.\alu.$procmux$4374_CMP $flatten\execute.\alu.$procmux$4371_CMP $flatten\execute.\alu.$procmux$4370_CMP $flatten\execute.\alu.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:54$74_Y \execute.alu_mul_div.i_mod \execute.alu_mul_div.i_div \execute.alu_mul_div.i_mul $flatten\decode.$0\oc_alu_mode[3:0] }
  transition:     4'0000 15'---------0----0 ->     4'0000 17'00000000000000000
  transition:     4'0000 15'000000000100000 ->     4'0000 17'00000000000000000
  transition:     4'0000 15'---1-----1----0 ->     4'0011 17'00000000000000011
  transition:     4'0000 15'----1----1----0 ->     4'0101 17'00000000000000101
  transition:     4'0000 15'-----1---1----0 ->     4'0110 17'00000000000000110
  transition:     4'0000 15'------1--1----0 ->     4'0100 17'00000000000000100
  transition:     4'0000 15'---------1---10 ->     4'1001 17'00000000000001001
  transition:     4'0000 15'---------1--1-0 ->     4'1010 17'00000000000001010
  transition:     4'0000 15'-------1-1----0 ->     4'0001 17'00000000000000001
  transition:     4'0000 15'--------11----0 ->     4'0111 17'00000000000000111
  transition:     4'0000 15'1--------1----0 ->     4'1000 17'00000000000001000
  transition:     4'0000 15'-1-------1----0 ->     4'1011 17'00000000000001011
  transition:     4'0000 15'---------1-1--0 ->     4'1100 17'00000000000001100
  transition:     4'0000 15'--1------1----0 ->     4'0010 17'00000000000000010
  transition:     4'0000 15'---------11---0 ->     4'1101 17'00000000000001101
  transition:     4'0000 15'--------------1 ->     4'0000 17'00000000000000000
  transition:     4'1000 15'---------0----0 ->     4'1000 17'00000010000001000
  transition:     4'1000 15'000000000100000 ->     4'0000 17'00000010000000000
  transition:     4'1000 15'---1-----1----0 ->     4'0011 17'00000010000000011
  transition:     4'1000 15'----1----1----0 ->     4'0101 17'00000010000000101
  transition:     4'1000 15'-----1---1----0 ->     4'0110 17'00000010000000110
  transition:     4'1000 15'------1--1----0 ->     4'0100 17'00000010000000100
  transition:     4'1000 15'---------1---10 ->     4'1001 17'00000010000001001
  transition:     4'1000 15'---------1--1-0 ->     4'1010 17'00000010000001010
  transition:     4'1000 15'-------1-1----0 ->     4'0001 17'00000010000000001
  transition:     4'1000 15'--------11----0 ->     4'0111 17'00000010000000111
  transition:     4'1000 15'1--------1----0 ->     4'1000 17'00000010000001000
  transition:     4'1000 15'-1-------1----0 ->     4'1011 17'00000010000001011
  transition:     4'1000 15'---------1-1--0 ->     4'1100 17'00000010000001100
  transition:     4'1000 15'--1------1----0 ->     4'0010 17'00000010000000010
  transition:     4'1000 15'---------11---0 ->     4'1101 17'00000010000001101
  transition:     4'1000 15'--------------1 ->     4'1000 17'00000010000001000
  transition:     4'0100 15'---------0----0 ->     4'0100 17'00100000000000100
  transition:     4'0100 15'000000000100000 ->     4'0000 17'00100000000000000
  transition:     4'0100 15'---1-----1----0 ->     4'0011 17'00100000000000011
  transition:     4'0100 15'----1----1----0 ->     4'0101 17'00100000000000101
  transition:     4'0100 15'-----1---1----0 ->     4'0110 17'00100000000000110
  transition:     4'0100 15'------1--1----0 ->     4'0100 17'00100000000000100
  transition:     4'0100 15'---------1---10 ->     4'1001 17'00100000000001001
  transition:     4'0100 15'---------1--1-0 ->     4'1010 17'00100000000001010
  transition:     4'0100 15'-------1-1----0 ->     4'0001 17'00100000000000001
  transition:     4'0100 15'--------11----0 ->     4'0111 17'00100000000000111
  transition:     4'0100 15'1--------1----0 ->     4'1000 17'00100000000001000
  transition:     4'0100 15'-1-------1----0 ->     4'1011 17'00100000000001011
  transition:     4'0100 15'---------1-1--0 ->     4'1100 17'00100000000001100
  transition:     4'0100 15'--1------1----0 ->     4'0010 17'00100000000000010
  transition:     4'0100 15'---------11---0 ->     4'1101 17'00100000000001101
  transition:     4'0100 15'--------------1 ->     4'0100 17'00100000000000100
  transition:     4'1100 15'---------0----0 ->     4'1100 17'00000000100001100
  transition:     4'1100 15'000000000100000 ->     4'0000 17'00000000100000000
  transition:     4'1100 15'---1-----1----0 ->     4'0011 17'00000000100000011
  transition:     4'1100 15'----1----1----0 ->     4'0101 17'00000000100000101
  transition:     4'1100 15'-----1---1----0 ->     4'0110 17'00000000100000110
  transition:     4'1100 15'------1--1----0 ->     4'0100 17'00000000100000100
  transition:     4'1100 15'---------1---10 ->     4'1001 17'00000000100001001
  transition:     4'1100 15'---------1--1-0 ->     4'1010 17'00000000100001010
  transition:     4'1100 15'-------1-1----0 ->     4'0001 17'00000000100000001
  transition:     4'1100 15'--------11----0 ->     4'0111 17'00000000100000111
  transition:     4'1100 15'1--------1----0 ->     4'1000 17'00000000100001000
  transition:     4'1100 15'-1-------1----0 ->     4'1011 17'00000000100001011
  transition:     4'1100 15'---------1-1--0 ->     4'1100 17'00000000100001100
  transition:     4'1100 15'--1------1----0 ->     4'0010 17'00000000100000010
  transition:     4'1100 15'---------11---0 ->     4'1101 17'00000000100001101
  transition:     4'1100 15'--------------1 ->     4'1100 17'00000000100001100
  transition:     4'0010 15'---------0----0 ->     4'0010 17'01000000000000010
  transition:     4'0010 15'000000000100000 ->     4'0000 17'01000000000000000
  transition:     4'0010 15'---1-----1----0 ->     4'0011 17'01000000000000011
  transition:     4'0010 15'----1----1----0 ->     4'0101 17'01000000000000101
  transition:     4'0010 15'-----1---1----0 ->     4'0110 17'01000000000000110
  transition:     4'0010 15'------1--1----0 ->     4'0100 17'01000000000000100
  transition:     4'0010 15'---------1---10 ->     4'1001 17'01000000000001001
  transition:     4'0010 15'---------1--1-0 ->     4'1010 17'01000000000001010
  transition:     4'0010 15'-------1-1----0 ->     4'0001 17'01000000000000001
  transition:     4'0010 15'--------11----0 ->     4'0111 17'01000000000000111
  transition:     4'0010 15'1--------1----0 ->     4'1000 17'01000000000001000
  transition:     4'0010 15'-1-------1----0 ->     4'1011 17'01000000000001011
  transition:     4'0010 15'---------1-1--0 ->     4'1100 17'01000000000001100
  transition:     4'0010 15'--1------1----0 ->     4'0010 17'01000000000000010
  transition:     4'0010 15'---------11---0 ->     4'1101 17'01000000000001101
  transition:     4'0010 15'--------------1 ->     4'0010 17'01000000000000010
  transition:     4'1010 15'---------0----0 ->     4'1010 17'00000000000101010
  transition:     4'1010 15'000000000100000 ->     4'0000 17'00000000000100000
  transition:     4'1010 15'---1-----1----0 ->     4'0011 17'00000000000100011
  transition:     4'1010 15'----1----1----0 ->     4'0101 17'00000000000100101
  transition:     4'1010 15'-----1---1----0 ->     4'0110 17'00000000000100110
  transition:     4'1010 15'------1--1----0 ->     4'0100 17'00000000000100100
  transition:     4'1010 15'---------1---10 ->     4'1001 17'00000000000101001
  transition:     4'1010 15'---------1--1-0 ->     4'1010 17'00000000000101010
  transition:     4'1010 15'-------1-1----0 ->     4'0001 17'00000000000100001
  transition:     4'1010 15'--------11----0 ->     4'0111 17'00000000000100111
  transition:     4'1010 15'1--------1----0 ->     4'1000 17'00000000000101000
  transition:     4'1010 15'-1-------1----0 ->     4'1011 17'00000000000101011
  transition:     4'1010 15'---------1-1--0 ->     4'1100 17'00000000000101100
  transition:     4'1010 15'--1------1----0 ->     4'0010 17'00000000000100010
  transition:     4'1010 15'---------11---0 ->     4'1101 17'00000000000101101
  transition:     4'1010 15'--------------1 ->     4'1010 17'00000000000101010
  transition:     4'0110 15'---------0----0 ->     4'0110 17'00001000000000110
  transition:     4'0110 15'000000000100000 ->     4'0000 17'00001000000000000
  transition:     4'0110 15'---1-----1----0 ->     4'0011 17'00001000000000011
  transition:     4'0110 15'----1----1----0 ->     4'0101 17'00001000000000101
  transition:     4'0110 15'-----1---1----0 ->     4'0110 17'00001000000000110
  transition:     4'0110 15'------1--1----0 ->     4'0100 17'00001000000000100
  transition:     4'0110 15'---------1---10 ->     4'1001 17'00001000000001001
  transition:     4'0110 15'---------1--1-0 ->     4'1010 17'00001000000001010
  transition:     4'0110 15'-------1-1----0 ->     4'0001 17'00001000000000001
  transition:     4'0110 15'--------11----0 ->     4'0111 17'00001000000000111
  transition:     4'0110 15'1--------1----0 ->     4'1000 17'00001000000001000
  transition:     4'0110 15'-1-------1----0 ->     4'1011 17'00001000000001011
  transition:     4'0110 15'---------1-1--0 ->     4'1100 17'00001000000001100
  transition:     4'0110 15'--1------1----0 ->     4'0010 17'00001000000000010
  transition:     4'0110 15'---------11---0 ->     4'1101 17'00001000000001101
  transition:     4'0110 15'--------------1 ->     4'0110 17'00001000000000110
  transition:     4'0001 15'---------0----0 ->     4'0001 17'10000000000000001
  transition:     4'0001 15'000000000100000 ->     4'0000 17'10000000000000000
  transition:     4'0001 15'---1-----1----0 ->     4'0011 17'10000000000000011
  transition:     4'0001 15'----1----1----0 ->     4'0101 17'10000000000000101
  transition:     4'0001 15'-----1---1----0 ->     4'0110 17'10000000000000110
  transition:     4'0001 15'------1--1----0 ->     4'0100 17'10000000000000100
  transition:     4'0001 15'---------1---10 ->     4'1001 17'10000000000001001
  transition:     4'0001 15'---------1--1-0 ->     4'1010 17'10000000000001010
  transition:     4'0001 15'-------1-1----0 ->     4'0001 17'10000000000000001
  transition:     4'0001 15'--------11----0 ->     4'0111 17'10000000000000111
  transition:     4'0001 15'1--------1----0 ->     4'1000 17'10000000000001000
  transition:     4'0001 15'-1-------1----0 ->     4'1011 17'10000000000001011
  transition:     4'0001 15'---------1-1--0 ->     4'1100 17'10000000000001100
  transition:     4'0001 15'--1------1----0 ->     4'0010 17'10000000000000010
  transition:     4'0001 15'---------11---0 ->     4'1101 17'10000000000001101
  transition:     4'0001 15'--------------1 ->     4'0001 17'10000000000000001
  transition:     4'1001 15'---------0----0 ->     4'1001 17'00000000000011001
  transition:     4'1001 15'000000000100000 ->     4'0000 17'00000000000010000
  transition:     4'1001 15'---1-----1----0 ->     4'0011 17'00000000000010011
  transition:     4'1001 15'----1----1----0 ->     4'0101 17'00000000000010101
  transition:     4'1001 15'-----1---1----0 ->     4'0110 17'00000000000010110
  transition:     4'1001 15'------1--1----0 ->     4'0100 17'00000000000010100
  transition:     4'1001 15'---------1---10 ->     4'1001 17'00000000000011001
  transition:     4'1001 15'---------1--1-0 ->     4'1010 17'00000000000011010
  transition:     4'1001 15'-------1-1----0 ->     4'0001 17'00000000000010001
  transition:     4'1001 15'--------11----0 ->     4'0111 17'00000000000010111
  transition:     4'1001 15'1--------1----0 ->     4'1000 17'00000000000011000
  transition:     4'1001 15'-1-------1----0 ->     4'1011 17'00000000000011011
  transition:     4'1001 15'---------1-1--0 ->     4'1100 17'00000000000011100
  transition:     4'1001 15'--1------1----0 ->     4'0010 17'00000000000010010
  transition:     4'1001 15'---------11---0 ->     4'1101 17'00000000000011101
  transition:     4'1001 15'--------------1 ->     4'1001 17'00000000000011001
  transition:     4'0101 15'---------0----0 ->     4'0101 17'00010000000000101
  transition:     4'0101 15'000000000100000 ->     4'0000 17'00010000000000000
  transition:     4'0101 15'---1-----1----0 ->     4'0011 17'00010000000000011
  transition:     4'0101 15'----1----1----0 ->     4'0101 17'00010000000000101
  transition:     4'0101 15'-----1---1----0 ->     4'0110 17'00010000000000110
  transition:     4'0101 15'------1--1----0 ->     4'0100 17'00010000000000100
  transition:     4'0101 15'---------1---10 ->     4'1001 17'00010000000001001
  transition:     4'0101 15'---------1--1-0 ->     4'1010 17'00010000000001010
  transition:     4'0101 15'-------1-1----0 ->     4'0001 17'00010000000000001
  transition:     4'0101 15'--------11----0 ->     4'0111 17'00010000000000111
  transition:     4'0101 15'1--------1----0 ->     4'1000 17'00010000000001000
  transition:     4'0101 15'-1-------1----0 ->     4'1011 17'00010000000001011
  transition:     4'0101 15'---------1-1--0 ->     4'1100 17'00010000000001100
  transition:     4'0101 15'--1------1----0 ->     4'0010 17'00010000000000010
  transition:     4'0101 15'---------11---0 ->     4'1101 17'00010000000001101
  transition:     4'0101 15'--------------1 ->     4'0101 17'00010000000000101
  transition:     4'1101 15'---------0----0 ->     4'1101 17'00000000001001101
  transition:     4'1101 15'000000000100000 ->     4'0000 17'00000000001000000
  transition:     4'1101 15'---1-----1----0 ->     4'0011 17'00000000001000011
  transition:     4'1101 15'----1----1----0 ->     4'0101 17'00000000001000101
  transition:     4'1101 15'-----1---1----0 ->     4'0110 17'00000000001000110
  transition:     4'1101 15'------1--1----0 ->     4'0100 17'00000000001000100
  transition:     4'1101 15'---------1---10 ->     4'1001 17'00000000001001001
  transition:     4'1101 15'---------1--1-0 ->     4'1010 17'00000000001001010
  transition:     4'1101 15'-------1-1----0 ->     4'0001 17'00000000001000001
  transition:     4'1101 15'--------11----0 ->     4'0111 17'00000000001000111
  transition:     4'1101 15'1--------1----0 ->     4'1000 17'00000000001001000
  transition:     4'1101 15'-1-------1----0 ->     4'1011 17'00000000001001011
  transition:     4'1101 15'---------1-1--0 ->     4'1100 17'00000000001001100
  transition:     4'1101 15'--1------1----0 ->     4'0010 17'00000000001000010
  transition:     4'1101 15'---------11---0 ->     4'1101 17'00000000001001101
  transition:     4'1101 15'--------------1 ->     4'1101 17'00000000001001101
  transition:     4'0011 15'---------0----0 ->     4'0011 17'00000000010000011
  transition:     4'0011 15'000000000100000 ->     4'0000 17'00000000010000000
  transition:     4'0011 15'---1-----1----0 ->     4'0011 17'00000000010000011
  transition:     4'0011 15'----1----1----0 ->     4'0101 17'00000000010000101
  transition:     4'0011 15'-----1---1----0 ->     4'0110 17'00000000010000110
  transition:     4'0011 15'------1--1----0 ->     4'0100 17'00000000010000100
  transition:     4'0011 15'---------1---10 ->     4'1001 17'00000000010001001
  transition:     4'0011 15'---------1--1-0 ->     4'1010 17'00000000010001010
  transition:     4'0011 15'-------1-1----0 ->     4'0001 17'00000000010000001
  transition:     4'0011 15'--------11----0 ->     4'0111 17'00000000010000111
  transition:     4'0011 15'1--------1----0 ->     4'1000 17'00000000010001000
  transition:     4'0011 15'-1-------1----0 ->     4'1011 17'00000000010001011
  transition:     4'0011 15'---------1-1--0 ->     4'1100 17'00000000010001100
  transition:     4'0011 15'--1------1----0 ->     4'0010 17'00000000010000010
  transition:     4'0011 15'---------11---0 ->     4'1101 17'00000000010001101
  transition:     4'0011 15'--------------1 ->     4'0011 17'00000000010000011
  transition:     4'1011 15'---------0----0 ->     4'1011 17'00000001000001011
  transition:     4'1011 15'000000000100000 ->     4'0000 17'00000001000000000
  transition:     4'1011 15'---1-----1----0 ->     4'0011 17'00000001000000011
  transition:     4'1011 15'----1----1----0 ->     4'0101 17'00000001000000101
  transition:     4'1011 15'-----1---1----0 ->     4'0110 17'00000001000000110
  transition:     4'1011 15'------1--1----0 ->     4'0100 17'00000001000000100
  transition:     4'1011 15'---------1---10 ->     4'1001 17'00000001000001001
  transition:     4'1011 15'---------1--1-0 ->     4'1010 17'00000001000001010
  transition:     4'1011 15'-------1-1----0 ->     4'0001 17'00000001000000001
  transition:     4'1011 15'--------11----0 ->     4'0111 17'00000001000000111
  transition:     4'1011 15'1--------1----0 ->     4'1000 17'00000001000001000
  transition:     4'1011 15'-1-------1----0 ->     4'1011 17'00000001000001011
  transition:     4'1011 15'---------1-1--0 ->     4'1100 17'00000001000001100
  transition:     4'1011 15'--1------1----0 ->     4'0010 17'00000001000000010
  transition:     4'1011 15'---------11---0 ->     4'1101 17'00000001000001101
  transition:     4'1011 15'--------------1 ->     4'1011 17'00000001000001011
  transition:     4'0111 15'---------0----0 ->     4'0111 17'00000100000000111
  transition:     4'0111 15'000000000100000 ->     4'0000 17'00000100000000000
  transition:     4'0111 15'---1-----1----0 ->     4'0011 17'00000100000000011
  transition:     4'0111 15'----1----1----0 ->     4'0101 17'00000100000000101
  transition:     4'0111 15'-----1---1----0 ->     4'0110 17'00000100000000110
  transition:     4'0111 15'------1--1----0 ->     4'0100 17'00000100000000100
  transition:     4'0111 15'---------1---10 ->     4'1001 17'00000100000001001
  transition:     4'0111 15'---------1--1-0 ->     4'1010 17'00000100000001010
  transition:     4'0111 15'-------1-1----0 ->     4'0001 17'00000100000000001
  transition:     4'0111 15'--------11----0 ->     4'0111 17'00000100000000111
  transition:     4'0111 15'1--------1----0 ->     4'1000 17'00000100000001000
  transition:     4'0111 15'-1-------1----0 ->     4'1011 17'00000100000001011
  transition:     4'0111 15'---------1-1--0 ->     4'1100 17'00000100000001100
  transition:     4'0111 15'--1------1----0 ->     4'0010 17'00000100000000010
  transition:     4'0111 15'---------11---0 ->     4'1101 17'00000100000001101
  transition:     4'0111 15'--------------1 ->     4'0111 17'00000100000000111

14.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\decode.oc_alu_mode$4590' from module `\core'.

14.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 17 unused cells and 17 unused wires.
<suppressed ~19 debug messages>

14.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\decode.oc_alu_mode$4590' from module `\core'.
  Removing unused output signal $flatten\decode.$0\oc_alu_mode[3:0] [0].
  Removing unused output signal $flatten\decode.$0\oc_alu_mode[3:0] [1].
  Removing unused output signal $flatten\decode.$0\oc_alu_mode[3:0] [2].
  Removing unused output signal $flatten\decode.$0\oc_alu_mode[3:0] [3].

14.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\decode.oc_alu_mode$4590' from module `\core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  0000 -> -------------1
  1000 -> ------------1-
  0100 -> -----------1--
  1100 -> ----------1---
  0010 -> ---------1----
  1010 -> --------1-----
  0110 -> -------1------
  0001 -> ------1-------
  1001 -> -----1--------
  0101 -> ----1---------
  1101 -> ---1----------
  0011 -> --1-----------
  1011 -> -1------------
  0111 -> 1-------------

14.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\decode.oc_alu_mode$4590' from module `core':
-------------------------------------

  Information on FSM $fsm$\decode.oc_alu_mode$4590 (\decode.oc_alu_mode):

  Number of input signals:   15
  Number of output signals:  13
  Number of state bits:      14

  Input signals:
    0: \i_rst
    1: $flatten\decode.$procmux$4000_CMP
    2: $flatten\decode.$procmux$3999_CMP
    3: $flatten\decode.$procmux$3991_CMP
    4: $flatten\decode.$procmux$3986_CMP
    5: $flatten\decode.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:482$627_Y
    6: $auto$opt_reduce.cc:134:opt_pmux$4575
    7: $auto$opt_reduce.cc:134:opt_pmux$4577
    8: $auto$opt_reduce.cc:134:opt_pmux$4579
    9: $auto$opt_reduce.cc:134:opt_pmux$4581
   10: $auto$opt_reduce.cc:134:opt_pmux$4583
   11: $auto$opt_reduce.cc:134:opt_pmux$4585
   12: $auto$opt_reduce.cc:134:opt_pmux$4569
   13: $auto$opt_reduce.cc:134:opt_pmux$4571
   14: $auto$opt_reduce.cc:134:opt_pmux$4573

  Output signals:
    0: \execute.alu_mul_div.i_mul
    1: \execute.alu_mul_div.i_div
    2: \execute.alu_mul_div.i_mod
    3: $flatten\execute.\alu.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:54$74_Y
    4: $flatten\execute.\alu.$procmux$4370_CMP
    5: $flatten\execute.\alu.$procmux$4371_CMP
    6: $flatten\execute.\alu.$procmux$4374_CMP
    7: $flatten\execute.\alu.$procmux$4375_CMP
    8: $flatten\execute.\alu.$procmux$4376_CMP
    9: $flatten\execute.\alu.$procmux$4377_CMP
   10: $flatten\execute.\alu.$procmux$4378_CMP
   11: $flatten\execute.\alu.$procmux$4380_CMP
   12: $flatten\execute.\alu.$procmux$4381_CMP

  State encoding:
    0: 14'-------------1
    1: 14'------------1-
    2: 14'-----------1--
    3: 14'----------1---
    4: 14'---------1----
    5: 14'--------1-----
    6: 14'-------1------
    7: 14'------1-------
    8: 14'-----1--------
    9: 14'----1---------
   10: 14'---1----------
   11: 14'--1-----------
   12: 14'-1------------
   13: 14'1-------------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 15'000000000100000   ->     0 13'0000000000000
      1:     0 15'---------0----0   ->     0 13'0000000000000
      2:     0 15'--------------1   ->     0 13'0000000000000
      3:     0 15'1--------1----0   ->     1 13'0000000000000
      4:     0 15'------1--1----0   ->     2 13'0000000000000
      5:     0 15'---------1-1--0   ->     3 13'0000000000000
      6:     0 15'--1------1----0   ->     4 13'0000000000000
      7:     0 15'---------1--1-0   ->     5 13'0000000000000
      8:     0 15'-----1---1----0   ->     6 13'0000000000000
      9:     0 15'-------1-1----0   ->     7 13'0000000000000
     10:     0 15'---------1---10   ->     8 13'0000000000000
     11:     0 15'----1----1----0   ->     9 13'0000000000000
     12:     0 15'---------11---0   ->    10 13'0000000000000
     13:     0 15'---1-----1----0   ->    11 13'0000000000000
     14:     0 15'-1-------1----0   ->    12 13'0000000000000
     15:     0 15'--------11----0   ->    13 13'0000000000000
     16:     1 15'000000000100000   ->     0 13'0000001000000
     17:     1 15'---------0----0   ->     1 13'0000001000000
     18:     1 15'1--------1----0   ->     1 13'0000001000000
     19:     1 15'--------------1   ->     1 13'0000001000000
     20:     1 15'------1--1----0   ->     2 13'0000001000000
     21:     1 15'---------1-1--0   ->     3 13'0000001000000
     22:     1 15'--1------1----0   ->     4 13'0000001000000
     23:     1 15'---------1--1-0   ->     5 13'0000001000000
     24:     1 15'-----1---1----0   ->     6 13'0000001000000
     25:     1 15'-------1-1----0   ->     7 13'0000001000000
     26:     1 15'---------1---10   ->     8 13'0000001000000
     27:     1 15'----1----1----0   ->     9 13'0000001000000
     28:     1 15'---------11---0   ->    10 13'0000001000000
     29:     1 15'---1-----1----0   ->    11 13'0000001000000
     30:     1 15'-1-------1----0   ->    12 13'0000001000000
     31:     1 15'--------11----0   ->    13 13'0000001000000
     32:     2 15'000000000100000   ->     0 13'0010000000000
     33:     2 15'1--------1----0   ->     1 13'0010000000000
     34:     2 15'---------0----0   ->     2 13'0010000000000
     35:     2 15'------1--1----0   ->     2 13'0010000000000
     36:     2 15'--------------1   ->     2 13'0010000000000
     37:     2 15'---------1-1--0   ->     3 13'0010000000000
     38:     2 15'--1------1----0   ->     4 13'0010000000000
     39:     2 15'---------1--1-0   ->     5 13'0010000000000
     40:     2 15'-----1---1----0   ->     6 13'0010000000000
     41:     2 15'-------1-1----0   ->     7 13'0010000000000
     42:     2 15'---------1---10   ->     8 13'0010000000000
     43:     2 15'----1----1----0   ->     9 13'0010000000000
     44:     2 15'---------11---0   ->    10 13'0010000000000
     45:     2 15'---1-----1----0   ->    11 13'0010000000000
     46:     2 15'-1-------1----0   ->    12 13'0010000000000
     47:     2 15'--------11----0   ->    13 13'0010000000000
     48:     3 15'000000000100000   ->     0 13'0000000010000
     49:     3 15'1--------1----0   ->     1 13'0000000010000
     50:     3 15'------1--1----0   ->     2 13'0000000010000
     51:     3 15'---------1-1--0   ->     3 13'0000000010000
     52:     3 15'---------0----0   ->     3 13'0000000010000
     53:     3 15'--------------1   ->     3 13'0000000010000
     54:     3 15'--1------1----0   ->     4 13'0000000010000
     55:     3 15'---------1--1-0   ->     5 13'0000000010000
     56:     3 15'-----1---1----0   ->     6 13'0000000010000
     57:     3 15'-------1-1----0   ->     7 13'0000000010000
     58:     3 15'---------1---10   ->     8 13'0000000010000
     59:     3 15'----1----1----0   ->     9 13'0000000010000
     60:     3 15'---------11---0   ->    10 13'0000000010000
     61:     3 15'---1-----1----0   ->    11 13'0000000010000
     62:     3 15'-1-------1----0   ->    12 13'0000000010000
     63:     3 15'--------11----0   ->    13 13'0000000010000
     64:     4 15'000000000100000   ->     0 13'0100000000000
     65:     4 15'1--------1----0   ->     1 13'0100000000000
     66:     4 15'------1--1----0   ->     2 13'0100000000000
     67:     4 15'---------1-1--0   ->     3 13'0100000000000
     68:     4 15'---------0----0   ->     4 13'0100000000000
     69:     4 15'--1------1----0   ->     4 13'0100000000000
     70:     4 15'--------------1   ->     4 13'0100000000000
     71:     4 15'---------1--1-0   ->     5 13'0100000000000
     72:     4 15'-----1---1----0   ->     6 13'0100000000000
     73:     4 15'-------1-1----0   ->     7 13'0100000000000
     74:     4 15'---------1---10   ->     8 13'0100000000000
     75:     4 15'----1----1----0   ->     9 13'0100000000000
     76:     4 15'---------11---0   ->    10 13'0100000000000
     77:     4 15'---1-----1----0   ->    11 13'0100000000000
     78:     4 15'-1-------1----0   ->    12 13'0100000000000
     79:     4 15'--------11----0   ->    13 13'0100000000000
     80:     5 15'000000000100000   ->     0 13'0000000000010
     81:     5 15'1--------1----0   ->     1 13'0000000000010
     82:     5 15'------1--1----0   ->     2 13'0000000000010
     83:     5 15'---------1-1--0   ->     3 13'0000000000010
     84:     5 15'--1------1----0   ->     4 13'0000000000010
     85:     5 15'---------1--1-0   ->     5 13'0000000000010
     86:     5 15'---------0----0   ->     5 13'0000000000010
     87:     5 15'--------------1   ->     5 13'0000000000010
     88:     5 15'-----1---1----0   ->     6 13'0000000000010
     89:     5 15'-------1-1----0   ->     7 13'0000000000010
     90:     5 15'---------1---10   ->     8 13'0000000000010
     91:     5 15'----1----1----0   ->     9 13'0000000000010
     92:     5 15'---------11---0   ->    10 13'0000000000010
     93:     5 15'---1-----1----0   ->    11 13'0000000000010
     94:     5 15'-1-------1----0   ->    12 13'0000000000010
     95:     5 15'--------11----0   ->    13 13'0000000000010
     96:     6 15'000000000100000   ->     0 13'0000100000000
     97:     6 15'1--------1----0   ->     1 13'0000100000000
     98:     6 15'------1--1----0   ->     2 13'0000100000000
     99:     6 15'---------1-1--0   ->     3 13'0000100000000
    100:     6 15'--1------1----0   ->     4 13'0000100000000
    101:     6 15'---------1--1-0   ->     5 13'0000100000000
    102:     6 15'---------0----0   ->     6 13'0000100000000
    103:     6 15'-----1---1----0   ->     6 13'0000100000000
    104:     6 15'--------------1   ->     6 13'0000100000000
    105:     6 15'-------1-1----0   ->     7 13'0000100000000
    106:     6 15'---------1---10   ->     8 13'0000100000000
    107:     6 15'----1----1----0   ->     9 13'0000100000000
    108:     6 15'---------11---0   ->    10 13'0000100000000
    109:     6 15'---1-----1----0   ->    11 13'0000100000000
    110:     6 15'-1-------1----0   ->    12 13'0000100000000
    111:     6 15'--------11----0   ->    13 13'0000100000000
    112:     7 15'000000000100000   ->     0 13'1000000000000
    113:     7 15'1--------1----0   ->     1 13'1000000000000
    114:     7 15'------1--1----0   ->     2 13'1000000000000
    115:     7 15'---------1-1--0   ->     3 13'1000000000000
    116:     7 15'--1------1----0   ->     4 13'1000000000000
    117:     7 15'---------1--1-0   ->     5 13'1000000000000
    118:     7 15'-----1---1----0   ->     6 13'1000000000000
    119:     7 15'---------0----0   ->     7 13'1000000000000
    120:     7 15'-------1-1----0   ->     7 13'1000000000000
    121:     7 15'--------------1   ->     7 13'1000000000000
    122:     7 15'---------1---10   ->     8 13'1000000000000
    123:     7 15'----1----1----0   ->     9 13'1000000000000
    124:     7 15'---------11---0   ->    10 13'1000000000000
    125:     7 15'---1-----1----0   ->    11 13'1000000000000
    126:     7 15'-1-------1----0   ->    12 13'1000000000000
    127:     7 15'--------11----0   ->    13 13'1000000000000
    128:     8 15'000000000100000   ->     0 13'0000000000001
    129:     8 15'1--------1----0   ->     1 13'0000000000001
    130:     8 15'------1--1----0   ->     2 13'0000000000001
    131:     8 15'---------1-1--0   ->     3 13'0000000000001
    132:     8 15'--1------1----0   ->     4 13'0000000000001
    133:     8 15'---------1--1-0   ->     5 13'0000000000001
    134:     8 15'-----1---1----0   ->     6 13'0000000000001
    135:     8 15'-------1-1----0   ->     7 13'0000000000001
    136:     8 15'---------1---10   ->     8 13'0000000000001
    137:     8 15'---------0----0   ->     8 13'0000000000001
    138:     8 15'--------------1   ->     8 13'0000000000001
    139:     8 15'----1----1----0   ->     9 13'0000000000001
    140:     8 15'---------11---0   ->    10 13'0000000000001
    141:     8 15'---1-----1----0   ->    11 13'0000000000001
    142:     8 15'-1-------1----0   ->    12 13'0000000000001
    143:     8 15'--------11----0   ->    13 13'0000000000001
    144:     9 15'000000000100000   ->     0 13'0001000000000
    145:     9 15'1--------1----0   ->     1 13'0001000000000
    146:     9 15'------1--1----0   ->     2 13'0001000000000
    147:     9 15'---------1-1--0   ->     3 13'0001000000000
    148:     9 15'--1------1----0   ->     4 13'0001000000000
    149:     9 15'---------1--1-0   ->     5 13'0001000000000
    150:     9 15'-----1---1----0   ->     6 13'0001000000000
    151:     9 15'-------1-1----0   ->     7 13'0001000000000
    152:     9 15'---------1---10   ->     8 13'0001000000000
    153:     9 15'---------0----0   ->     9 13'0001000000000
    154:     9 15'----1----1----0   ->     9 13'0001000000000
    155:     9 15'--------------1   ->     9 13'0001000000000
    156:     9 15'---------11---0   ->    10 13'0001000000000
    157:     9 15'---1-----1----0   ->    11 13'0001000000000
    158:     9 15'-1-------1----0   ->    12 13'0001000000000
    159:     9 15'--------11----0   ->    13 13'0001000000000
    160:    10 15'000000000100000   ->     0 13'0000000000100
    161:    10 15'1--------1----0   ->     1 13'0000000000100
    162:    10 15'------1--1----0   ->     2 13'0000000000100
    163:    10 15'---------1-1--0   ->     3 13'0000000000100
    164:    10 15'--1------1----0   ->     4 13'0000000000100
    165:    10 15'---------1--1-0   ->     5 13'0000000000100
    166:    10 15'-----1---1----0   ->     6 13'0000000000100
    167:    10 15'-------1-1----0   ->     7 13'0000000000100
    168:    10 15'---------1---10   ->     8 13'0000000000100
    169:    10 15'----1----1----0   ->     9 13'0000000000100
    170:    10 15'---------11---0   ->    10 13'0000000000100
    171:    10 15'---------0----0   ->    10 13'0000000000100
    172:    10 15'--------------1   ->    10 13'0000000000100
    173:    10 15'---1-----1----0   ->    11 13'0000000000100
    174:    10 15'-1-------1----0   ->    12 13'0000000000100
    175:    10 15'--------11----0   ->    13 13'0000000000100
    176:    11 15'000000000100000   ->     0 13'0000000001000
    177:    11 15'1--------1----0   ->     1 13'0000000001000
    178:    11 15'------1--1----0   ->     2 13'0000000001000
    179:    11 15'---------1-1--0   ->     3 13'0000000001000
    180:    11 15'--1------1----0   ->     4 13'0000000001000
    181:    11 15'---------1--1-0   ->     5 13'0000000001000
    182:    11 15'-----1---1----0   ->     6 13'0000000001000
    183:    11 15'-------1-1----0   ->     7 13'0000000001000
    184:    11 15'---------1---10   ->     8 13'0000000001000
    185:    11 15'----1----1----0   ->     9 13'0000000001000
    186:    11 15'---------11---0   ->    10 13'0000000001000
    187:    11 15'---------0----0   ->    11 13'0000000001000
    188:    11 15'---1-----1----0   ->    11 13'0000000001000
    189:    11 15'--------------1   ->    11 13'0000000001000
    190:    11 15'-1-------1----0   ->    12 13'0000000001000
    191:    11 15'--------11----0   ->    13 13'0000000001000
    192:    12 15'000000000100000   ->     0 13'0000000100000
    193:    12 15'1--------1----0   ->     1 13'0000000100000
    194:    12 15'------1--1----0   ->     2 13'0000000100000
    195:    12 15'---------1-1--0   ->     3 13'0000000100000
    196:    12 15'--1------1----0   ->     4 13'0000000100000
    197:    12 15'---------1--1-0   ->     5 13'0000000100000
    198:    12 15'-----1---1----0   ->     6 13'0000000100000
    199:    12 15'-------1-1----0   ->     7 13'0000000100000
    200:    12 15'---------1---10   ->     8 13'0000000100000
    201:    12 15'----1----1----0   ->     9 13'0000000100000
    202:    12 15'---------11---0   ->    10 13'0000000100000
    203:    12 15'---1-----1----0   ->    11 13'0000000100000
    204:    12 15'---------0----0   ->    12 13'0000000100000
    205:    12 15'-1-------1----0   ->    12 13'0000000100000
    206:    12 15'--------------1   ->    12 13'0000000100000
    207:    12 15'--------11----0   ->    13 13'0000000100000
    208:    13 15'000000000100000   ->     0 13'0000010000000
    209:    13 15'1--------1----0   ->     1 13'0000010000000
    210:    13 15'------1--1----0   ->     2 13'0000010000000
    211:    13 15'---------1-1--0   ->     3 13'0000010000000
    212:    13 15'--1------1----0   ->     4 13'0000010000000
    213:    13 15'---------1--1-0   ->     5 13'0000010000000
    214:    13 15'-----1---1----0   ->     6 13'0000010000000
    215:    13 15'-------1-1----0   ->     7 13'0000010000000
    216:    13 15'---------1---10   ->     8 13'0000010000000
    217:    13 15'----1----1----0   ->     9 13'0000010000000
    218:    13 15'---------11---0   ->    10 13'0000010000000
    219:    13 15'---1-----1----0   ->    11 13'0000010000000
    220:    13 15'-1-------1----0   ->    12 13'0000010000000
    221:    13 15'---------0----0   ->    13 13'0000010000000
    222:    13 15'--------11----0   ->    13 13'0000010000000
    223:    13 15'--------------1   ->    13 13'0000010000000

-------------------------------------

14.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\decode.oc_alu_mode$4590' from module `\core'.

14.9. Executing OPT pass (performing simple optimizations).

14.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~28 debug messages>

14.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
<suppressed ~39 debug messages>
Removed a total of 13 cells.

14.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~104 debug messages>

14.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

14.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\memwb.$procdff$4490 ($dff) from module core (D = $flatten\memwb.$procmux$1403_Y, Q = \memwb.o_mem_req, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4763 ($sdff) from module core (D = $flatten\memwb.$procmux$1403_Y, Q = \memwb.o_mem_req).
Adding SRST signal on $flatten\fetch.$procdff$4502 ($dff) from module core (D = $flatten\fetch.$procmux$1502_Y, Q = \fetch.pc_reset_override, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$4767 ($sdff) from module core (D = 1'0, Q = \fetch.pc_reset_override).
Adding SRST signal on $flatten\fetch.$procdff$4501 ($dff) from module core (D = $flatten\fetch.$procmux$1497_Y, Q = \fetch.pc_flush_override, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4769 ($sdff) from module core (D = 1'1, Q = \fetch.pc_flush_override).
Adding SRST signal on $flatten\fetch.$procdff$4500 ($dff) from module core (D = $flatten\fetch.$procmux$1492_Y, Q = \fetch.flush_event_invalidate, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4771 ($sdff) from module core (D = 1'1, Q = \fetch.flush_event_invalidate).
Adding SRST signal on $flatten\fetch.$procdff$4499 ($dff) from module core (D = $flatten\fetch.$procmux$1487_Y, Q = \fetch.instr_wait, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4773 ($sdff) from module core (D = $flatten\fetch.$procmux$1487_Y, Q = \fetch.instr_wait).
Adding EN signal on $flatten\fetch.$procdff$4498 ($dff) from module core (D = \fetch.out_jmp_predict, Q = \fetch.o_jmp_predict).
Adding EN signal on $flatten\fetch.$procdff$4497 ($dff) from module core (D = { \fetch.branch_pred_instr [31:16] \fetch.out_instr [15:11] \fetch.branch_pred_instr [10:0] }, Q = \fetch.o_instr).
Adding EN signal on $flatten\fetch.$procdff$4495 ($dff) from module core (D = \o_req_addr, Q = \fetch.prev_request_pc).
Adding SRST signal on $flatten\fetch.$procdff$4493 ($dff) from module core (D = $flatten\fetch.$procmux$1411_Y, Q = \fetch.out_buffer_valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4780 ($sdff) from module core (D = $flatten\fetch.$procmux$1411_Y, Q = \fetch.out_buffer_valid).
Adding EN signal on $flatten\fetch.$procdff$4492 ($dff) from module core (D = \fetch.current_req_branch_pred, Q = \fetch.out_buffer_data_pred).
Adding EN signal on $flatten\fetch.$procdff$4491 ($dff) from module core (D = \i_req_data, Q = \fetch.out_buffer_data_instr).
Adding SRST signal on $flatten\execute.\sreg_scratch.$procdff$4488 ($dff) from module core (D = $flatten\execute.\sreg_scratch.$procmux$1348_Y, Q = \execute.sreg_scratch.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4800 ($sdff) from module core (D = \execute.reg_r_con, Q = \execute.sreg_scratch.o_d).
Adding SRST signal on $flatten\execute.\sreg_priv_control.$procdff$4503 ($dff) from module core (D = $flatten\execute.\sreg_priv_control.$procmux$1507_Y, Q = \execute.sreg_priv_control.o_d, rval = 16'0000000000000001).
Adding EN signal on $auto$ff.cc:266:slice$4802 ($sdff) from module core (D = \execute.sreg_priv_control.i_d, Q = \execute.sreg_priv_control.o_d).
Adding SRST signal on $flatten\execute.\sreg_jtr_buff.$procdff$4467 ($dff) from module core (D = $flatten\execute.\sreg_jtr_buff.$procmux$1137_Y, Q = \execute.sreg_jtr_buff.o_d, rval = 3'001).
Adding EN signal on $auto$ff.cc:266:slice$4804 ($sdff) from module core (D = \execute.sreg_jtr_buff.i_d, Q = \execute.sreg_jtr_buff.o_d).
Adding SRST signal on $flatten\execute.\sreg_jtr.$procdff$4467 ($dff) from module core (D = $flatten\execute.\sreg_jtr.$procmux$1137_Y, Q = \execute.sreg_jtr.o_d, rval = 3'001).
Adding EN signal on $auto$ff.cc:266:slice$4806 ($sdff) from module core (D = { \execute.sreg_jtr.i_d [2:1] \execute.jtr_in [0] }, Q = \execute.sreg_jtr.o_d).
Adding SRST signal on $flatten\execute.\sreg_irq_pc.$procdff$4488 ($dff) from module core (D = $flatten\execute.\sreg_irq_pc.$procmux$1348_Y, Q = \execute.sreg_irq_pc.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4808 ($sdff) from module core (D = \execute.sreg_irq_pc.i_d, Q = \execute.sreg_irq_pc.o_d).
Adding SRST signal on $flatten\execute.\sreg_irq_flags.$procdff$4468 ($dff) from module core (D = $flatten\execute.\sreg_irq_flags.$procmux$1142_Y, Q = \execute.sreg_irq_flags.o_d, rval = 5'00000).
Adding EN signal on $auto$ff.cc:266:slice$4810 ($sdff) from module core (D = { \execute.sreg_irq_flags.i_d [4] \i_mem_exception \execute.trap_exception \execute.prev_sys \execute.sreg_irq_flags.i_d [0] }, Q = \execute.sreg_irq_flags.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[7].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[7].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[7].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4812 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[7].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[6].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[6].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[6].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4814 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[6].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[5].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[5].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[5].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4816 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[5].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[4].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[4].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[4].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4818 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[4].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[3].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[3].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[3].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4820 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[3].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[2].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[2].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[2].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4822 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[2].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[1].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[1].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[1].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4824 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[1].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\rf.\rf_regs[0].rf_reg.$procdff$4488 ($dff) from module core (D = $flatten\execute.\rf.\rf_regs[0].rf_reg.$procmux$1348_Y, Q = \execute.rf.rf_regs[0].rf_reg.o_d, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4826 ($sdff) from module core (D = \execute.rf.rf_regs[0].rf_reg.i_d, Q = \execute.rf.rf_regs[0].rf_reg.o_d).
Adding SRST signal on $flatten\execute.\pc_high_reg.$procdff$4469 ($dff) from module core (D = $flatten\execute.\pc_high_reg.$procmux$1147_Y, Q = \execute.pc_high_reg.o_d, rval = 8'10000000).
Adding EN signal on $auto$ff.cc:266:slice$4828 ($sdff) from module core (D = \execute.pc_high_reg.i_d, Q = \execute.pc_high_reg.o_d).
Adding SRST signal on $flatten\execute.\pc_high_buff_reg.$procdff$4469 ($dff) from module core (D = $flatten\execute.\pc_high_buff_reg.$procmux$1147_Y, Q = \execute.pc_high_buff_reg.o_d, rval = 8'10000000).
Adding EN signal on $auto$ff.cc:266:slice$4830 ($sdff) from module core (D = \execute.pc_high_buff_reg.i_d, Q = \execute.pc_high_buff_reg.o_d).
Adding SRST signal on $flatten\execute.\pc.$procdff$4489 ($dff) from module core (D = $flatten\execute.\pc.$procmux$1359_Y [0], Q = \execute.pc.o_pc [0], rval = 1'0).
Adding SRST signal on $flatten\execute.\pc.$procdff$4489 ($dff) from module core (D = $flatten\execute.\pc.$procmux$1356_Y [15:1], Q = \execute.pc.o_pc [15:1], rval = 15'000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4833 ($sdff) from module core (D = $flatten\execute.\pc.$procmux$1356_Y [15:1], Q = \execute.pc.o_pc [15:1]).
Adding EN signal on $auto$ff.cc:266:slice$4832 ($sdff) from module core (D = $flatten\execute.\pc.$procmux$1359_Y [0], Q = \execute.pc.o_pc [0]).
Adding EN signal on $flatten\execute.\alu_mul_div.$procdff$4539 ($dff) from module core (D = { 15'000000000000000 \execute.alu.i_l [15] }, Q = \execute.alu_mul_div.div_cur).
Adding EN signal on $flatten\execute.\alu_mul_div.$procdff$4538 ($dff) from module core (D = 16'0000000000000000, Q = \execute.alu_mul_div.div_res).
Adding EN signal on $flatten\execute.\alu_mul_div.$procdff$4537 ($dff) from module core (D = $flatten\execute.\alu_mul_div.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:36$8_Y, Q = \execute.alu_mul_div.mul_res).
Adding SRST signal on $auto$ff.cc:266:slice$4852 ($dffe) from module core (D = \execute.alu.i_l, Q = \execute.alu_mul_div.mul_res, rval = 16'0000000000000000).
Adding SRST signal on $flatten\execute.\alu_mul_div.$procdff$4536 ($dff) from module core (D = $flatten\execute.\alu_mul_div.$procmux$4454_Y, Q = \execute.alu_mul_div.comp, rval = 1'0).
Adding EN signal on $flatten\execute.\alu_mul_div.$procdff$4535 ($dff) from module core (D = $flatten\execute.\alu_mul_div.$procmux$4462_Y, Q = \execute.alu_mul_div.cbit).
Adding EN signal on $flatten\execute.\alu_mul_div.$procdff$4534 ($dff) from module core (D = $flatten\execute.\alu_mul_div.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:51$16_Y, Q = \execute.alu_mul_div.mul_res).
Adding EN signal on $flatten\execute.\alu_mul_div.$procdff$4529 ($dff) from module core (D = $flatten\execute.\alu_mul_div.$procmux$4425_Y, Q = \execute.alu_mul_div.div_cur).
Adding EN signal on $flatten\execute.\alu_mul_div.$procdff$4528 ($dff) from module core (D = $flatten\execute.\alu_mul_div.$or$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:0$45_Y, Q = \execute.alu_mul_div.div_res).
Adding SRST signal on $flatten\execute.\alu_flag_reg.$procdff$4468 ($dff) from module core (D = $flatten\execute.\alu_flag_reg.$procmux$1142_Y, Q = \execute.alu_flag_reg.o_d, rval = 5'00000).
Adding EN signal on $auto$ff.cc:266:slice$4875 ($sdff) from module core (D = \execute.alu_flag_reg.i_d, Q = \execute.alu_flag_reg.o_d).
Adding SRST signal on $flatten\execute.$procdff$4487 ($dff) from module core (D = $flatten\execute.$procmux$1340_Y, Q = \execute.hold_valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4877 ($sdff) from module core (D = 1'1, Q = \execute.hold_valid).
Adding SRST signal on $flatten\execute.$procdff$4486 ($dff) from module core (D = \execute.i_next_ready, Q = \execute.next_ready_delayed, rval = 1'0).
Adding EN signal on $flatten\execute.$procdff$4484 ($dff) from module core (D = $flatten\execute.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:257$1010_Y, Q = \execute.o_mem_long_mode).
Adding EN signal on $flatten\execute.$procdff$4483 ($dff) from module core (D = \decode.oc_mem_width, Q = \execute.o_mem_width).
Adding EN signal on $flatten\execute.$procdff$4482 ($dff) from module core (D = \decode.oc_mem_access, Q = \execute.o_mem_access).
Adding EN signal on $flatten\execute.$procdff$4481 ($dff) from module core (D = \decode.oc_rf_ie, Q = \execute.o_reg_ie).
Adding EN signal on $flatten\execute.$procdff$4480 ($dff) from module core (D = \execute.alu_bus, Q = \execute.o_addr).
Adding EN signal on $flatten\execute.$procdff$4479 ($dff) from module core (D = $flatten\execute.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:250$1009_Y, Q = \execute.o_data).
Adding SRST signal on $flatten\execute.$procdff$4478 ($dff) from module core (D = $flatten\execute.$procmux$1269_Y, Q = \execute.o_submit, rval = 1'0).
Adding EN signal on $flatten\execute.$procdff$4477 ($dff) from module core (D = \execute.computed_mem_addr_high, Q = \execute.o_mem_addr_high).
Adding EN signal on $flatten\execute.$procdff$4476 ($dff) from module core (D = \decode.oc_mem_we, Q = \execute.o_mem_we).
Adding SRST signal on $flatten\execute.$procdff$4475 ($dff) from module core (D = $flatten\execute.$procmux$1263_Y, Q = \execute.prev_sys, rval = 1'0).
Adding SRST signal on $flatten\execute.$procdff$4474 ($dff) from module core (D = $flatten\execute.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:281$1014_Y, Q = \execute.trap_exception, rval = 1'0).
Adding SRST signal on $flatten\execute.$procdff$4473 ($dff) from module core (D = $flatten\execute.$procmux$1254_Y, Q = \execute.mem_stage_pc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4925 ($sdff) from module core (D = \execute.pc.o_pc, Q = \execute.mem_stage_pc).
Adding SRST signal on $flatten\execute.$procdff$4471 ($dff) from module core (D = $flatten\execute.$procmux$1155_Y, Q = \execute.o_c_data_page, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4927 ($sdff) from module core (D = \execute.sreg_priv_control.o_d [1], Q = \execute.o_c_data_page).
Adding SRST signal on $flatten\execute.$procdff$4470 ($dff) from module core (D = \execute.pc_high, Q = \execute.prev_pc_high, rval = 8'00000000).
Adding SRST signal on $flatten\decode.$procdff$4527 ($dff) from module core (D = $flatten\decode.$procmux$1521_Y, Q = \decode.input_valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4930 ($sdff) from module core (D = $flatten\decode.$procmux$1521_Y, Q = \decode.input_valid).
Adding EN signal on $flatten\decode.$procdff$4526 ($dff) from module core (D = \decode.c_mem_long, Q = \decode.oc_mem_long).
Adding EN signal on $flatten\decode.$procdff$4525 ($dff) from module core (D = \decode.c_mem_width, Q = \decode.oc_mem_width).
Adding EN signal on $flatten\decode.$procdff$4524 ($dff) from module core (D = \decode.c_sys, Q = \decode.oc_sys).
Adding EN signal on $flatten\decode.$procdff$4523 ($dff) from module core (D = \decode.c_sreg_irt, Q = \decode.oc_sreg_irt).
Adding EN signal on $flatten\decode.$procdff$4522 ($dff) from module core (D = \decode.c_sreg_jal_over, Q = \decode.oc_sreg_jal_over).
Adding EN signal on $flatten\decode.$procdff$4521 ($dff) from module core (D = \decode.c_sreg_store, Q = \decode.oc_sreg_store).
Adding EN signal on $flatten\decode.$procdff$4520 ($dff) from module core (D = \decode.c_sreg_load, Q = \decode.oc_sreg_load).
Adding EN signal on $flatten\decode.$procdff$4519 ($dff) from module core (D = \decode.c_used_operands, Q = \decode.oc_used_operands).
Adding EN signal on $flatten\decode.$procdff$4518 ($dff) from module core (D = \decode.c_mem_we, Q = \decode.oc_mem_we).
Adding EN signal on $flatten\decode.$procdff$4517 ($dff) from module core (D = \decode.c_mem_access, Q = \decode.oc_mem_access).
Adding EN signal on $flatten\decode.$procdff$4516 ($dff) from module core (D = \fetch.o_jmp_predict, Q = \decode.o_jmp_pred_pass).
Adding EN signal on $flatten\decode.$procdff$4515 ($dff) from module core (D = \decode.c_jump_cond_code, Q = \decode.oc_jump_cond_code).
Adding EN signal on $flatten\decode.$procdff$4514 ($dff) from module core (D = \decode.c_rf_ie, Q = \decode.oc_rf_ie).
Adding SRST signal on $auto$ff.cc:266:slice$4996 ($dffe) from module core (D = $flatten\decode.$or$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$359_Y, Q = \decode.oc_rf_ie, rval = 8'00000000).
Adding EN signal on $flatten\decode.$procdff$4513 ($dff) from module core (D = \decode.c_r_reg_sel, Q = \decode.oc_r_reg_sel).
Adding EN signal on $flatten\decode.$procdff$4512 ($dff) from module core (D = \decode.c_l_reg_sel, Q = \decode.oc_l_reg_sel).
Adding EN signal on $flatten\decode.$procdff$4511 ($dff) from module core (D = \decode.c_alu_carry_en, Q = \decode.oc_alu_carry_en).
Adding EN signal on $flatten\decode.$procdff$4510 ($dff) from module core (D = \decode.c_alu_flags_ie, Q = \decode.oc_alu_flags_ie).
Adding EN signal on $flatten\decode.$procdff$4508 ($dff) from module core (D = \decode.c_r_bus_imm, Q = \decode.oc_r_bus_imm).
Adding EN signal on $flatten\decode.$procdff$4507 ($dff) from module core (D = 1'0, Q = \decode.oc_pc_ie).
Adding EN signal on $flatten\decode.$procdff$4506 ($dff) from module core (D = \decode.c_pc_inc, Q = \decode.oc_pc_inc).
Adding EN signal on $flatten\decode.$procdff$4505 ($dff) from module core (D = \fetch.o_instr [31:16], Q = \decode.o_imm_pass).
Adding SRST signal on $flatten\decode.$procdff$4504 ($dff) from module core (D = $flatten\decode.$procmux$1512_Y, Q = \decode.o_submit, rval = 1'0).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5027 ($dffe) from module core.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$4847 ($dffe) from module core.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$4842 ($dffe) from module core.

14.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [15] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [14] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [13] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [12] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [11] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [10] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [9] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [8] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [7] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [6] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [5] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [4] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [3] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [2] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_cur [1] between cell $auto$ff.cc:266:slice$4867.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [15] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [14] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [13] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [12] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [11] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [10] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [9] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [8] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [7] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [6] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [5] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [4] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [3] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [2] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [1] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Warning: Driver-driver conflict for \execute.alu_mul_div.div_res [0] between cell $auto$ff.cc:266:slice$4872.Q and constant 1'0 in core: Resolved using constant.
Removed 154 unused cells and 193 unused wires.
<suppressed ~156 debug messages>

14.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~9 debug messages>

14.9.9. Rerunning OPT passes. (Maybe there is more to do..)

14.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~66 debug messages>

14.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

14.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
<suppressed ~192 debug messages>
Removed a total of 64 cells.

14.9.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$ff.cc:266:slice$4867 ($dffe) from module core (D = $flatten\execute.\alu_mul_div.$procmux$4425_Y [15:2], Q = 14'00000000000000).

14.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 3 unused cells and 67 unused wires.
<suppressed ~4 debug messages>

14.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.9.16. Rerunning OPT passes. (Maybe there is more to do..)

14.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~66 debug messages>

14.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

14.9.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.9.20. Executing OPT_DFF pass (perform DFF optimizations).

14.9.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.9.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.9.23. Finished OPT passes. (There is nothing left to do.)

14.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 3 bits (of 7) from port B of cell core.$flatten\fetch.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:121$848 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\fetch.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:107$845 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\fetch.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:100$839 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\fetch.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:100$837 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\fetch.$eq$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:100$836 ($eq).
Removed top 15 bits (of 16) from port B of cell core.$flatten\fetch.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:94$833 ($add).
Removed top 9 bits (of 15) from port B of cell core.$auto$fsm_map.cc:77:implement_pattern_cache$4610 ($eq).
Removed top 4 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4107_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4078_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4045_CMP0 ($eq).
Removed top 6 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4021_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4020_CMP0 ($eq).
Removed top 4 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4019_CMP0 ($eq).
Removed top 4 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4018_CMP0 ($eq).
Removed top 4 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4017_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4016_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4015_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4014_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4013_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4012_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4011_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4009_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4008_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4007_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4006_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4005_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4004_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4003_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4002_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4001_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$4000_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3999_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3995_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3994_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3993_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3992_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3991_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3986_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3983_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3952_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3922_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3890_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3873_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3855_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3854_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3853_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3852_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3846_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3845_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3844_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell core.$flatten\decode.$procmux$3843_CMP0 ($eq).
Removed top 7 bits (of 8) from port A of cell core.$flatten\decode.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$574 ($and).
Removed top 28 bits (of 32) from port A of cell core.$flatten\decode.$neg$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$352 ($neg).
Converting cell core.$flatten\decode.$neg$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$352 ($neg) from signed to unsigned.
Removed top 1 bits (of 4) from port A of cell core.$flatten\decode.$neg$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$352 ($neg).
Removed top 15 bits (of 16) from mux cell core.$flatten\execute.\pc.$procmux$1359 ($mux).
Removed top 3 bits (of 4) from mux cell core.$flatten\execute.\alu_mul_div.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:33$7 ($mux).
Removed top 15 bits (of 16) from port A of cell core.$flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:56$17 ($sub).
Removed top 15 bits (of 16) from port A of cell core.$flatten\execute.\alu_mul_div.$ge$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:60$30 ($ge).
Removed top 27 bits (of 32) from port A of cell core.$flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$35 ($sub).
Removed top 26 bits (of 32) from port Y of cell core.$flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$35 ($sub).
Removed top 30 bits (of 32) from port B of cell core.$flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:63$48 ($sub).
Removed top 14 bits (of 16) from mux cell core.$flatten\execute.\alu_mul_div.$procmux$4419 ($mux).
Removed top 14 bits (of 16) from mux cell core.$flatten\execute.\alu_mul_div.$procmux$4425 ($mux).
Removed top 16 bits (of 17) from port B of cell core.$flatten\execute.\alu.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:28$59 ($add).
Removed top 16 bits (of 17) from port B of cell core.$flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:30$61 ($sub).
Removed top 1 bits (of 17) from port A of cell core.$flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:38$65 ($shl).
Removed top 1 bits (of 17) from port B of cell core.$flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:38$65 ($shl).
Removed top 27 bits (of 32) from port A of cell core.$flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69 ($sub).
Removed top 15 bits (of 32) from port Y of cell core.$flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69 ($sub).
Removed top 2 bits (of 3) from port B of cell core.$flatten\execute.\rf.$or$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v:31$1132 ($or).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1369_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1370_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1371_CMP0 ($eq).
Removed top 8 bits (of 16) from mux cell core.$flatten\execute.\rf.$procmux$1373 ($pmux).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1378_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1379_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1380_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1387_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1388_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1389_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1396_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1397_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell core.$flatten\execute.\rf.$procmux$1398_CMP0 ($eq).
Removed top 15 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1191_CMP0 ($eq).
Removed top 14 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1190_CMP0 ($eq).
Removed top 14 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1189_CMP0 ($eq).
Removed top 13 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1188_CMP0 ($eq).
Removed top 13 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1187_CMP0 ($eq).
Removed top 13 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1186_CMP0 ($eq).
Removed top 13 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1185_CMP0 ($eq).
Removed top 12 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1184_CMP0 ($eq).
Removed top 12 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1183_CMP0 ($eq).
Removed top 12 bits (of 16) from port B of cell core.$flatten\execute.$procmux$1182_CMP0 ($eq).
Removed top 7 bits (of 8) from port B of cell core.$flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:479$1078 ($add).
Removed top 7 bits (of 8) from port B of cell core.$flatten\execute.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:478$1077 ($sub).
Removed top 6 bits (of 7) from port B of cell core.$flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:443$1062 ($add).
Removed top 24 bits (of 32) from mux cell core.$flatten\execute.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:438$1055 ($mux).
Removed top 23 bits (of 32) from port B of cell core.$flatten\execute.$lt$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:421$1041 ($lt).
Removed top 7 bits (of 16) from port B of cell core.$flatten\execute.$ge$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:421$1040 ($ge).
Removed top 13 bits (of 16) from port B of cell core.$flatten\execute.$or$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:369$1018 ($or).
Removed top 15 bits (of 16) from mux cell core.$flatten\execute.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:251$1006 ($mux).
Removed top 15 bits (of 16) from port B of cell core.$flatten\execute.\pc.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:29$1088 ($add).
Removed top 31 bits (of 32) from port B of cell core.$flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:74$927 ($add).
Removed top 28 bits (of 32) from port Y of cell core.$flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:74$927 ($add).
Removed top 1 bits (of 2) from port A of cell core.$flatten\memwb.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:51$869 ($shl).
Removed top 1 bits (of 16) from port B of cell core.$flatten\memwb.$or$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:46$867 ($or).
Removed top 8 bits (of 16) from port B of cell core.$flatten\memwb.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:42$858 ($and).
Removed top 14 bits (of 16) from mux cell core.$flatten\execute.\alu_mul_div.$procmux$4423 ($mux).
Removed top 14 bits (of 16) from port Y of cell core.$flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:56$17 ($sub).
Removed top 14 bits (of 16) from port B of cell core.$flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:56$17 ($sub).
Removed top 28 bits (of 32) from wire core.$flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:74$927_Y.
Removed top 15 bits (of 16) from wire core.$flatten\execute.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:251$1006_Y.
Removed top 14 bits (of 16) from wire core.$flatten\execute.\alu_mul_div.$procmux$4419_Y.
Removed top 14 bits (of 16) from wire core.$flatten\execute.\alu_mul_div.$procmux$4423_Y.
Removed top 14 bits (of 16) from wire core.$flatten\execute.\alu_mul_div.$procmux$4425_Y.
Removed top 3 bits (of 4) from wire core.$flatten\execute.\alu_mul_div.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:33$7_Y.
Removed top 15 bits (of 16) from wire core.$flatten\execute.\pc.$procmux$1359_Y.

14.11. Executing PEEPOPT pass (run peephole optimizers).

14.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 0 unused cells and 8 unused wires.
<suppressed ~1 debug messages>

14.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module core:
  creating $macc model for $flatten\decode.$neg$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$352 ($neg).
  creating $macc model for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:251$1007 ($add).
  creating $macc model for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:443$1062 ($add).
  creating $macc model for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:479$1078 ($add).
  creating $macc model for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:74$927 ($add).
  creating $macc model for $flatten\execute.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:478$1077 ($sub).
  creating $macc model for $flatten\execute.\alu.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:28$58 ($add).
  creating $macc model for $flatten\execute.\alu.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:28$59 ($add).
  creating $macc model for $flatten\execute.\alu.$mul$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:42$67 ($mul).
  creating $macc model for $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:30$60 ($sub).
  creating $macc model for $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:30$61 ($sub).
  creating $macc model for $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69 ($sub).
  creating $macc model for $flatten\execute.\alu_mul_div.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:40$9 ($add).
  creating $macc model for $flatten\execute.\alu_mul_div.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:51$16 ($add).
  creating $macc model for $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:56$17 ($sub).
  creating $macc model for $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$35 ($sub).
  creating $macc model for $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:63$48 ($sub).
  creating $macc model for $flatten\execute.\pc.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:29$1088 ($add).
  creating $macc model for $flatten\fetch.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:94$833 ($add).
  merging $macc model for $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:30$60 into $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:30$61.
  merging $macc model for $flatten\execute.\alu.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:28$58 into $flatten\execute.\alu.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:28$59.
  creating $alu model for $macc $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:63$48.
  creating $alu model for $macc $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$35.
  creating $alu model for $macc $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:56$17.
  creating $alu model for $macc $flatten\execute.\alu_mul_div.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:51$16.
  creating $alu model for $macc $flatten\execute.\alu_mul_div.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:40$9.
  creating $alu model for $macc $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69.
  creating $alu model for $macc $flatten\execute.\pc.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:29$1088.
  creating $alu model for $macc $flatten\execute.\alu.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:28$59.
  creating $alu model for $macc $flatten\fetch.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:94$833.
  creating $alu model for $macc $flatten\execute.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:478$1077.
  creating $alu model for $macc $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:74$927.
  creating $alu model for $macc $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:479$1078.
  creating $alu model for $macc $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:443$1062.
  creating $alu model for $macc $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:251$1007.
  creating $alu model for $macc $flatten\decode.$neg$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$352.
  creating $macc cell for $flatten\execute.\alu.$mul$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:42$67: $auto$alumacc.cc:365:replace_macc$5059
  creating $macc cell for $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:30$61: $auto$alumacc.cc:365:replace_macc$5060
  creating $alu model for $flatten\execute.$ge$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:421$1040 ($ge): new $alu
  creating $alu model for $flatten\execute.$lt$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:421$1041 ($lt): new $alu
  creating $alu model for $flatten\execute.\alu_mul_div.$ge$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:60$30 ($ge): new $alu
  creating $alu model for $flatten\fetch.$gt$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:113$847 ($gt): new $alu
  creating $alu cell for $flatten\fetch.$gt$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:113$847: $auto$alumacc.cc:485:replace_alu$5065
  creating $alu cell for $flatten\execute.\alu_mul_div.$ge$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:60$30: $auto$alumacc.cc:485:replace_alu$5076
  creating $alu cell for $flatten\execute.$lt$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:421$1041: $auto$alumacc.cc:485:replace_alu$5089
  creating $alu cell for $flatten\execute.$ge$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:421$1040: $auto$alumacc.cc:485:replace_alu$5100
  creating $alu cell for $flatten\decode.$neg$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$352: $auto$alumacc.cc:485:replace_alu$5109
  creating $alu cell for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:251$1007: $auto$alumacc.cc:485:replace_alu$5112
  creating $alu cell for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:443$1062: $auto$alumacc.cc:485:replace_alu$5115
  creating $alu cell for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:479$1078: $auto$alumacc.cc:485:replace_alu$5118
  creating $alu cell for $flatten\execute.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:74$927: $auto$alumacc.cc:485:replace_alu$5121
  creating $alu cell for $flatten\execute.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:478$1077: $auto$alumacc.cc:485:replace_alu$5124
  creating $alu cell for $flatten\fetch.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v:94$833: $auto$alumacc.cc:485:replace_alu$5127
  creating $alu cell for $flatten\execute.\alu.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:28$59: $auto$alumacc.cc:485:replace_alu$5130
  creating $alu cell for $flatten\execute.\pc.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v:29$1088: $auto$alumacc.cc:485:replace_alu$5133
  creating $alu cell for $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69: $auto$alumacc.cc:485:replace_alu$5136
  creating $alu cell for $flatten\execute.\alu_mul_div.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:40$9: $auto$alumacc.cc:485:replace_alu$5139
  creating $alu cell for $flatten\execute.\alu_mul_div.$add$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:51$16: $auto$alumacc.cc:485:replace_alu$5142
  creating $alu cell for $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:56$17: $auto$alumacc.cc:485:replace_alu$5145
  creating $alu cell for $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:61$35: $auto$alumacc.cc:485:replace_alu$5148
  creating $alu cell for $flatten\execute.\alu_mul_div.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v:63$48: $auto$alumacc.cc:485:replace_alu$5151
  created 19 $alu and 2 $macc cells.

14.14. Executing SHARE pass (SAT-based resource sharing).
Found 3 cells in module core that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\execute.\alu.$shr$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:40$66 ($shr):
    Found 2 activation_patterns using ctrl signal { \decode.oc_alu_mode [12] \decode.oc_alu_mode [1] }.
    No candidates found.
  Analyzing resource sharing options for $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$70 ($shl):
    Found 1 activation_patterns using ctrl signal \decode.oc_alu_mode [12].
    Found 1 candidates: $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:38$65
    Analyzing resource sharing with $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:38$65 ($shl):
      Found 1 activation_patterns using ctrl signal \decode.oc_alu_mode [13].
      Forbidden control signals for this pair of cells: { $flatten\execute.$and$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v:478$1076_Y \execute.alu.outc [16] }
      Activation pattern for cell $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$70: \decode.oc_alu_mode [12] = 1'1
      Activation pattern for cell $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:38$65: \decode.oc_alu_mode [13] = 1'1
      Size of SAT problem: 0 cells, 21 variables, 201 clauses
      According to the SAT solver this pair of cells can be shared.
      Activation signal for $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$70: $auto$share.cc:977:make_cell_activation_logic$5154
      New cell: $auto$share.cc:667:make_supercell$5161 ($shl)
  Analyzing resource sharing options for $auto$share.cc:667:make_supercell$5161 ($shl):
    Found 2 activation_patterns using ctrl signal \decode.oc_alu_mode [13:12].
    No candidates found.
Removing 2 cells in module core:
  Removing cell $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:38$65 ($shl).
  Removing cell $flatten\execute.\alu.$shl$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$70 ($shl).

14.15. Executing OPT pass (performing simple optimizations).

14.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~2 debug messages>

14.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~68 debug messages>

14.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

14.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.15.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$4859 ($dffe) from module core (D = $flatten\execute.\alu_mul_div.$procmux$4459_Y [3:1], Q = \execute.alu_mul_div.cbit [3:1], rval = 3'000).

14.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 3 unused cells and 10 unused wires.
<suppressed ~6 debug messages>

14.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.15.9. Rerunning OPT passes. (Maybe there is more to do..)

14.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~69 debug messages>

14.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

14.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.15.13. Executing OPT_DFF pass (perform DFF optimizations).

14.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.15.16. Finished OPT passes. (There is nothing left to do.)

14.16. Executing MEMORY pass.

14.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

14.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

14.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

14.16.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

14.16.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

14.16.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.16.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

14.16.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

14.16.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.16.10. Executing MEMORY_COLLECT pass (generating $mem cells).

14.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.18. Executing OPT pass (performing simple optimizations).

14.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~110 debug messages>

14.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.18.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$ff.cc:266:slice$4803 ($sdffe) from module core (D = { \execute.sreg_priv_control.i_d [15:3] \execute.sreg_priv_control.i_d [1:0] }, Q = { \execute.sreg_priv_control.o_d [15:3] \execute.sreg_priv_control.o_d [1:0] }).

14.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 5 unused cells and 54 unused wires.
<suppressed ~7 debug messages>

14.18.5. Rerunning OPT passes. (Removed registers in this run.)

14.18.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~2 debug messages>

14.18.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

14.18.8. Executing OPT_DFF pass (perform DFF optimizations).

14.18.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

14.18.10. Finished fast OPT passes.

14.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

14.20. Executing OPT pass (performing simple optimizations).

14.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/8 on $pmux $flatten\execute.\rf.$procmux$1373.
    dead port 4/8 on $pmux $flatten\execute.\rf.$procmux$1373.
    dead port 6/8 on $pmux $flatten\execute.\rf.$procmux$1373.
Removed 3 multiplexer ports.
<suppressed ~37 debug messages>

14.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
    Consolidated identical input bits for $mux cell $auto$share.cc:660:make_supercell$5158:
      Old ports: A=\execute.alu.i_l, B={ \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] }, Y=$auto$share.cc:657:make_supercell$5156
      New ports: A=\execute.alu.i_l [14:0], B={ \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] \execute.alu.i_l [15] }, Y=$auto$share.cc:657:make_supercell$5156 [14:0]
      New connections: $auto$share.cc:657:make_supercell$5156 [15] = \execute.alu.i_l [15]
    Consolidated identical input bits for $mux cell $auto$share.cc:661:make_supercell$5159:
      Old ports: A={ 16'0000000000000000 \execute.alu.i_r }, B={ $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [15:0] }, Y=$auto$share.cc:658:make_supercell$5157
      New ports: A={ 1'0 \execute.alu.i_r }, B={ $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [31] $flatten\execute.\alu.$sub$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v:46$69_Y [15:0] }, Y=$auto$share.cc:658:make_supercell$5157 [16:0]
      New connections: $auto$share.cc:658:make_supercell$5157 [31:17] = { $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] $auto$share.cc:658:make_supercell$5157 [16] }
    Consolidated identical input bits for $mux cell $flatten\memwb.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:42$859:
      Old ports: A={ 8'00000000 \i_mem_data [7:0] }, B={ 8'00000000 \i_mem_data [15:8] }, Y=$flatten\memwb.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:42$859_Y
      New ports: A=\i_mem_data [7:0], B=\i_mem_data [15:8], Y=$flatten\memwb.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:42$859_Y [7:0]
      New connections: $flatten\memwb.$ternary$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v:42$859_Y [15:8] = 8'00000000
  Optimizing cells in module \core.
Performed a total of 3 changes.

14.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.20.6. Executing OPT_SHARE pass.

14.20.7. Executing OPT_DFF pass (perform DFF optimizations).

14.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.20.10. Rerunning OPT passes. (Maybe there is more to do..)

14.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~37 debug messages>

14.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

14.20.13. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

14.20.14. Executing OPT_SHARE pass.

14.20.15. Executing OPT_DFF pass (perform DFF optimizations).

14.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

14.20.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

14.20.18. Finished OPT passes. (There is nothing left to do.)

14.21. Executing TECHMAP pass (map to technology primitives).

14.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

14.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$504d7726e493b7d5a8a8ac16f387eb0143f8a853\_90_pmux for cells of type $pmux.
Using template $paramod$081ba1a4a7201ecdb44563d3c3bd7013d1ebf4eb\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$constmap:0092cbbf2312d28bbd19d8624c2b386ff8fb0a39$paramod$1bcfc907724c63c8d49cac4a746a6303c20c2a13\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux.
Using template $paramod$70d30c21ff772b34d0d1da2801fbd781dc3c70e4\_90_pmux for cells of type $pmux.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$117a422dd91271f31dcbd629d7b52dc0eb1e49ab\_90_alu for cells of type $alu.
Using template $paramod$constmap:53f81d327ce76cbf6a8a98434119a90a4847620f$paramod$21dee603dc19e4530a14795556c80eafcc4f26b8\_90_shift_shiftx for cells of type $shift.
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc.
  add \execute.alu.i_l * \execute.alu.i_r (16x16 bits, unsigned)
Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_90_alu for cells of type $alu.
Using template $paramod$constmap:00a5b8c078faac2d9dcf7d1311e85cfd31359fcf$paramod$b1f8e9a58fee383a65180922397f7058048191fe\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$constmap:446553370afc6c2aa6cc0b8f657b7f64b237ff7c$paramod$962bb79c2a50a422516483c1c9c06046761917ac\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$9dd2c168c92ea5e7211728a4dd85e9d07319b5c9\_90_alu for cells of type $alu.
Using template $paramod$7a879e600cfb66edc319701e3d60cd93f323b9dc\_90_alu for cells of type $alu.
Using template $paramod$constmap:b23e69f9359ccab1581cffa68b8a9cdf073114c2$paramod$781451a06cb6b76ec9b48f10e71685a77ec5f36c\_90_shift_shiftx for cells of type $shiftx.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$constmap:d38d98c7f121c352e37113a9a1041f7c16bf352c$paramod$02dbae28c9ac2b40a59ca8e36294a63e0f81b019\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
  add \execute.alu.i_l (16 bits, unsigned)
  sub \execute.alu.i_carry (1 bits, unsigned)
  sub \execute.alu.i_r (16 bits, unsigned)
  packed 2 (1) bits / 1 words into adder tree
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_xor.
Using template $paramod$17a66edbde2bdde182c5f9e669e6d9c10a11f346\_90_pmux for cells of type $pmux.
Using template $paramod$ee721315a7b0169d82611b9aea01747035b97792\_90_pmux for cells of type $pmux.
Using template $paramod$f1a1302b8e09c99a2717f99de3f6cd758facf154\_90_pmux for cells of type $pmux.
Using template $paramod$08e410500e53e3f6955ef694e2ea15d9fc14e03c\_90_pmux for cells of type $pmux.
Using template $paramod$bfceb922395790c0ce92e9f9b5b428d4fc72cc30\_90_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_90_alu for cells of type $alu.
Using template $paramod$341aa3df018211312935dfad98c63330c1858baf\_90_alu for cells of type $alu.
Using template $paramod$constmap:eaa2ba5f0b70ada53775eacff15b2ac9c5d10fde$paramod$27b5e5b711f58371dce0b3a5224f46c13c76d8cc\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$403a3c2fa431a154c52a6a5429d7a6260b5d144f\_90_alu for cells of type $alu.
Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$constmap:a4d8bd4c83ae7aadb9a39a6a6c198c7f62a08526$paramod$640153b3f54eea4944e561520acd295aeb1e03d2\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011111 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000101 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010001 for cells of type $fa.
Using template $paramod$3bb72ad0665cdca279bbc49ed6a39f403f16497f\_90_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000010001 for cells of type $lcu.
No more expansions possible.
<suppressed ~5601 debug messages>

14.22. Executing OPT pass (performing simple optimizations).

14.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~3528 debug messages>

14.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
<suppressed ~2817 debug messages>
Removed a total of 939 cells.

14.22.3. Executing OPT_DFF pass (perform DFF optimizations).

14.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 650 unused cells and 2684 unused wires.
<suppressed ~651 debug messages>

14.22.5. Finished fast OPT passes.

14.23. Executing ABC pass (technology mapping using ABC).

14.23.1. Extracting gate netlist of module `\core' to `<abc-temp-dir>/input.blif'..
Extracted 4759 gates and 5271 wires to a netlist network with 509 inputs and 386 outputs.

14.23.1.1. Executing ABC.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

14.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:      158
ABC RESULTS:              XNOR cells:       72
ABC RESULTS:               XOR cells:      410
ABC RESULTS:               NOR cells:      190
ABC RESULTS:              NAND cells:      115
ABC RESULTS:             ORNOT cells:      183
ABC RESULTS:               NOT cells:      188
ABC RESULTS:               MUX cells:      636
ABC RESULTS:            ANDNOT cells:     1546
ABC RESULTS:                OR cells:     1072
ABC RESULTS:        internal signals:     4376
ABC RESULTS:           input signals:      509
ABC RESULTS:          output signals:      386
Removing temp directory.

14.24. Executing OPT pass (performing simple optimizations).

14.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.
<suppressed ~151 debug messages>

14.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

14.24.3. Executing OPT_DFF pass (perform DFF optimizations).

14.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 7 unused cells and 2210 unused wires.
<suppressed ~55 debug messages>

14.24.5. Finished fast OPT passes.

14.25. Executing HIERARCHY pass (managing design hierarchy).

14.25.1. Analyzing design hierarchy..
Top module:  \core

14.25.2. Analyzing design hierarchy..
Top module:  \core
Removed 0 unused modules.

14.26. Printing statistics.

=== core ===

   Number of wires:               4669
   Number of wire bits:           6759
   Number of public wires:         414
   Number of public wire bits:    2464
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               5061
     $_ANDNOT_                    1543
     $_AND_                        157
     $_DFFE_PP_                    196
     $_DFF_P_                       17
     $_MUX_                        636
     $_NAND_                       114
     $_NOR_                        190
     $_NOT_                        181
     $_ORNOT_                      183
     $_OR_                        1072
     $_SDFFCE_PN0P_                 24
     $_SDFFCE_PP0P_                  3
     $_SDFFE_PP0N_                   7
     $_SDFFE_PP0P_                 236
     $_SDFFE_PP1N_                   1
     $_SDFFE_PP1P_                   5
     $_SDFF_PP0_                    14
     $_XNOR_                        72
     $_XOR_                        410

14.27. Executing CHECK pass (checking for obvious problems).
Checking module core...
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [15]:
    port Q[0] of cell $auto$ff.cc:266:slice$8513 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8529 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [14]:
    port Q[0] of cell $auto$ff.cc:266:slice$8512 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8528 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [13]:
    port Q[0] of cell $auto$ff.cc:266:slice$8511 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8527 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [12]:
    port Q[0] of cell $auto$ff.cc:266:slice$8510 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8526 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [11]:
    port Q[0] of cell $auto$ff.cc:266:slice$8509 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8525 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [10]:
    port Q[0] of cell $auto$ff.cc:266:slice$8508 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8524 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [9]:
    port Q[0] of cell $auto$ff.cc:266:slice$8507 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8523 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [8]:
    port Q[0] of cell $auto$ff.cc:266:slice$8506 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8522 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [7]:
    port Q[0] of cell $auto$ff.cc:266:slice$8505 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8521 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [6]:
    port Q[0] of cell $auto$ff.cc:266:slice$8504 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8520 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [5]:
    port Q[0] of cell $auto$ff.cc:266:slice$8503 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8519 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [4]:
    port Q[0] of cell $auto$ff.cc:266:slice$8502 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8518 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [3]:
    port Q[0] of cell $auto$ff.cc:266:slice$8501 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8517 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [2]:
    port Q[0] of cell $auto$ff.cc:266:slice$8500 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8516 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [1]:
    port Q[0] of cell $auto$ff.cc:266:slice$8499 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8515 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.mul_res [0]:
    port Q[0] of cell $auto$ff.cc:266:slice$8498 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8514 ($_SDFFCE_PN0P_)
Warning: multiple conflicting drivers for core.\execute.alu_mul_div.div_cur [0]:
    port Q[0] of cell $auto$ff.cc:266:slice$5715 ($_DFFE_PP_)
    port Q[0] of cell $auto$ff.cc:266:slice$8531 ($_DFFE_PP_)
Found and reported 17 problems.

15. Generating Graphviz representation of design.
Writing dot description to `/home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/synthesis/post_techmap.dot'.
Dumping module core to page 1.
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.alu.i_l [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.alu.i_l [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.alu.i_l [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.alu.i_l [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.alu.i_l [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.alu.i_l [6] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.pc_high [0] 1
Warning: WIDTHLABEL \execute.pc_high [0] 1
Warning: WIDTHLABEL \execute.prev_pc_high [0] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high [1] 1
Warning: WIDTHLABEL \execute.pc_high [1] 1
Warning: WIDTHLABEL \execute.prev_pc_high [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high [2] 1
Warning: WIDTHLABEL \execute.pc_high [2] 1
Warning: WIDTHLABEL \execute.prev_pc_high [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high [3] 1
Warning: WIDTHLABEL \execute.pc_high [3] 1
Warning: WIDTHLABEL \execute.prev_pc_high [3] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high [4] 1
Warning: WIDTHLABEL \execute.pc_high [4] 1
Warning: WIDTHLABEL \execute.prev_pc_high [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high [5] 1
Warning: WIDTHLABEL \execute.pc_high [5] 1
Warning: WIDTHLABEL \execute.prev_pc_high [5] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high [6] 1
Warning: WIDTHLABEL \execute.pc_high [6] 1
Warning: WIDTHLABEL \execute.prev_pc_high [6] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high [7] 1
Warning: WIDTHLABEL \execute.pc_high [7] 1
Warning: WIDTHLABEL \execute.prev_pc_high [7] 1
Warning: WIDTHLABEL \execute.o_reg_ie [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [2] 1
Warning: WIDTHLABEL \execute.o_reg_ie [3] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \execute.o_reg_ie [4] 1
Warning: WIDTHLABEL \execute.o_reg_ie [5] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [6] 1
Warning: WIDTHLABEL \execute.o_reg_ie [7] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_used_operands [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [2] 1
Warning: WIDTHLABEL \execute.o_reg_ie [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [1] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [2] 1
Warning: WIDTHLABEL \execute.o_reg_ie [3] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [1] 1
Warning: WIDTHLABEL \execute.o_reg_ie [4] 1
Warning: WIDTHLABEL \execute.o_reg_ie [5] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [6] 1
Warning: WIDTHLABEL \execute.o_reg_ie [7] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_used_operands [1] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [3] 1
Warning: WIDTHLABEL \decode.oc_used_operands [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [1] 1
Warning: WIDTHLABEL \execute.o_reg_ie [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [3] 1
Warning: WIDTHLABEL \execute.o_reg_ie [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \execute.o_reg_ie [5] 1
Warning: WIDTHLABEL \execute.o_reg_ie [4] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [7] 1
Warning: WIDTHLABEL \execute.o_reg_ie [6] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \dbg_in [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [10] 1
Warning: WIDTHLABEL \i_req_data [1] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [1] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [1] 1
Warning: WIDTHLABEL \i_req_data [4] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [4] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [4] 1
Warning: WIDTHLABEL \i_req_data [3] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [3] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [3] 1
Warning: WIDTHLABEL \i_req_data [2] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [2] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [2] 1
Warning: WIDTHLABEL \i_req_data [0] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [0] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [0] 1
Warning: WIDTHLABEL \fetch.o_instr [0] 1
Warning: WIDTHLABEL \fetch.o_instr [1] 1
Warning: WIDTHLABEL \fetch.o_instr [3] 1
Warning: WIDTHLABEL \fetch.o_instr [2] 1
Warning: WIDTHLABEL \fetch.o_instr [6] 1
Warning: WIDTHLABEL \fetch.o_instr [5] 1
Warning: WIDTHLABEL \fetch.o_instr [4] 1
Warning: WIDTHLABEL \decode.o_imm_pass [1] 1
Warning: WIDTHLABEL \decode.o_imm_pass [0] 1
Warning: WIDTHLABEL \decode.o_imm_pass [2] 1
Warning: WIDTHLABEL \decode.o_imm_pass [3] 1
Warning: WIDTHLABEL \decode.o_imm_pass [5] 1
Warning: WIDTHLABEL \decode.o_imm_pass [4] 1
Warning: WIDTHLABEL \decode.o_imm_pass [7] 1
Warning: WIDTHLABEL \decode.o_imm_pass [6] 1
Warning: WIDTHLABEL \decode.o_imm_pass [9] 1
Warning: WIDTHLABEL \decode.o_imm_pass [8] 1
Warning: WIDTHLABEL \decode.o_imm_pass [11] 1
Warning: WIDTHLABEL \decode.o_imm_pass [10] 1
Warning: WIDTHLABEL \decode.o_imm_pass [13] 1
Warning: WIDTHLABEL \decode.o_imm_pass [12] 1
Warning: WIDTHLABEL \decode.o_imm_pass [15] 1
Warning: WIDTHLABEL \decode.o_imm_pass [14] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [0] 1
Warning: WIDTHLABEL \fetch.o_instr [0] 1
Warning: WIDTHLABEL \fetch.o_instr [1] 1
Warning: WIDTHLABEL \fetch.o_instr [2] 1
Warning: WIDTHLABEL \fetch.o_instr [3] 1
Warning: WIDTHLABEL \fetch.o_instr [4] 1
Warning: WIDTHLABEL \fetch.o_instr [5] 1
Warning: WIDTHLABEL \fetch.o_instr [1] 1
Warning: WIDTHLABEL \fetch.o_instr [0] 1
Warning: WIDTHLABEL \fetch.o_instr [0] 1
Warning: WIDTHLABEL \fetch.o_instr [1] 1
Warning: WIDTHLABEL \fetch.o_instr [3] 1
Warning: WIDTHLABEL \fetch.o_instr [2] 1
Warning: WIDTHLABEL \fetch.o_instr [3] 1
Warning: WIDTHLABEL \fetch.o_instr [2] 1
Warning: WIDTHLABEL \fetch.o_instr [5] 1
Warning: WIDTHLABEL \fetch.o_instr [4] 1
Warning: WIDTHLABEL \fetch.o_instr [6] 1
Warning: WIDTHLABEL \i_req_data [5] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [5] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [5] 1
Warning: WIDTHLABEL \i_req_data [6] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [6] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [6] 1
Warning: WIDTHLABEL \i_req_data [16] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [16] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [16] 1
Warning: WIDTHLABEL \i_req_data [17] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [17] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [17] 1
Warning: WIDTHLABEL \i_req_data [18] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [18] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [18] 1
Warning: WIDTHLABEL \i_req_data [19] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [19] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [19] 1
Warning: WIDTHLABEL \i_req_data [20] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [20] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [20] 1
Warning: WIDTHLABEL \i_req_data [21] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [21] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [21] 1
Warning: WIDTHLABEL \i_req_data [22] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [22] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [22] 1
Warning: WIDTHLABEL \i_req_data [23] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [23] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [23] 1
Warning: WIDTHLABEL \i_req_data [24] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [24] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [24] 1
Warning: WIDTHLABEL \i_req_data [25] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [25] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [25] 1
Warning: WIDTHLABEL \i_req_data [26] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [26] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [26] 1
Warning: WIDTHLABEL \i_req_data [27] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [27] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [27] 1
Warning: WIDTHLABEL \i_req_data [28] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [28] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [28] 1
Warning: WIDTHLABEL \i_req_data [29] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [29] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [29] 1
Warning: WIDTHLABEL \i_req_data [30] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [30] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [30] 1
Warning: WIDTHLABEL \i_req_data [31] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [31] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [31] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.reg_r_con [15] 1
Warning: WIDTHLABEL \execute.reg_r_con [15] 1
Warning: WIDTHLABEL \decode.o_imm_pass [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.reg_r_con [14] 1
Warning: WIDTHLABEL \execute.reg_r_con [14] 1
Warning: WIDTHLABEL \decode.o_imm_pass [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.reg_r_con [13] 1
Warning: WIDTHLABEL \execute.reg_r_con [13] 1
Warning: WIDTHLABEL \decode.o_imm_pass [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.reg_r_con [12] 1
Warning: WIDTHLABEL \execute.reg_r_con [12] 1
Warning: WIDTHLABEL \decode.o_imm_pass [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.reg_r_con [11] 1
Warning: WIDTHLABEL \execute.reg_r_con [11] 1
Warning: WIDTHLABEL \decode.o_imm_pass [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.reg_r_con [10] 1
Warning: WIDTHLABEL \execute.reg_r_con [10] 1
Warning: WIDTHLABEL \decode.o_imm_pass [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.reg_r_con [9] 1
Warning: WIDTHLABEL \execute.reg_r_con [9] 1
Warning: WIDTHLABEL \decode.o_imm_pass [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.reg_r_con [8] 1
Warning: WIDTHLABEL \execute.reg_r_con [8] 1
Warning: WIDTHLABEL \decode.o_imm_pass [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \decode.o_imm_pass [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \decode.o_imm_pass [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \decode.o_imm_pass [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \decode.o_imm_pass [4] 1
Warning: WIDTHLABEL \decode.o_imm_pass [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \decode.o_imm_pass [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \decode.o_imm_pass [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \decode.o_imm_pass [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.div_cur [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.div_cur [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [10] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [1] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [0] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [2] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [3] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [5] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [4] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [6] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [2] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [3] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [1] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [0] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [17] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [16] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [19] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [18] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [21] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [20] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [23] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [22] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [25] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [24] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [27] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [26] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [29] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [28] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [31] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [30] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [10] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [10] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [2] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [3] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [2] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [3] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [4] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [3] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [3] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [2] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [2] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [3] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [2] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \decode.o_imm_pass [1] 1
Warning: WIDTHLABEL \decode.o_imm_pass [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \i_req_data [7] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [7] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [7] 1
Warning: WIDTHLABEL \i_req_data [8] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [8] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [8] 1
Warning: WIDTHLABEL \i_req_data [9] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [9] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [9] 1
Warning: WIDTHLABEL \i_req_data [10] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [10] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \execute.alu.i_l [3] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \execute.alu.i_l [3] 1
Warning: WIDTHLABEL \execute.alu.i_l [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [7] 1
Warning: WIDTHLABEL \decode.o_imm_pass [2] 1
Warning: WIDTHLABEL \decode.o_imm_pass [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.pc_high [0] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.pc_high [1] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.pc_high [2] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [3] 1
Warning: WIDTHLABEL \execute.pc_high [3] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \execute.pc_high [4] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \execute.pc_high [5] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \execute.pc_high [6] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \execute.pc_high [7] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [3] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.o_d [0] 1
Warning: WIDTHLABEL \execute.jtr_in [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr.i_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr.i_d [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.i_d [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.i_d [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.i_d [2] 1
Warning: WIDTHLABEL \execute.pc.o_pc [0] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [0] 1
Warning: WIDTHLABEL \decode.o_imm_pass [1] 1
Warning: WIDTHLABEL \decode.o_imm_pass [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [0] 1
Warning: WIDTHLABEL \execute.pc.o_pc [1] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [1] 1
Warning: WIDTHLABEL \execute.pc.o_pc [2] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [2] 1
Warning: WIDTHLABEL \execute.pc.o_pc [3] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [3] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [3] 1
Warning: WIDTHLABEL \execute.pc.o_pc [4] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [4] 1
Warning: WIDTHLABEL \execute.pc.o_pc [5] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [5] 1
Warning: WIDTHLABEL \execute.pc.o_pc [6] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [6] 1
Warning: WIDTHLABEL \execute.pc.o_pc [7] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [7] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [7] 1
Warning: WIDTHLABEL \execute.pc.o_pc [8] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [8] 1
Warning: WIDTHLABEL \execute.reg_r_con [8] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [8] 1
Warning: WIDTHLABEL \execute.pc.o_pc [9] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [9] 1
Warning: WIDTHLABEL \execute.reg_r_con [9] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [9] 1
Warning: WIDTHLABEL \execute.pc.o_pc [10] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [10] 1
Warning: WIDTHLABEL \execute.reg_r_con [10] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [10] 1
Warning: WIDTHLABEL \execute.pc.o_pc [11] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [11] 1
Warning: WIDTHLABEL \execute.reg_r_con [11] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [11] 1
Warning: WIDTHLABEL \execute.pc.o_pc [12] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [12] 1
Warning: WIDTHLABEL \execute.reg_r_con [12] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [12] 1
Warning: WIDTHLABEL \execute.pc.o_pc [13] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [13] 1
Warning: WIDTHLABEL \execute.reg_r_con [13] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [13] 1
Warning: WIDTHLABEL \execute.pc.o_pc [14] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [14] 1
Warning: WIDTHLABEL \execute.reg_r_con [14] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [14] 1
Warning: WIDTHLABEL \execute.pc.o_pc [15] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [15] 1
Warning: WIDTHLABEL \execute.reg_r_con [15] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [15] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [2] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [7] 1
Warning: WIDTHLABEL \execute.reg_r_con [8] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [8] 1
Warning: WIDTHLABEL \execute.reg_r_con [9] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [9] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [10] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [11] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [12] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [13] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [14] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [15] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [7] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.div_cur [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [10] 1
Warning: WIDTHLABEL \execute.alu_bus [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [0] 1
Warning: WIDTHLABEL \execute.pc.o_pc [0] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [0] 1
Warning: WIDTHLABEL \decode.o_imm_pass [2] 1
Warning: WIDTHLABEL \decode.o_imm_pass [3] 1
Warning: WIDTHLABEL \i_core_int_sreg [0] 1
Warning: WIDTHLABEL \decode.o_imm_pass [0] 1
Warning: WIDTHLABEL \decode.o_imm_pass [1] 1
Warning: WIDTHLABEL \decode.o_imm_pass [3] 1
Warning: WIDTHLABEL \decode.o_imm_pass [2] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [0] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [0] 1
Warning: WIDTHLABEL \execute.pc.o_pc [0] 1
Warning: WIDTHLABEL \execute.alu_bus [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [10] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [1] 1
Warning: WIDTHLABEL \execute.alu_bus [1] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [1] 1
Warning: WIDTHLABEL \i_core_int_sreg [1] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [1] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [1] 1
Warning: WIDTHLABEL \execute.pc.o_pc [1] 1
Warning: WIDTHLABEL \execute.pc.o_pc [1] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [1] 1
Warning: WIDTHLABEL \execute.alu_bus [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.alu.i_l [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [2] 1
Warning: WIDTHLABEL \execute.alu_bus [2] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [2] 1
Warning: WIDTHLABEL \i_core_int_sreg [2] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [2] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [2] 1
Warning: WIDTHLABEL \execute.pc.o_pc [2] 1
Warning: WIDTHLABEL \execute.pc.o_pc [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [2] 1
Warning: WIDTHLABEL \execute.alu_bus [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \execute.alu.i_l [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [7] 1
Warning: WIDTHLABEL \execute.alu.i_l [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [3] 1
Warning: WIDTHLABEL \execute.alu_bus [3] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [3] 1
Warning: WIDTHLABEL \i_core_int_sreg [3] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [3] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [3] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [3] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [3] 1
Warning: WIDTHLABEL \execute.pc.o_pc [3] 1
Warning: WIDTHLABEL \execute.pc.o_pc [3] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [3] 1
Warning: WIDTHLABEL \execute.alu_bus [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [3] 1
Warning: WIDTHLABEL \execute.alu.i_l [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_l [4] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [4] 1
Warning: WIDTHLABEL \execute.alu_bus [4] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [4] 1
Warning: WIDTHLABEL \i_core_int_sreg [4] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [4] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [4] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [4] 1
Warning: WIDTHLABEL \execute.pc.o_pc [4] 1
Warning: WIDTHLABEL \execute.pc.o_pc [4] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [4] 1
Warning: WIDTHLABEL \execute.alu_bus [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [5] 1
Warning: WIDTHLABEL \execute.alu.i_l [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [5] 1
Warning: WIDTHLABEL \execute.alu_bus [5] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [5] 1
Warning: WIDTHLABEL \i_core_int_sreg [5] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [5] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [5] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [5] 1
Warning: WIDTHLABEL \execute.pc.o_pc [5] 1
Warning: WIDTHLABEL \execute.pc.o_pc [5] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [5] 1
Warning: WIDTHLABEL \execute.alu_bus [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [6] 1
Warning: WIDTHLABEL \execute.alu_bus [6] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [6] 1
Warning: WIDTHLABEL \i_core_int_sreg [6] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [6] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [6] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [6] 1
Warning: WIDTHLABEL \execute.pc.o_pc [6] 1
Warning: WIDTHLABEL \execute.pc.o_pc [6] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [6] 1
Warning: WIDTHLABEL \execute.alu_bus [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \execute.alu.i_l [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_l [7] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [7] 1
Warning: WIDTHLABEL \execute.alu_bus [7] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [7] 1
Warning: WIDTHLABEL \i_core_int_sreg [7] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [7] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [7] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [7] 1
Warning: WIDTHLABEL \execute.pc.o_pc [7] 1
Warning: WIDTHLABEL \execute.pc.o_pc [7] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [7] 1
Warning: WIDTHLABEL \execute.alu_bus [7] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \execute.alu.i_l [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_l [8] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [8] 1
Warning: WIDTHLABEL \execute.alu_bus [8] 1
Warning: WIDTHLABEL \i_core_int_sreg [8] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [8] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [8] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [8] 1
Warning: WIDTHLABEL \execute.pc.o_pc [8] 1
Warning: WIDTHLABEL \execute.pc.o_pc [8] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [8] 1
Warning: WIDTHLABEL \execute.alu_bus [8] 1
Warning: WIDTHLABEL \execute.reg_r_con [8] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [9] 1
Warning: WIDTHLABEL \execute.alu.i_l [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [9] 1
Warning: WIDTHLABEL \execute.alu_bus [9] 1
Warning: WIDTHLABEL \i_core_int_sreg [9] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [9] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [9] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [9] 1
Warning: WIDTHLABEL \execute.pc.o_pc [9] 1
Warning: WIDTHLABEL \execute.pc.o_pc [9] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [9] 1
Warning: WIDTHLABEL \execute.alu_bus [9] 1
Warning: WIDTHLABEL \execute.reg_r_con [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [10] 1
Warning: WIDTHLABEL \execute.alu.i_l [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [10] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [10] 1
Warning: WIDTHLABEL \execute.alu_bus [10] 1
Warning: WIDTHLABEL \i_core_int_sreg [10] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [10] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [10] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [10] 1
Warning: WIDTHLABEL \execute.pc.o_pc [10] 1
Warning: WIDTHLABEL \execute.pc.o_pc [10] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [10] 1
Warning: WIDTHLABEL \execute.alu_bus [10] 1
Warning: WIDTHLABEL \execute.reg_r_con [10] 1
Warning: WIDTHLABEL \execute.alu.i_l [11] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_l [11] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [11] 1
Warning: WIDTHLABEL \execute.alu_bus [11] 1
Warning: WIDTHLABEL \i_core_int_sreg [11] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [11] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [11] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [11] 1
Warning: WIDTHLABEL \execute.pc.o_pc [11] 1
Warning: WIDTHLABEL \execute.pc.o_pc [11] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [11] 1
Warning: WIDTHLABEL \execute.alu_bus [11] 1
Warning: WIDTHLABEL \execute.reg_r_con [11] 1
Warning: WIDTHLABEL \execute.alu.i_l [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [12] 1
Warning: WIDTHLABEL \execute.alu_bus [12] 1
Warning: WIDTHLABEL \i_core_int_sreg [12] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [12] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [12] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [12] 1
Warning: WIDTHLABEL \execute.pc.o_pc [12] 1
Warning: WIDTHLABEL \execute.pc.o_pc [12] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [12] 1
Warning: WIDTHLABEL \execute.alu_bus [12] 1
Warning: WIDTHLABEL \execute.reg_r_con [12] 1
Warning: WIDTHLABEL \execute.alu.i_l [13] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [10] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [13] 1
Warning: WIDTHLABEL \execute.alu_bus [13] 1
Warning: WIDTHLABEL \i_core_int_sreg [13] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [13] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [13] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [13] 1
Warning: WIDTHLABEL \execute.pc.o_pc [13] 1
Warning: WIDTHLABEL \execute.pc.o_pc [13] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [13] 1
Warning: WIDTHLABEL \execute.alu_bus [13] 1
Warning: WIDTHLABEL \execute.reg_r_con [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \execute.alu.i_l [14] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [14] 1
Warning: WIDTHLABEL \execute.alu_bus [14] 1
Warning: WIDTHLABEL \i_core_int_sreg [14] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [14] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [14] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [14] 1
Warning: WIDTHLABEL \execute.pc.o_pc [14] 1
Warning: WIDTHLABEL \execute.pc.o_pc [14] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [14] 1
Warning: WIDTHLABEL \execute.alu_bus [14] 1
Warning: WIDTHLABEL \execute.reg_r_con [14] 1
Warning: WIDTHLABEL \execute.alu.i_l [15] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \execute.alu.i_l [15] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
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Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [15] 1
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Warning: WIDTHLABEL \i_core_int_sreg [15] 1
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Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [15] 1
Warning: WIDTHLABEL \execute.pc.o_pc [15] 1
Warning: WIDTHLABEL \execute.pc.o_pc [15] 1
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Warning: WIDTHLABEL \execute.reg_r_con [15] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \execute.reg_r_con [3] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.o_reg_ie [1] 1
Warning: WIDTHLABEL \execute.o_reg_ie [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [3] 1
Warning: WIDTHLABEL \execute.o_reg_ie [2] 1
Warning: WIDTHLABEL \execute.o_reg_ie [5] 1
Warning: WIDTHLABEL \execute.o_reg_ie [4] 1
Warning: WIDTHLABEL \execute.o_reg_ie [7] 1
Warning: WIDTHLABEL \execute.o_reg_ie [6] 1
Warning: WIDTHLABEL \execute.o_reg_ie [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [1] 1
Warning: WIDTHLABEL \execute.o_reg_ie [2] 1
Warning: WIDTHLABEL \execute.o_reg_ie [3] 1
Warning: WIDTHLABEL \execute.o_reg_ie [4] 1
Warning: WIDTHLABEL \execute.o_reg_ie [5] 1
Warning: WIDTHLABEL \execute.o_reg_ie [6] 1
Warning: WIDTHLABEL \execute.o_reg_ie [7] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
Warning: WIDTHLABEL \o_mem_sel [0] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
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Warning: WIDTHLABEL \execute.o_addr [0] 1
Warning: WIDTHLABEL \execute.o_data [0] 1
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Warning: WIDTHLABEL \execute.o_data [1] 1
Warning: WIDTHLABEL \o_mem_data [1] 1
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Warning: WIDTHLABEL \execute.o_data [3] 1
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Warning: WIDTHLABEL \execute.o_data [1] 1
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Warning: WIDTHLABEL \execute.o_data [10] 1
Warning: WIDTHLABEL \execute.o_data [2] 1
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Warning: WIDTHLABEL \execute.o_data [11] 1
Warning: WIDTHLABEL \execute.o_data [3] 1
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Warning: WIDTHLABEL \execute.o_data [12] 1
Warning: WIDTHLABEL \execute.o_data [4] 1
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Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
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Warning: WIDTHLABEL \i_mem_data [9] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
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Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
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Warning: WIDTHLABEL \i_mem_data [10] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
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Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
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Warning: WIDTHLABEL \i_mem_data [11] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
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Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
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Warning: WIDTHLABEL \i_mem_data [12] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
Warning: WIDTHLABEL \i_mem_data [4] 1
Warning: WIDTHLABEL \execute.o_data [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
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Warning: WIDTHLABEL \i_mem_data [13] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
Warning: WIDTHLABEL \i_mem_data [5] 1
Warning: WIDTHLABEL \execute.o_data [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \i_mem_data [6] 1
Warning: WIDTHLABEL \i_mem_data [14] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
Warning: WIDTHLABEL \i_mem_data [6] 1
Warning: WIDTHLABEL \execute.o_data [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \i_mem_data [7] 1
Warning: WIDTHLABEL \i_mem_data [15] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
Warning: WIDTHLABEL \i_mem_data [7] 1
Warning: WIDTHLABEL \execute.o_data [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \i_mem_data [8] 1
Warning: WIDTHLABEL \execute.o_data [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \i_mem_data [9] 1
Warning: WIDTHLABEL \execute.o_data [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
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Warning: WIDTHLABEL \execute.o_data [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \i_mem_data [11] 1
Warning: WIDTHLABEL \execute.o_data [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \i_mem_data [12] 1
Warning: WIDTHLABEL \execute.o_data [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \i_mem_data [13] 1
Warning: WIDTHLABEL \execute.o_data [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \i_mem_data [14] 1
Warning: WIDTHLABEL \execute.o_data [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \i_mem_data [15] 1
Warning: WIDTHLABEL \execute.o_data [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \dbg_in [2] 1
Warning: WIDTHLABEL \dbg_in [1] 1
Warning: WIDTHLABEL \dbg_in [0] 1
Warning: WIDTHLABEL \dbg_in [0] 1
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Warning: WIDTHLABEL \dbg_in [1] 1
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Warning: WIDTHLABEL \dbg_in [2] 1
Warning: WIDTHLABEL \dbg_in [2] 1
Warning: WIDTHLABEL \dbg_in [2] 1
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Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [1] 1
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Warning: WIDTHLABEL \dbg_out [1] 1
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Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [3] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [14] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [13] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [14] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [3] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [15] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [14] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [15] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.X [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5139.Y [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5139.Y [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [0] 1
Warning: WIDTHLABEL \execute.alu_bus [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [0] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [1] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [3] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [3] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [4] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [4] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [5] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [5] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [6] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [6] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [7] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [7] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [8] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [8] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [9] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [9] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [10] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [10] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [11] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [11] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [12] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [12] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [13] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [13] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [14] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [14] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [15] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [15] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [0] 1
Warning: WIDTHLABEL \fetch.o_instr [0] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [1] 1
Warning: WIDTHLABEL \fetch.o_instr [1] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [2] 1
Warning: WIDTHLABEL \fetch.o_instr [2] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [3] 1
Warning: WIDTHLABEL \fetch.o_instr [3] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [4] 1
Warning: WIDTHLABEL \fetch.o_instr [4] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [5] 1
Warning: WIDTHLABEL \fetch.o_instr [5] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [6] 1
Warning: WIDTHLABEL \fetch.o_instr [6] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [7] 1
Warning: WIDTHLABEL \fetch.o_instr [7] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [8] 1
Warning: WIDTHLABEL \fetch.o_instr [8] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [9] 1
Warning: WIDTHLABEL \fetch.o_instr [9] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [10] 1
Warning: WIDTHLABEL \fetch.o_instr [10] 1
Warning: WIDTHLABEL \fetch.out_instr [11] 1
Warning: WIDTHLABEL \fetch.o_instr [11] 1
Warning: WIDTHLABEL \fetch.out_instr [12] 1
Warning: WIDTHLABEL \fetch.o_instr [12] 1
Warning: WIDTHLABEL \fetch.out_instr [13] 1
Warning: WIDTHLABEL \fetch.o_instr [13] 1
Warning: WIDTHLABEL \fetch.out_instr [14] 1
Warning: WIDTHLABEL \fetch.o_instr [14] 1
Warning: WIDTHLABEL \fetch.out_instr [15] 1
Warning: WIDTHLABEL \fetch.o_instr [15] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [16] 1
Warning: WIDTHLABEL \fetch.o_instr [16] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [17] 1
Warning: WIDTHLABEL \fetch.o_instr [17] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [18] 1
Warning: WIDTHLABEL \fetch.o_instr [18] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [19] 1
Warning: WIDTHLABEL \fetch.o_instr [19] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [20] 1
Warning: WIDTHLABEL \fetch.o_instr [20] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [21] 1
Warning: WIDTHLABEL \fetch.o_instr [21] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [22] 1
Warning: WIDTHLABEL \fetch.o_instr [22] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [23] 1
Warning: WIDTHLABEL \fetch.o_instr [23] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [24] 1
Warning: WIDTHLABEL \fetch.o_instr [24] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [25] 1
Warning: WIDTHLABEL \fetch.o_instr [25] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [26] 1
Warning: WIDTHLABEL \fetch.o_instr [26] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [27] 1
Warning: WIDTHLABEL \fetch.o_instr [27] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [28] 1
Warning: WIDTHLABEL \fetch.o_instr [28] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [29] 1
Warning: WIDTHLABEL \fetch.o_instr [29] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [30] 1
Warning: WIDTHLABEL \fetch.o_instr [30] 1
Warning: WIDTHLABEL \fetch.branch_pred_instr [31] 1
Warning: WIDTHLABEL \fetch.o_instr [31] 1
Warning: WIDTHLABEL \o_req_addr [0] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [0] 1
Warning: WIDTHLABEL \o_req_addr [1] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [1] 1
Warning: WIDTHLABEL \o_req_addr [2] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [2] 1
Warning: WIDTHLABEL \o_req_addr [3] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [3] 1
Warning: WIDTHLABEL \o_req_addr [4] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [4] 1
Warning: WIDTHLABEL \o_req_addr [5] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [5] 1
Warning: WIDTHLABEL \o_req_addr [6] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [6] 1
Warning: WIDTHLABEL \o_req_addr [7] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [7] 1
Warning: WIDTHLABEL \o_req_addr [8] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [8] 1
Warning: WIDTHLABEL \o_req_addr [9] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [9] 1
Warning: WIDTHLABEL \o_req_addr [10] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [10] 1
Warning: WIDTHLABEL \o_req_addr [11] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [11] 1
Warning: WIDTHLABEL \o_req_addr [12] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [12] 1
Warning: WIDTHLABEL \o_req_addr [13] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [13] 1
Warning: WIDTHLABEL \o_req_addr [14] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [14] 1
Warning: WIDTHLABEL \o_req_addr [15] 1
Warning: WIDTHLABEL \fetch.prev_request_pc [15] 1
Warning: WIDTHLABEL \i_req_data [0] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [0] 1
Warning: WIDTHLABEL \i_req_data [1] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [1] 1
Warning: WIDTHLABEL \i_req_data [2] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [2] 1
Warning: WIDTHLABEL \i_req_data [3] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [3] 1
Warning: WIDTHLABEL \i_req_data [4] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [4] 1
Warning: WIDTHLABEL \i_req_data [5] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [5] 1
Warning: WIDTHLABEL \i_req_data [6] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [6] 1
Warning: WIDTHLABEL \i_req_data [7] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [7] 1
Warning: WIDTHLABEL \i_req_data [8] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [8] 1
Warning: WIDTHLABEL \i_req_data [9] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [9] 1
Warning: WIDTHLABEL \i_req_data [10] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [10] 1
Warning: WIDTHLABEL \i_req_data [11] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [11] 1
Warning: WIDTHLABEL \i_req_data [12] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [12] 1
Warning: WIDTHLABEL \i_req_data [13] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [13] 1
Warning: WIDTHLABEL \i_req_data [14] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [14] 1
Warning: WIDTHLABEL \i_req_data [15] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [15] 1
Warning: WIDTHLABEL \i_req_data [16] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [16] 1
Warning: WIDTHLABEL \i_req_data [17] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [17] 1
Warning: WIDTHLABEL \i_req_data [18] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [18] 1
Warning: WIDTHLABEL \i_req_data [19] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [19] 1
Warning: WIDTHLABEL \i_req_data [20] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [20] 1
Warning: WIDTHLABEL \i_req_data [21] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [21] 1
Warning: WIDTHLABEL \i_req_data [22] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [22] 1
Warning: WIDTHLABEL \i_req_data [23] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [23] 1
Warning: WIDTHLABEL \i_req_data [24] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [24] 1
Warning: WIDTHLABEL \i_req_data [25] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [25] 1
Warning: WIDTHLABEL \i_req_data [26] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [26] 1
Warning: WIDTHLABEL \i_req_data [27] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [27] 1
Warning: WIDTHLABEL \i_req_data [28] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [28] 1
Warning: WIDTHLABEL \i_req_data [29] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [29] 1
Warning: WIDTHLABEL \i_req_data [30] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [30] 1
Warning: WIDTHLABEL \i_req_data [31] 1
Warning: WIDTHLABEL \fetch.out_buffer_data_instr [31] 1
Warning: WIDTHLABEL \execute.alu_mul_div.div_cur [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5139.Y [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [1] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5139.Y [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5139.Y [3] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [3] 1
Warning: WIDTHLABEL \execute.pc.o_pc [0] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [1] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [2] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [3] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [4] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [5] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [6] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [7] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [8] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [9] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [10] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [11] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [12] 1
Warning: WIDTHLABEL \decode.oc_alu_mode [13] 1
Warning: WIDTHLABEL \decode.c_used_operands [0] 1
Warning: WIDTHLABEL \decode.oc_used_operands [0] 1
Warning: WIDTHLABEL \decode.c_used_operands [1] 1
Warning: WIDTHLABEL \decode.oc_used_operands [1] 1
Warning: WIDTHLABEL \decode.c_jump_cond_code [0] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [0] 1
Warning: WIDTHLABEL \decode.c_jump_cond_code [1] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [1] 1
Warning: WIDTHLABEL \decode.c_jump_cond_code [2] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [2] 1
Warning: WIDTHLABEL \decode.c_jump_cond_code [3] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [3] 1
Warning: WIDTHLABEL \decode.c_jump_cond_code [4] 1
Warning: WIDTHLABEL \decode.oc_jump_cond_code [4] 1
Warning: WIDTHLABEL \decode.c_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [0] 1
Warning: WIDTHLABEL \decode.c_r_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [1] 1
Warning: WIDTHLABEL \decode.c_r_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_r_reg_sel [2] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [0] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [0] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [1] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [1] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [2] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [2] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [3] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [3] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [4] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [4] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [5] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [5] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [6] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [6] 1
Warning: WIDTHLABEL $flatten\decode.$shift$/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v:0$353.Y [7] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [7] 1
Warning: WIDTHLABEL \decode.c_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [0] 1
Warning: WIDTHLABEL \decode.c_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [1] 1
Warning: WIDTHLABEL \decode.c_l_reg_sel [2] 1
Warning: WIDTHLABEL \decode.oc_l_reg_sel [2] 1
Warning: WIDTHLABEL \fetch.o_instr [16] 1
Warning: WIDTHLABEL \decode.o_imm_pass [0] 1
Warning: WIDTHLABEL \fetch.o_instr [17] 1
Warning: WIDTHLABEL \decode.o_imm_pass [1] 1
Warning: WIDTHLABEL \fetch.o_instr [18] 1
Warning: WIDTHLABEL \decode.o_imm_pass [2] 1
Warning: WIDTHLABEL \fetch.o_instr [19] 1
Warning: WIDTHLABEL \decode.o_imm_pass [3] 1
Warning: WIDTHLABEL \fetch.o_instr [20] 1
Warning: WIDTHLABEL \decode.o_imm_pass [4] 1
Warning: WIDTHLABEL \fetch.o_instr [21] 1
Warning: WIDTHLABEL \decode.o_imm_pass [5] 1
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Warning: WIDTHLABEL \decode.o_imm_pass [6] 1
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Warning: WIDTHLABEL \decode.o_imm_pass [7] 1
Warning: WIDTHLABEL \fetch.o_instr [24] 1
Warning: WIDTHLABEL \decode.o_imm_pass [8] 1
Warning: WIDTHLABEL \fetch.o_instr [25] 1
Warning: WIDTHLABEL \decode.o_imm_pass [9] 1
Warning: WIDTHLABEL \fetch.o_instr [26] 1
Warning: WIDTHLABEL \decode.o_imm_pass [10] 1
Warning: WIDTHLABEL \fetch.o_instr [27] 1
Warning: WIDTHLABEL \decode.o_imm_pass [11] 1
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Warning: WIDTHLABEL \decode.o_imm_pass [12] 1
Warning: WIDTHLABEL \fetch.o_instr [29] 1
Warning: WIDTHLABEL \decode.o_imm_pass [13] 1
Warning: WIDTHLABEL \fetch.o_instr [30] 1
Warning: WIDTHLABEL \decode.o_imm_pass [14] 1
Warning: WIDTHLABEL \fetch.o_instr [31] 1
Warning: WIDTHLABEL \decode.o_imm_pass [15] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.pc_high_buff_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.pc_high_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.pc_high_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.i_d [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [3] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.i_d [4] 1
Warning: WIDTHLABEL \execute.sreg_irq_flags.o_d [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [0] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [0] 1
Warning: WIDTHLABEL \execute.reg_r_con [1] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [1] 1
Warning: WIDTHLABEL \execute.reg_r_con [2] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [2] 1
Warning: WIDTHLABEL \execute.reg_r_con [3] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [3] 1
Warning: WIDTHLABEL \execute.reg_r_con [4] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [4] 1
Warning: WIDTHLABEL \execute.reg_r_con [5] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [5] 1
Warning: WIDTHLABEL \execute.reg_r_con [6] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [6] 1
Warning: WIDTHLABEL \execute.reg_r_con [7] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [7] 1
Warning: WIDTHLABEL \execute.reg_r_con [8] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [8] 1
Warning: WIDTHLABEL \execute.reg_r_con [9] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [9] 1
Warning: WIDTHLABEL \execute.reg_r_con [10] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [10] 1
Warning: WIDTHLABEL \execute.reg_r_con [11] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [11] 1
Warning: WIDTHLABEL \execute.reg_r_con [12] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [12] 1
Warning: WIDTHLABEL \execute.reg_r_con [13] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [13] 1
Warning: WIDTHLABEL \execute.reg_r_con [14] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [14] 1
Warning: WIDTHLABEL \execute.reg_r_con [15] 1
Warning: WIDTHLABEL \execute.sreg_scratch.o_d [15] 1
Warning: WIDTHLABEL \execute.jtr_in [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr.i_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr.i_d [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.i_d [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.i_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.i_d [2] 1
Warning: WIDTHLABEL \execute.sreg_jtr_buff.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [0] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [1] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [1] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [2] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [3] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [3] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [4] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [4] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [5] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [5] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [6] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [6] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [7] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [7] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [8] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [8] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [9] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [9] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [10] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [10] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [11] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [11] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [12] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [12] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [13] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [13] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [14] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [14] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.i_d [15] 1
Warning: WIDTHLABEL \execute.sreg_irq_pc.o_d [15] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.alu_flag_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.pc.o_pc [1] 1
Warning: WIDTHLABEL \execute.pc.o_pc [2] 1
Warning: WIDTHLABEL \execute.pc.o_pc [3] 1
Warning: WIDTHLABEL \execute.pc.o_pc [4] 1
Warning: WIDTHLABEL \execute.pc.o_pc [5] 1
Warning: WIDTHLABEL \execute.pc.o_pc [6] 1
Warning: WIDTHLABEL \execute.pc.o_pc [7] 1
Warning: WIDTHLABEL \execute.pc.o_pc [8] 1
Warning: WIDTHLABEL \execute.pc.o_pc [9] 1
Warning: WIDTHLABEL \execute.pc.o_pc [10] 1
Warning: WIDTHLABEL \execute.pc.o_pc [11] 1
Warning: WIDTHLABEL \execute.pc.o_pc [12] 1
Warning: WIDTHLABEL \execute.pc.o_pc [13] 1
Warning: WIDTHLABEL \execute.pc.o_pc [14] 1
Warning: WIDTHLABEL \execute.pc.o_pc [15] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.X [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [1] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [3] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [4] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [4] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [5] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [6] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [6] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [7] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [7] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [8] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [8] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [9] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [9] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [10] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [10] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [11] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [11] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [12] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [12] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [13] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [13] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [14] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [14] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$5142.Y [15] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [15] 1
Warning: WIDTHLABEL \execute.alu.i_l [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [0] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [1] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [1] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [2] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [2] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [3] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [3] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [4] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [4] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [5] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [5] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [6] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [6] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [7] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [7] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [8] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [8] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [9] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [9] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [10] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [10] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [11] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [11] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [12] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [12] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [13] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [13] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [14] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [14] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [15] 1
Warning: WIDTHLABEL \execute.alu_mul_div.mul_res [15] 1
Warning: WIDTHLABEL \execute.alu.i_r [0] 1
Warning: WIDTHLABEL \execute.alu.i_l [15] 1
Warning: WIDTHLABEL \execute.alu_mul_div.div_cur [0] 1
Warning: WIDTHLABEL \execute.alu_mul_div.cbit [0] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.i_d [2] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[1].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[2].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[3].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[4].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[5].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[6].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [0] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [1] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [2] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [3] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [4] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [5] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [6] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [7] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [8] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [9] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [10] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [11] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [12] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [13] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [14] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[0].rf_reg.i_d [15] 1
Warning: WIDTHLABEL \execute.rf.rf_regs[7].rf_reg.o_d [15] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [0] 1
Warning: WIDTHLABEL \execute.o_reg_ie [0] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [1] 1
Warning: WIDTHLABEL \execute.o_reg_ie [1] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [2] 1
Warning: WIDTHLABEL \execute.o_reg_ie [2] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [3] 1
Warning: WIDTHLABEL \execute.o_reg_ie [3] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [4] 1
Warning: WIDTHLABEL \execute.o_reg_ie [4] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [5] 1
Warning: WIDTHLABEL \execute.o_reg_ie [5] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [6] 1
Warning: WIDTHLABEL \execute.o_reg_ie [6] 1
Warning: WIDTHLABEL \decode.oc_rf_ie [7] 1
Warning: WIDTHLABEL \execute.o_reg_ie [7] 1
Warning: WIDTHLABEL \execute.alu_bus [0] 1
Warning: WIDTHLABEL \execute.o_addr [0] 1
Warning: WIDTHLABEL \execute.alu_bus [1] 1
Warning: WIDTHLABEL \execute.o_addr [1] 1
Warning: WIDTHLABEL \execute.alu_bus [2] 1
Warning: WIDTHLABEL \execute.o_addr [2] 1
Warning: WIDTHLABEL \execute.alu_bus [3] 1
Warning: WIDTHLABEL \execute.o_addr [3] 1
Warning: WIDTHLABEL \execute.alu_bus [4] 1
Warning: WIDTHLABEL \execute.o_addr [4] 1
Warning: WIDTHLABEL \execute.alu_bus [5] 1
Warning: WIDTHLABEL \execute.o_addr [5] 1
Warning: WIDTHLABEL \execute.alu_bus [6] 1
Warning: WIDTHLABEL \execute.o_addr [6] 1
Warning: WIDTHLABEL \execute.alu_bus [7] 1
Warning: WIDTHLABEL \execute.o_addr [7] 1
Warning: WIDTHLABEL \execute.alu_bus [8] 1
Warning: WIDTHLABEL \execute.o_addr [8] 1
Warning: WIDTHLABEL \execute.alu_bus [9] 1
Warning: WIDTHLABEL \execute.o_addr [9] 1
Warning: WIDTHLABEL \execute.alu_bus [10] 1
Warning: WIDTHLABEL \execute.o_addr [10] 1
Warning: WIDTHLABEL \execute.alu_bus [11] 1
Warning: WIDTHLABEL \execute.o_addr [11] 1
Warning: WIDTHLABEL \execute.alu_bus [12] 1
Warning: WIDTHLABEL \execute.o_addr [12] 1
Warning: WIDTHLABEL \execute.alu_bus [13] 1
Warning: WIDTHLABEL \execute.o_addr [13] 1
Warning: WIDTHLABEL \execute.alu_bus [14] 1
Warning: WIDTHLABEL \execute.o_addr [14] 1
Warning: WIDTHLABEL \execute.alu_bus [15] 1
Warning: WIDTHLABEL \execute.o_addr [15] 1
Warning: WIDTHLABEL \execute.o_data [0] 1
Warning: WIDTHLABEL \execute.o_data [1] 1
Warning: WIDTHLABEL \execute.o_data [2] 1
Warning: WIDTHLABEL \execute.o_data [3] 1
Warning: WIDTHLABEL \execute.o_data [4] 1
Warning: WIDTHLABEL \execute.o_data [5] 1
Warning: WIDTHLABEL \execute.o_data [6] 1
Warning: WIDTHLABEL \execute.o_data [7] 1
Warning: WIDTHLABEL \execute.o_data [8] 1
Warning: WIDTHLABEL \execute.o_data [9] 1
Warning: WIDTHLABEL \execute.o_data [10] 1
Warning: WIDTHLABEL \execute.o_data [11] 1
Warning: WIDTHLABEL \execute.o_data [12] 1
Warning: WIDTHLABEL \execute.o_data [13] 1
Warning: WIDTHLABEL \execute.o_data [14] 1
Warning: WIDTHLABEL \execute.o_data [15] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [0] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [0] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [1] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [1] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [2] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [2] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [3] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [3] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [4] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [4] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [5] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [5] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [6] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [6] 1
Warning: WIDTHLABEL \execute.computed_mem_addr_high [7] 1
Warning: WIDTHLABEL \execute.o_mem_addr_high [7] 1
Warning: WIDTHLABEL \execute.pc_high [0] 1
Warning: WIDTHLABEL \execute.prev_pc_high [0] 1
Warning: WIDTHLABEL \execute.pc_high [1] 1
Warning: WIDTHLABEL \execute.prev_pc_high [1] 1
Warning: WIDTHLABEL \execute.pc_high [2] 1
Warning: WIDTHLABEL \execute.prev_pc_high [2] 1
Warning: WIDTHLABEL \execute.pc_high [3] 1
Warning: WIDTHLABEL \execute.prev_pc_high [3] 1
Warning: WIDTHLABEL \execute.pc_high [4] 1
Warning: WIDTHLABEL \execute.prev_pc_high [4] 1
Warning: WIDTHLABEL \execute.pc_high [5] 1
Warning: WIDTHLABEL \execute.prev_pc_high [5] 1
Warning: WIDTHLABEL \execute.pc_high [6] 1
Warning: WIDTHLABEL \execute.prev_pc_high [6] 1
Warning: WIDTHLABEL \execute.pc_high [7] 1
Warning: WIDTHLABEL \execute.prev_pc_high [7] 1
Warning: WIDTHLABEL \execute.pc.o_pc [0] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [0] 1
Warning: WIDTHLABEL \execute.pc.o_pc [1] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [1] 1
Warning: WIDTHLABEL \execute.pc.o_pc [2] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [2] 1
Warning: WIDTHLABEL \execute.pc.o_pc [3] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [3] 1
Warning: WIDTHLABEL \execute.pc.o_pc [4] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [4] 1
Warning: WIDTHLABEL \execute.pc.o_pc [5] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [5] 1
Warning: WIDTHLABEL \execute.pc.o_pc [6] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [6] 1
Warning: WIDTHLABEL \execute.pc.o_pc [7] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [7] 1
Warning: WIDTHLABEL \execute.pc.o_pc [8] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [8] 1
Warning: WIDTHLABEL \execute.pc.o_pc [9] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [9] 1
Warning: WIDTHLABEL \execute.pc.o_pc [10] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [10] 1
Warning: WIDTHLABEL \execute.pc.o_pc [11] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [11] 1
Warning: WIDTHLABEL \execute.pc.o_pc [12] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [12] 1
Warning: WIDTHLABEL \execute.pc.o_pc [13] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [13] 1
Warning: WIDTHLABEL \execute.pc.o_pc [14] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [14] 1
Warning: WIDTHLABEL \execute.pc.o_pc [15] 1
Warning: WIDTHLABEL \execute.mem_stage_pc [15] 1
Warning: WIDTHLABEL \execute.sreg_priv_control.o_d [1] 1

16. Executing SHARE pass (SAT-based resource sharing).

17. Executing OPT pass (performing simple optimizations).

17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \core..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \core.
Performed a total of 0 changes.

17.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\core'.
Removed a total of 0 cells.

17.6. Executing OPT_DFF pass (perform DFF optimizations).

17.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..

17.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module core.

17.9. Finished OPT passes. (There is nothing left to do.)

18. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 0 unused cells and 246 unused wires.
<suppressed ~246 debug messages>

19. Printing statistics.

=== core ===

   Number of wires:               4423
   Number of wire bits:           5238
   Number of public wires:         168
   Number of public wire bits:     943
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               5061
     $_ANDNOT_                    1543
     $_AND_                        157
     $_DFFE_PP_                    196
     $_DFF_P_                       17
     $_MUX_                        636
     $_NAND_                       114
     $_NOR_                        190
     $_NOT_                        181
     $_ORNOT_                      183
     $_OR_                        1072
     $_SDFFCE_PN0P_                 24
     $_SDFFCE_PP0P_                  3
     $_SDFFE_PP0N_                   7
     $_SDFFE_PP0P_                 236
     $_SDFFE_PP1N_                   1
     $_SDFFE_PP1P_                   5
     $_SDFF_PP0_                    14
     $_XNOR_                        72
     $_XOR_                        410

mapping tbuf

20. Executing TECHMAP pass (map to technology primitives).

20.1. Executing Verilog-2005 frontend: /home/piotro/opt/silicon/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
Parsing Verilog input from `/home/piotro/opt/silicon/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.

20.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>

21. Executing SIMPLEMAP pass (map simple cells to gate primitives).

22. Executing TECHMAP pass (map to technology primitives).

22.1. Executing Verilog-2005 frontend: /home/piotro/opt/silicon/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v
Parsing Verilog input from `/home/piotro/opt/silicon/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Successfully finished Verilog frontend.

22.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

23. Executing SIMPLEMAP pass (map simple cells to gate primitives).

24. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

24.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\core':
  mapped 503 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells.

25. Printing statistics.

=== core ===

   Number of wires:               5185
   Number of wire bits:           6000
   Number of public wires:         168
   Number of public wire bits:     943
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               5823
     $_ANDNOT_                    1543
     $_AND_                        157
     $_MUX_                       1398
     $_NAND_                       114
     $_NOR_                        190
     $_NOT_                        181
     $_ORNOT_                      183
     $_OR_                        1072
     $_XNOR_                        72
     $_XOR_                        410
     sky130_fd_sc_hd__dfxtp_2      503

[INFO]: USING STRATEGY AREA 0

26. Executing ABC pass (technology mapping using ABC).

26.1. Extracting gate netlist of module `\core' to `/tmp/yosys-abc-Xvcl1w/input.blif'..
Extracted 5320 gates and 5882 wires to a netlist network with 560 inputs and 584 outputs.

26.1.1. Executing ABC.
Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-Xvcl1w/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-Xvcl1w/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-Xvcl1w/input.blif 
ABC: + read_lib -w /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/synthesis/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.04 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Library "sky130A_merged" from "/home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/synthesis/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use).  Time =     0.07 sec
ABC: Memory =    9.54 MB. Time =     0.07 sec
ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
ABC: + read_constr -v /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/synthesis/synthesis.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2".
ABC: Setting output load to be 33.442001.
ABC: + read_constr /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/tmp/synthesis/synthesis.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 10000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + fraig_store 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + fraig_restore 
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 10000 
ABC: + &get -n 
ABC: + &st 
ABC: + &dch 
ABC: + &nf 
ABC: + &put 
ABC: + buffer -N 10 -S 750.0 
ABC: + upsize -D 10000 
ABC: Current delay (7825.38 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 10000 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =   3926 ( 16.6 %)   Cap = 11.2 ff (  4.1 %)   Area =    33932.54 ( 82.7 %)   Delay =  8107.96 ps  (  4.9 %)               
ABC: Path  0 --     280 : 0    3 pi                        A =   0.00  Df =  20.9  -12.1 ps  S =  34.7 ps  Cin =  0.0 ff  Cout =   6.0 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --    1148 : 1   10 sky130_fd_sc_hd__buf_1    A =   3.75  Df = 262.0  -96.5 ps  S = 282.7 ps  Cin =  2.1 ff  Cout =  23.5 ff  Cmax = 130.0 ff  G = 1073  
ABC: Path  2 --    1286 : 2    1 sky130_fd_sc_hd__or2b_2   A =   8.76  Df = 581.7 -229.4 ps  S =  50.2 ps  Cin =  1.6 ff  Cout =   2.5 ff  Cmax = 312.2 ff  G =  153  
ABC: Path  3 --    1290 : 5    1 sky130_fd_sc_hd__a2111o_2 A =  12.51  Df =1044.6 -419.4 ps  S =  66.9 ps  Cin =  2.4 ff  Cout =   4.7 ff  Cmax = 324.1 ff  G =  181  
ABC: Path  4 --    1291 : 5    8 sky130_fd_sc_hd__o32ai_2  A =  16.27  Df =1572.6 -496.8 ps  S = 630.2 ps  Cin =  4.4 ff  Cout =  32.3 ff  Cmax =  88.8 ff  G =  711  
ABC: Path  5 --    1292 : 1    4 sky130_fd_sc_hd__inv_2    A =   3.75  Df =1809.7 -523.8 ps  S = 200.1 ps  Cin =  4.5 ff  Cout =  40.2 ff  Cmax = 331.4 ff  G =  894  
ABC: Path  6 --    2399 : 3    3 sky130_fd_sc_hd__mux2_2   A =  11.26  Df =2152.1 -658.8 ps  S =  66.5 ps  Cin =  2.3 ff  Cout =   8.3 ff  Cmax = 297.6 ff  G =  354  
ABC: Path  7 --    2400 : 1   10 sky130_fd_sc_hd__buf_1    A =   3.75  Df =2343.2 -568.8 ps  S = 325.6 ps  Cin =  2.1 ff  Cout =  27.2 ff  Cmax = 130.0 ff  G = 1237  
ABC: Path  8 --    3204 : 4    2 sky130_fd_sc_hd__a31o_2   A =   8.76  Df =2622.9 -618.9 ps  S =  64.9 ps  Cin =  2.4 ff  Cout =   7.3 ff  Cmax = 271.9 ff  G =  292  
ABC: Path  9 --    3205 : 3    3 sky130_fd_sc_hd__a21o_2   A =   8.76  Df =2824.7 -371.0 ps  S =  61.7 ps  Cin =  2.4 ff  Cout =   9.6 ff  Cmax = 309.5 ff  G =  390  
ABC: Path 10 --    3249 : 3    2 sky130_fd_sc_hd__a21o_2   A =   8.76  Df =3042.1 -206.3 ps  S =  48.2 ps  Cin =  2.4 ff  Cout =   6.6 ff  Cmax = 309.5 ff  G =  270  
ABC: Path 11 --    3250 : 3    4 sky130_fd_sc_hd__and3_2   A =   7.51  Df =3283.7 -139.6 ps  S = 106.5 ps  Cin =  1.5 ff  Cout =  16.6 ff  Cmax = 309.5 ff  G = 1073  
ABC: Path 12 --    3254 : 3    3 sky130_fd_sc_hd__or3b_2   A =   8.76  Df =3795.2 -441.0 ps  S = 107.4 ps  Cin =  1.5 ff  Cout =  11.7 ff  Cmax = 269.2 ff  G =  744  
ABC: Path 13 --    3288 : 2    2 sky130_fd_sc_hd__nand2_2  A =   6.26  Df =3895.5 -389.4 ps  S =  71.0 ps  Cin =  4.4 ff  Cout =   9.9 ff  Cmax = 295.7 ff  G =  218  
ABC: Path 14 --    3295 : 2    2 sky130_fd_sc_hd__xnor2_2  A =  16.27  Df =4048.0 -161.3 ps  S = 183.3 ps  Cin =  8.5 ff  Cout =  10.0 ff  Cmax = 121.8 ff  G =  113  
ABC: Path 15 --    3296 : 2    2 sky130_fd_sc_hd__or2_2    A =   6.26  Df =4341.8 -299.8 ps  S =  67.1 ps  Cin =  1.5 ff  Cout =   7.0 ff  Cmax = 299.4 ff  G =  466  
ABC: Path 16 --    3298 : 4    4 sky130_fd_sc_hd__a211oi_2 A =  12.51  Df =4684.4 -384.9 ps  S = 322.2 ps  Cin =  4.4 ff  Cout =  14.3 ff  Cmax =  88.8 ff  G =  308  
ABC: Path 17 --    3307 : 4    2 sky130_fd_sc_hd__o211a_2  A =  10.01  Df =4938.7 -211.2 ps  S =  78.3 ps  Cin =  2.4 ff  Cout =   9.3 ff  Cmax = 268.3 ff  G =  368  
ABC: Path 18 --    3329 : 4    4 sky130_fd_sc_hd__o211ai_2 A =  12.51  Df =5040.3   -3.2 ps  S = 189.7 ps  Cin =  4.4 ff  Cout =  10.2 ff  Cmax = 133.7 ff  G =  225  
ABC: Path 19 --    3741 : 2    2 sky130_fd_sc_hd__and2b_2  A =   8.76  Df =5265.6  -46.9 ps  S =  51.8 ps  Cin =  1.6 ff  Cout =   6.1 ff  Cmax = 310.4 ff  G =  367  
ABC: Path 20 --    3743 : 2    1 sky130_fd_sc_hd__or2_2    A =   6.26  Df =5528.0 -214.8 ps  S =  52.5 ps  Cin =  1.5 ff  Cout =   2.5 ff  Cmax = 299.4 ff  G =  163  
ABC: Path 21 --    3764 : 4    2 sky130_fd_sc_hd__a31o_2   A =   8.76  Df =5794.2  -28.9 ps  S =  79.8 ps  Cin =  2.4 ff  Cout =  10.8 ff  Cmax = 271.9 ff  G =  441  
ABC: Path 22 --    3779 : 2    1 sky130_fd_sc_hd__or2b_2   A =   8.76  Df =6069.3 -203.7 ps  S =  46.3 ps  Cin =  1.6 ff  Cout =   1.5 ff  Cmax = 312.2 ff  G =   91  
ABC: Path 23 --    3920 : 4    1 sky130_fd_sc_hd__or4_2    A =   8.76  Df =6707.4 -753.1 ps  S =  91.3 ps  Cin =  1.5 ff  Cout =   1.6 ff  Cmax = 310.4 ff  G =  103  
ABC: Path 24 --    3955 : 3    1 sky130_fd_sc_hd__or3_2    A =   7.51  Df =7172.8-1117.9 ps  S =  68.3 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   88  
ABC: Path 25 --    3956 : 4    1 sky130_fd_sc_hd__or4_2    A =   8.76  Df =7722.4-1078.1 ps  S = 107.5 ps  Cin =  1.5 ff  Cout =   4.4 ff  Cmax = 310.4 ff  G =  290  
ABC: Path 26 --    3957 : 4    1 sky130_fd_sc_hd__o211ai_2 A =  12.51  Df =7798.0-1095.5 ps  S = 109.8 ps  Cin =  4.4 ff  Cout =   2.4 ff  Cmax = 133.7 ff  G =   53  
ABC: Path 27 --    3958 : 4    1 sky130_fd_sc_hd__o211a_2  A =  10.01  Df =8108.0-1196.7 ps  S = 204.2 ps  Cin =  2.4 ff  Cout =  33.4 ff  Cmax = 268.3 ff  G = 1415  
ABC: Start-point = pi279 (\decode.oc_r_reg_sel [2]).  End-point = po317 ($auto$rtlil.cc:2560:MuxGate$24410).
ABC: + print_stats -m 
ABC: netlist                       : i/o =  560/  584  lat =    0  nd =  3926  edge =  10774  area =33934.92  delay =32.00  lev = 32
ABC: + write_blif /tmp/yosys-abc-Xvcl1w/output.blif 

26.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a2111oi_2 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__nor4_2 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__and4bb_2 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__o41a_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__o32ai_2 cells:        8
ABC RESULTS:   sky130_fd_sc_hd__nand4_2 cells:        6
ABC RESULTS:   sky130_fd_sc_hd__o22ai_2 cells:       17
ABC RESULTS:   sky130_fd_sc_hd__a21boi_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__and4b_2 cells:       37
ABC RESULTS:   sky130_fd_sc_hd__a41o_2 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__nor2b_2 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__nand2b_2 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__a311oi_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__nand3_2 cells:       31
ABC RESULTS:   sky130_fd_sc_hd__a211oi_2 cells:       18
ABC RESULTS:   sky130_fd_sc_hd__a2111o_2 cells:       13
ABC RESULTS:   sky130_fd_sc_hd__a221oi_2 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__a32o_2 cells:       18
ABC RESULTS:   sky130_fd_sc_hd__o311a_2 cells:        7
ABC RESULTS:   sky130_fd_sc_hd__or4b_2 cells:       13
ABC RESULTS:   sky130_fd_sc_hd__a311o_2 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__o31ai_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__o211ai_2 cells:       12
ABC RESULTS:   sky130_fd_sc_hd__o2111a_2 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__o221ai_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a22oi_2 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__nor3_2 cells:       31
ABC RESULTS:   sky130_fd_sc_hd__a31oi_2 cells:        6
ABC RESULTS:   sky130_fd_sc_hd__o221a_2 cells:       13
ABC RESULTS:   sky130_fd_sc_hd__and3b_2 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__or3b_2 cells:       28
ABC RESULTS:   sky130_fd_sc_hd__nor3b_2 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__o21bai_2 cells:       12
ABC RESULTS:   sky130_fd_sc_hd__mux4_2 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__and4_2 cells:       23
ABC RESULTS:   sky130_fd_sc_hd__o22a_2 cells:       37
ABC RESULTS:   sky130_fd_sc_hd__o32a_2 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__o31a_2 cells:       17
ABC RESULTS:   sky130_fd_sc_hd__a21bo_2 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__and2b_2 cells:       31
ABC RESULTS:   sky130_fd_sc_hd__o2bb2a_2 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__a211o_2 cells:      101
ABC RESULTS:   sky130_fd_sc_hd__a31o_2 cells:       41
ABC RESULTS:   sky130_fd_sc_hd__a2bb2o_2 cells:       24
ABC RESULTS:   sky130_fd_sc_hd__or3_2 cells:       61
ABC RESULTS:   sky130_fd_sc_hd__o21ai_2 cells:       71
ABC RESULTS:   sky130_fd_sc_hd__inv_2 cells:      131
ABC RESULTS:   sky130_fd_sc_hd__o21a_2 cells:       94
ABC RESULTS:   sky130_fd_sc_hd__nand3b_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__or4_2 cells:       38
ABC RESULTS:   sky130_fd_sc_hd__xor2_2 cells:       42
ABC RESULTS:   sky130_fd_sc_hd__or2b_2 cells:       50
ABC RESULTS:   sky130_fd_sc_hd__o21ba_2 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__a22o_2 cells:      181
ABC RESULTS:   sky130_fd_sc_hd__a221o_2 cells:      114
ABC RESULTS:   sky130_fd_sc_hd__nand2_2 cells:      275
ABC RESULTS:   sky130_fd_sc_hd__a21o_2 cells:      111
ABC RESULTS:   sky130_fd_sc_hd__a21oi_2 cells:      126
ABC RESULTS:   sky130_fd_sc_hd__xnor2_2 cells:      146
ABC RESULTS:   sky130_fd_sc_hd__and3_2 cells:       93
ABC RESULTS:   sky130_fd_sc_hd__nor2_2 cells:      240
ABC RESULTS:   sky130_fd_sc_hd__and2_2 cells:      113
ABC RESULTS:   sky130_fd_sc_hd__or2_2 cells:      166
ABC RESULTS:   sky130_fd_sc_hd__o211a_2 cells:      237
ABC RESULTS:   sky130_fd_sc_hd__mux2_2 cells:      367
ABC RESULTS:   sky130_fd_sc_hd__buf_1 cells:      520
ABC RESULTS:        internal signals:     4738
ABC RESULTS:           input signals:      560
ABC RESULTS:          output signals:      584
Removing temp directory.

27. Executing SETUNDEF pass (replace undef values with defined constants).

28. Executing HILOMAP pass (mapping to constant drivers).

29. Executing SPLITNETS pass (splitting up multi-bit signals).

30. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \core..
Removed 15 unused cells and 5997 unused wires.
<suppressed ~297 debug messages>

31. Executing INSBUF pass (insert buffer cells for connected wires).
Added core.$auto$insbuf.cc:79:execute$29266: \dbg_out [16] -> \dbg_pc [0]
Added core.$auto$insbuf.cc:79:execute$29267: \dbg_out [17] -> \dbg_pc [1]
Added core.$auto$insbuf.cc:79:execute$29268: \dbg_out [18] -> \dbg_pc [2]
Added core.$auto$insbuf.cc:79:execute$29269: \dbg_out [19] -> \dbg_pc [3]
Added core.$auto$insbuf.cc:79:execute$29270: \dbg_out [20] -> \dbg_pc [4]
Added core.$auto$insbuf.cc:79:execute$29271: \dbg_out [21] -> \dbg_pc [5]
Added core.$auto$insbuf.cc:79:execute$29272: \dbg_out [22] -> \dbg_pc [6]
Added core.$auto$insbuf.cc:79:execute$29273: \dbg_out [23] -> \dbg_pc [7]
Added core.$auto$insbuf.cc:79:execute$29274: \dbg_out [24] -> \dbg_pc [8]
Added core.$auto$insbuf.cc:79:execute$29275: \dbg_out [25] -> \dbg_pc [9]
Added core.$auto$insbuf.cc:79:execute$29276: \dbg_out [26] -> \dbg_pc [10]
Added core.$auto$insbuf.cc:79:execute$29277: \dbg_out [27] -> \dbg_pc [11]
Added core.$auto$insbuf.cc:79:execute$29278: \dbg_out [28] -> \dbg_pc [12]
Added core.$auto$insbuf.cc:79:execute$29279: \dbg_out [29] -> \dbg_pc [13]
Added core.$auto$insbuf.cc:79:execute$29280: \dbg_out [30] -> \dbg_pc [14]
Added core.$auto$insbuf.cc:79:execute$29281: \dbg_out [31] -> \dbg_pc [15]

32. Executing CHECK pass (checking for obvious problems).
Checking module core...
Warning: Wire core.\sr_bus_we is used but has no driver.
Warning: Wire core.\sr_bus_data_o [15] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [14] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [13] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [12] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [11] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [10] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [9] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [8] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [7] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [6] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [5] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [4] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [3] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [2] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [1] is used but has no driver.
Warning: Wire core.\sr_bus_data_o [0] is used but has no driver.
Warning: Wire core.\sr_bus_addr [15] is used but has no driver.
Warning: Wire core.\sr_bus_addr [14] is used but has no driver.
Warning: Wire core.\sr_bus_addr [13] is used but has no driver.
Warning: Wire core.\sr_bus_addr [12] is used but has no driver.
Warning: Wire core.\sr_bus_addr [11] is used but has no driver.
Warning: Wire core.\sr_bus_addr [10] is used but has no driver.
Warning: Wire core.\sr_bus_addr [9] is used but has no driver.
Warning: Wire core.\sr_bus_addr [8] is used but has no driver.
Warning: Wire core.\sr_bus_addr [7] is used but has no driver.
Warning: Wire core.\sr_bus_addr [6] is used but has no driver.
Warning: Wire core.\sr_bus_addr [5] is used but has no driver.
Warning: Wire core.\sr_bus_addr [4] is used but has no driver.
Warning: Wire core.\sr_bus_addr [3] is used but has no driver.
Warning: Wire core.\sr_bus_addr [2] is used but has no driver.
Warning: Wire core.\sr_bus_addr [1] is used but has no driver.
Warning: Wire core.\sr_bus_addr [0] is used but has no driver.
Warning: Wire core.\o_req_ppl_submit is used but has no driver.
Warning: Wire core.\o_req_addr [15] is used but has no driver.
Warning: Wire core.\o_req_addr [14] is used but has no driver.
Warning: Wire core.\o_req_addr [13] is used but has no driver.
Warning: Wire core.\o_req_addr [12] is used but has no driver.
Warning: Wire core.\o_req_addr [11] is used but has no driver.
Warning: Wire core.\o_req_addr [10] is used but has no driver.
Warning: Wire core.\o_req_addr [9] is used but has no driver.
Warning: Wire core.\o_req_addr [8] is used but has no driver.
Warning: Wire core.\o_req_addr [7] is used but has no driver.
Warning: Wire core.\o_req_addr [6] is used but has no driver.
Warning: Wire core.\o_req_addr [5] is used but has no driver.
Warning: Wire core.\o_req_addr [4] is used but has no driver.
Warning: Wire core.\o_req_addr [3] is used but has no driver.
Warning: Wire core.\o_req_addr [2] is used but has no driver.
Warning: Wire core.\o_req_addr [1] is used but has no driver.
Warning: Wire core.\o_req_addr [0] is used but has no driver.
Warning: Wire core.\o_req_active is used but has no driver.
Warning: Wire core.\o_mem_we is used but has no driver.
Warning: Wire core.\o_mem_sel [1] is used but has no driver.
Warning: Wire core.\o_mem_sel [0] is used but has no driver.
Warning: Wire core.\o_mem_req is used but has no driver.
Warning: Wire core.\o_mem_long is used but has no driver.
Warning: Wire core.\o_mem_data [15] is used but has no driver.
Warning: Wire core.\o_mem_data [14] is used but has no driver.
Warning: Wire core.\o_mem_data [13] is used but has no driver.
Warning: Wire core.\o_mem_data [12] is used but has no driver.
Warning: Wire core.\o_mem_data [11] is used but has no driver.
Warning: Wire core.\o_mem_data [10] is used but has no driver.
Warning: Wire core.\o_mem_data [9] is used but has no driver.
Warning: Wire core.\o_mem_data [8] is used but has no driver.
Warning: Wire core.\o_mem_data [7] is used but has no driver.
Warning: Wire core.\o_mem_data [6] is used but has no driver.
Warning: Wire core.\o_mem_data [5] is used but has no driver.
Warning: Wire core.\o_mem_data [4] is used but has no driver.
Warning: Wire core.\o_mem_data [3] is used but has no driver.
Warning: Wire core.\o_mem_data [2] is used but has no driver.
Warning: Wire core.\o_mem_data [1] is used but has no driver.
Warning: Wire core.\o_mem_data [0] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [7] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [6] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [5] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [4] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [3] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [2] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [1] is used but has no driver.
Warning: Wire core.\o_mem_addr_high [0] is used but has no driver.
Warning: Wire core.\o_mem_addr [15] is used but has no driver.
Warning: Wire core.\o_mem_addr [14] is used but has no driver.
Warning: Wire core.\o_mem_addr [13] is used but has no driver.
Warning: Wire core.\o_mem_addr [12] is used but has no driver.
Warning: Wire core.\o_mem_addr [11] is used but has no driver.
Warning: Wire core.\o_mem_addr [10] is used but has no driver.
Warning: Wire core.\o_mem_addr [9] is used but has no driver.
Warning: Wire core.\o_mem_addr [8] is used but has no driver.
Warning: Wire core.\o_mem_addr [7] is used but has no driver.
Warning: Wire core.\o_mem_addr [6] is used but has no driver.
Warning: Wire core.\o_mem_addr [5] is used but has no driver.
Warning: Wire core.\o_mem_addr [4] is used but has no driver.
Warning: Wire core.\o_mem_addr [3] is used but has no driver.
Warning: Wire core.\o_mem_addr [2] is used but has no driver.
Warning: Wire core.\o_mem_addr [1] is used but has no driver.
Warning: Wire core.\o_mem_addr [0] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [7] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [6] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [5] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [4] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [3] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [2] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [1] is used but has no driver.
Warning: Wire core.\o_instr_long_addr [0] is used but has no driver.
Warning: Wire core.\o_icache_flush is used but has no driver.
Warning: Wire core.\o_c_instr_page is used but has no driver.
Warning: Wire core.\o_c_instr_long is used but has no driver.
Warning: Wire core.\o_c_data_page is used but has no driver.
Warning: Wire core.\dbg_r0 [15] is used but has no driver.
Warning: Wire core.\dbg_r0 [14] is used but has no driver.
Warning: Wire core.\dbg_r0 [13] is used but has no driver.
Warning: Wire core.\dbg_r0 [12] is used but has no driver.
Warning: Wire core.\dbg_r0 [11] is used but has no driver.
Warning: Wire core.\dbg_r0 [10] is used but has no driver.
Warning: Wire core.\dbg_r0 [9] is used but has no driver.
Warning: Wire core.\dbg_r0 [8] is used but has no driver.
Warning: Wire core.\dbg_r0 [7] is used but has no driver.
Warning: Wire core.\dbg_r0 [6] is used but has no driver.
Warning: Wire core.\dbg_r0 [5] is used but has no driver.
Warning: Wire core.\dbg_r0 [4] is used but has no driver.
Warning: Wire core.\dbg_r0 [3] is used but has no driver.
Warning: Wire core.\dbg_r0 [2] is used but has no driver.
Warning: Wire core.\dbg_r0 [1] is used but has no driver.
Warning: Wire core.\dbg_r0 [0] is used but has no driver.
Warning: Wire core.\dbg_pc [15] is used but has no driver.
Warning: Wire core.\dbg_pc [14] is used but has no driver.
Warning: Wire core.\dbg_pc [13] is used but has no driver.
Warning: Wire core.\dbg_pc [12] is used but has no driver.
Warning: Wire core.\dbg_pc [11] is used but has no driver.
Warning: Wire core.\dbg_pc [10] is used but has no driver.
Warning: Wire core.\dbg_pc [9] is used but has no driver.
Warning: Wire core.\dbg_pc [8] is used but has no driver.
Warning: Wire core.\dbg_pc [7] is used but has no driver.
Warning: Wire core.\dbg_pc [6] is used but has no driver.
Warning: Wire core.\dbg_pc [5] is used but has no driver.
Warning: Wire core.\dbg_pc [4] is used but has no driver.
Warning: Wire core.\dbg_pc [3] is used but has no driver.
Warning: Wire core.\dbg_pc [2] is used but has no driver.
Warning: Wire core.\dbg_pc [1] is used but has no driver.
Warning: Wire core.\dbg_pc [0] is used but has no driver.
Warning: Wire core.\dbg_out [35] is used but has no driver.
Warning: Wire core.\dbg_out [34] is used but has no driver.
Warning: Wire core.\dbg_out [33] is used but has no driver.
Warning: Wire core.\dbg_out [32] is used but has no driver.
Warning: Wire core.\dbg_out [31] is used but has no driver.
Warning: Wire core.\dbg_out [30] is used but has no driver.
Warning: Wire core.\dbg_out [29] is used but has no driver.
Warning: Wire core.\dbg_out [28] is used but has no driver.
Warning: Wire core.\dbg_out [27] is used but has no driver.
Warning: Wire core.\dbg_out [26] is used but has no driver.
Warning: Wire core.\dbg_out [25] is used but has no driver.
Warning: Wire core.\dbg_out [24] is used but has no driver.
Warning: Wire core.\dbg_out [23] is used but has no driver.
Warning: Wire core.\dbg_out [22] is used but has no driver.
Warning: Wire core.\dbg_out [21] is used but has no driver.
Warning: Wire core.\dbg_out [20] is used but has no driver.
Warning: Wire core.\dbg_out [19] is used but has no driver.
Warning: Wire core.\dbg_out [18] is used but has no driver.
Warning: Wire core.\dbg_out [17] is used but has no driver.
Warning: Wire core.\dbg_out [16] is used but has no driver.
Warning: Wire core.\dbg_out [15] is used but has no driver.
Warning: Wire core.\dbg_out [14] is used but has no driver.
Warning: Wire core.\dbg_out [13] is used but has no driver.
Warning: Wire core.\dbg_out [12] is used but has no driver.
Warning: Wire core.\dbg_out [11] is used but has no driver.
Warning: Wire core.\dbg_out [10] is used but has no driver.
Warning: Wire core.\dbg_out [9] is used but has no driver.
Warning: Wire core.\dbg_out [8] is used but has no driver.
Warning: Wire core.\dbg_out [7] is used but has no driver.
Warning: Wire core.\dbg_out [6] is used but has no driver.
Warning: Wire core.\dbg_out [5] is used but has no driver.
Warning: Wire core.\dbg_out [4] is used but has no driver.
Warning: Wire core.\dbg_out [3] is used but has no driver.
Warning: Wire core.\dbg_out [2] is used but has no driver.
Warning: Wire core.\dbg_out [1] is used but has no driver.
Warning: Wire core.\dbg_out [0] is used but has no driver.
Found and reported 176 problems.

33. Printing statistics.

=== core ===

   Number of wires:               4286
   Number of wire bits:           4505
   Number of public wires:         443
   Number of public wire bits:     662
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               4446
     sky130_fd_sc_hd__a2111o_2      13
     sky130_fd_sc_hd__a2111oi_2     10
     sky130_fd_sc_hd__a211o_2      101
     sky130_fd_sc_hd__a211oi_2      18
     sky130_fd_sc_hd__a21bo_2       21
     sky130_fd_sc_hd__a21boi_2       3
     sky130_fd_sc_hd__a21o_2       111
     sky130_fd_sc_hd__a21oi_2      126
     sky130_fd_sc_hd__a221o_2      114
     sky130_fd_sc_hd__a221oi_2       5
     sky130_fd_sc_hd__a22o_2       181
     sky130_fd_sc_hd__a22oi_2        2
     sky130_fd_sc_hd__a2bb2o_2      24
     sky130_fd_sc_hd__a311o_2       11
     sky130_fd_sc_hd__a311oi_2       1
     sky130_fd_sc_hd__a31o_2        41
     sky130_fd_sc_hd__a31oi_2        6
     sky130_fd_sc_hd__a32o_2        18
     sky130_fd_sc_hd__a41o_2         4
     sky130_fd_sc_hd__and2_2       113
     sky130_fd_sc_hd__and2b_2       31
     sky130_fd_sc_hd__and3_2        93
     sky130_fd_sc_hd__and3b_2       21
     sky130_fd_sc_hd__and4_2        23
     sky130_fd_sc_hd__and4b_2       37
     sky130_fd_sc_hd__and4bb_2      21
     sky130_fd_sc_hd__buf_1        520
     sky130_fd_sc_hd__buf_2         16
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfxtp_2      503
     sky130_fd_sc_hd__inv_2        131
     sky130_fd_sc_hd__mux2_2       367
     sky130_fd_sc_hd__mux4_2        21
     sky130_fd_sc_hd__nand2_2      275
     sky130_fd_sc_hd__nand2b_2       5
     sky130_fd_sc_hd__nand3_2       31
     sky130_fd_sc_hd__nand3b_2       1
     sky130_fd_sc_hd__nand4_2        6
     sky130_fd_sc_hd__nor2_2       240
     sky130_fd_sc_hd__nor2b_2        2
     sky130_fd_sc_hd__nor3_2        31
     sky130_fd_sc_hd__nor3b_2       11
     sky130_fd_sc_hd__nor4_2         2
     sky130_fd_sc_hd__o2111a_2       4
     sky130_fd_sc_hd__o211a_2      237
     sky130_fd_sc_hd__o211ai_2      12
     sky130_fd_sc_hd__o21a_2        94
     sky130_fd_sc_hd__o21ai_2       71
     sky130_fd_sc_hd__o21ba_2       22
     sky130_fd_sc_hd__o21bai_2      12
     sky130_fd_sc_hd__o221a_2       13
     sky130_fd_sc_hd__o221ai_2       3
     sky130_fd_sc_hd__o22a_2        37
     sky130_fd_sc_hd__o22ai_2       17
     sky130_fd_sc_hd__o2bb2a_2      21
     sky130_fd_sc_hd__o311a_2        7
     sky130_fd_sc_hd__o31a_2        17
     sky130_fd_sc_hd__o31ai_2        1
     sky130_fd_sc_hd__o32a_2        11
     sky130_fd_sc_hd__o32ai_2        8
     sky130_fd_sc_hd__o41a_2         3
     sky130_fd_sc_hd__or2_2        166
     sky130_fd_sc_hd__or2b_2        50
     sky130_fd_sc_hd__or3_2         61
     sky130_fd_sc_hd__or3b_2        28
     sky130_fd_sc_hd__or4_2         38
     sky130_fd_sc_hd__or4b_2        13
     sky130_fd_sc_hd__xnor2_2      146
     sky130_fd_sc_hd__xor2_2        42

   Chip area for module '\core': 44715.385600

34. Executing Verilog backend.

34.1. Executing BMUXMAP pass.

34.2. Executing DEMUXMAP pass.
Dumping module `\core'.

Warnings: 1059 unique messages, 3305 total
End of script. Logfile hash: 7435add135, CPU: user 5.78s system 0.05s, MEM: 74.08 MB peak
Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
Time spent: 60% 2x abc (8 sec), 10% 55x opt_expr (1 sec), ...