OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ORD-0030] Using 6 thread(s).
[INFO DRT-0149] Reading tech and libs.

Units:                1000
Number of layers:     13
Number of macros:     441
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   core
Die area:                 ( 0 0 ) ( 500000 500000 )
Number of track patterns: 12
Number of DEF vias:       3
Number of components:     35762
Number of terminals:      254
Number of snets:          2
Number of nets:           4896

[INFO DRT-0167] List of default vias:
  Layer mcon
    default via: L1M1_PR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
[INFO DRT-0164] Number of unique instances = 486.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete Fr_VIA.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 278858.
[INFO DRT-0033] mcon shape region query size = 362625.
[INFO DRT-0033] met1 shape region query size = 80110.
[INFO DRT-0033] via shape region query size = 3080.
[INFO DRT-0033] met2 shape region query size = 1920.
[INFO DRT-0033] via2 shape region query size = 2464.
[INFO DRT-0033] met3 shape region query size = 2028.
[INFO DRT-0033] via3 shape region query size = 2464.
[INFO DRT-0033] met4 shape region query size = 630.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0076]   Complete 600 pins.
[INFO DRT-0076]   Complete 700 pins.
[INFO DRT-0076]   Complete 800 pins.
[INFO DRT-0076]   Complete 900 pins.
[INFO DRT-0077]   Complete 1000 pins.
[INFO DRT-0078]   Complete 1934 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0079]   Complete 200 unique inst patterns.
[INFO DRT-0079]   Complete 300 unique inst patterns.
[INFO DRT-0079]   Complete 400 unique inst patterns.
[INFO DRT-0081]   Complete 468 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0084]   Complete 9638 groups.
#scanned instances     = 35762
#unique  instances     = 486
#stdCellGenAp          = 14445
#stdCellValidPlanarAp  = 61
#stdCellValidViaAp     = 11079
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 17024
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:01:10, elapsed time = 00:00:12, memory = 236.71 (MB), peak = 238.40 (MB)

Number of guides:     46739

[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 72 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 72 STEP 6900 ;
[INFO DRT-0026]   Complete 10000 origin guides.
[INFO DRT-0026]   Complete 20000 origin guides.
[INFO DRT-0026]   Complete 30000 origin guides.
[INFO DRT-0026]   Complete 40000 origin guides.
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete Fr_VIA.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete Fr_VIA (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 17253.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 14110.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 7566.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 303.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 54.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 24873 vertical wires in 2 frboxes and 14413 horizontal wires in 2 frboxes.
[INFO DRT-0186] Done with 2888 vertical wires in 2 frboxes and 4602 horizontal wires in 2 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:02, memory = 332.11 (MB), peak = 387.51 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 332.11 (MB), peak = 387.51 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:01, memory = 589.16 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:03, memory = 823.19 (MB).
    Completing 30% with 643 violations.
    elapsed time = 00:00:04, memory = 627.88 (MB).
    Completing 40% with 643 violations.
    elapsed time = 00:00:06, memory = 760.86 (MB).
    Completing 50% with 643 violations.
    elapsed time = 00:00:08, memory = 839.04 (MB).
    Completing 60% with 1276 violations.
    elapsed time = 00:00:09, memory = 676.45 (MB).
    Completing 70% with 1276 violations.
    elapsed time = 00:00:13, memory = 789.37 (MB).
    Completing 80% with 1816 violations.
    elapsed time = 00:00:15, memory = 769.68 (MB).
    Completing 90% with 1816 violations.
    elapsed time = 00:00:17, memory = 825.46 (MB).
    Completing 100% with 2367 violations.
    elapsed time = 00:00:21, memory = 784.93 (MB).
[INFO DRT-0199]   Number of violations = 4516.
Viol/Layer         li1   mcon   met1    via   met2   met3   met4
Cut Spacing          0      1      0      0      0      0      0
Metal Spacing       23      0    444      0     37     27      0
Min Hole             0      0      1      0      0      0      0
NS Metal             1      0      0      0      0      0      0
Recheck              0      0   1422      0    596    130      1
Short                0      0   1735      1     97      0      0
[INFO DRT-0267] cpu time = 00:01:42, elapsed time = 00:00:21, memory = 1045.81 (MB), peak = 1045.81 (MB)
Total wire length = 287943 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 145103 um.
Total wire length on LAYER met2 = 133048 um.
Total wire length on LAYER met3 = 4741 um.
Total wire length on LAYER met4 = 5049 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 46928.
Up-via summary (total 46928):.

------------------------
 FR_MASTERSLICE        0
            li1    21818
           met1    24603
           met2      400
           met3      107
           met4        0
------------------------
                   46928


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 4516 violations.
    elapsed time = 00:00:00, memory = 1062.84 (MB).
    Completing 20% with 4516 violations.
    elapsed time = 00:00:02, memory = 1143.39 (MB).
    Completing 30% with 3594 violations.
    elapsed time = 00:00:05, memory = 1049.58 (MB).
    Completing 40% with 3594 violations.
    elapsed time = 00:00:07, memory = 1092.91 (MB).
    Completing 50% with 3594 violations.
    elapsed time = 00:00:09, memory = 1139.76 (MB).
    Completing 60% with 2663 violations.
    elapsed time = 00:00:11, memory = 1078.08 (MB).
    Completing 70% with 2663 violations.
    elapsed time = 00:00:13, memory = 1130.09 (MB).
    Completing 80% with 2096 violations.
    elapsed time = 00:00:15, memory = 1061.95 (MB).
    Completing 90% with 2096 violations.
    elapsed time = 00:00:18, memory = 1114.04 (MB).
    Completing 100% with 1566 violations.
    elapsed time = 00:00:22, memory = 1068.26 (MB).
[INFO DRT-0199]   Number of violations = 2073.
Viol/Layer        mcon   met1    via   met2   met3
Cut Spacing          2      0      0      0      0
Metal Spacing        0    311      0     22      0
Recheck              0      0      0      0    507
Short                0   1200      1     30      0
[INFO DRT-0267] cpu time = 00:01:44, elapsed time = 00:00:22, memory = 1071.09 (MB), peak = 1210.50 (MB)
Total wire length = 286090 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 144660 um.
Total wire length on LAYER met2 = 131812 um.
Total wire length on LAYER met3 = 4616 um.
Total wire length on LAYER met4 = 5001 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 46779.
Up-via summary (total 46779):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24458
           met2      406
           met3      104
           met4        0
------------------------
                   46779


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 2073 violations.
    elapsed time = 00:00:00, memory = 1071.26 (MB).
    Completing 20% with 2073 violations.
    elapsed time = 00:00:02, memory = 1155.94 (MB).
    Completing 30% with 1838 violations.
    elapsed time = 00:00:05, memory = 1096.43 (MB).
    Completing 40% with 1838 violations.
    elapsed time = 00:00:07, memory = 1096.43 (MB).
    Completing 50% with 1838 violations.
    elapsed time = 00:00:08, memory = 1123.23 (MB).
    Completing 60% with 1369 violations.
    elapsed time = 00:00:10, memory = 1096.31 (MB).
    Completing 70% with 1369 violations.
    elapsed time = 00:00:12, memory = 1111.44 (MB).
    Completing 80% with 1328 violations.
    elapsed time = 00:00:14, memory = 1096.44 (MB).
    Completing 90% with 1328 violations.
    elapsed time = 00:00:17, memory = 1112.36 (MB).
    Completing 100% with 1341 violations.
    elapsed time = 00:00:20, memory = 1102.09 (MB).
[INFO DRT-0199]   Number of violations = 1377.
Viol/Layer        mcon   met1   met2
Cut Spacing          1      0      0
Metal Spacing        0    250     16
Recheck              0     36      0
Short                0   1036     38
[INFO DRT-0267] cpu time = 00:01:40, elapsed time = 00:00:20, memory = 1104.86 (MB), peak = 1210.50 (MB)
Total wire length = 285388 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 144176 um.
Total wire length on LAYER met2 = 131414 um.
Total wire length on LAYER met3 = 4772 um.
Total wire length on LAYER met4 = 5024 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 46617.
Up-via summary (total 46617):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24273
           met2      427
           met3      106
           met4        0
------------------------
                   46617


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 1377 violations.
    elapsed time = 00:00:01, memory = 1113.13 (MB).
    Completing 20% with 1377 violations.
    elapsed time = 00:00:03, memory = 1204.01 (MB).
    Completing 30% with 1085 violations.
    elapsed time = 00:00:12, memory = 1125.47 (MB).
    Completing 40% with 1085 violations.
    elapsed time = 00:00:17, memory = 1145.25 (MB).
    Completing 50% with 1085 violations.
    elapsed time = 00:00:19, memory = 1207.67 (MB).
    Completing 60% with 788 violations.
    elapsed time = 00:00:27, memory = 1111.98 (MB).
    Completing 70% with 788 violations.
    elapsed time = 00:00:33, memory = 1147.78 (MB).
    Completing 80% with 520 violations.
    elapsed time = 00:00:37, memory = 1112.10 (MB).
    Completing 90% with 520 violations.
    elapsed time = 00:00:39, memory = 1112.10 (MB).
    Completing 100% with 225 violations.
    elapsed time = 00:00:48, memory = 1129.96 (MB).
[INFO DRT-0199]   Number of violations = 225.
Viol/Layer        mcon   met1   met2
Cut Spacing          6      0      0
Metal Spacing        0    124      9
Short                0     83      3
[INFO DRT-0267] cpu time = 00:03:10, elapsed time = 00:00:48, memory = 1130.73 (MB), peak = 1220.07 (MB)
Total wire length = 285008 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 139263 um.
Total wire length on LAYER met2 = 131813 um.
Total wire length on LAYER met3 = 8895 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47440.
Up-via summary (total 47440):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24604
           met2      915
           met3      110
           met4        0
------------------------
                   47440


[INFO DRT-0195] Start 4th optimization iteration.
    Completing 10% with 225 violations.
    elapsed time = 00:00:00, memory = 1130.96 (MB).
    Completing 20% with 225 violations.
    elapsed time = 00:00:02, memory = 1113.25 (MB).
    Completing 30% with 176 violations.
    elapsed time = 00:00:07, memory = 1113.25 (MB).
    Completing 40% with 176 violations.
    elapsed time = 00:00:07, memory = 1113.25 (MB).
    Completing 50% with 176 violations.
    elapsed time = 00:00:07, memory = 1113.25 (MB).
    Completing 60% with 155 violations.
    elapsed time = 00:00:14, memory = 1113.25 (MB).
    Completing 70% with 155 violations.
    elapsed time = 00:00:14, memory = 1113.25 (MB).
    Completing 80% with 122 violations.
    elapsed time = 00:00:24, memory = 1113.25 (MB).
    Completing 90% with 122 violations.
    elapsed time = 00:00:24, memory = 1113.25 (MB).
    Completing 100% with 72 violations.
    elapsed time = 00:00:30, memory = 1113.33 (MB).
[INFO DRT-0199]   Number of violations = 72.
Viol/Layer        mcon   met1
Cut Spacing          3      0
Metal Spacing        0     46
Short                0     23
[INFO DRT-0267] cpu time = 00:01:31, elapsed time = 00:00:30, memory = 1113.33 (MB), peak = 1220.07 (MB)
Total wire length = 284967 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138871 um.
Total wire length on LAYER met2 = 131857 um.
Total wire length on LAYER met3 = 9202 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47477.
Up-via summary (total 47477):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24614
           met2      942
           met3      110
           met4        0
------------------------
                   47477


[INFO DRT-0195] Start 5th optimization iteration.
    Completing 10% with 72 violations.
    elapsed time = 00:00:00, memory = 1113.33 (MB).
    Completing 20% with 72 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 30% with 55 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 40% with 55 violations.
    elapsed time = 00:00:01, memory = 1113.37 (MB).
    Completing 50% with 55 violations.
    elapsed time = 00:00:01, memory = 1113.37 (MB).
    Completing 60% with 42 violations.
    elapsed time = 00:00:02, memory = 1113.37 (MB).
    Completing 70% with 42 violations.
    elapsed time = 00:00:02, memory = 1113.37 (MB).
    Completing 80% with 24 violations.
    elapsed time = 00:00:05, memory = 1113.37 (MB).
    Completing 90% with 24 violations.
    elapsed time = 00:00:05, memory = 1113.37 (MB).
    Completing 100% with 17 violations.
    elapsed time = 00:00:09, memory = 1113.37 (MB).
[INFO DRT-0199]   Number of violations = 17.
Viol/Layer        met1
Metal Spacing       10
Short                7
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:09, memory = 1113.37 (MB), peak = 1220.07 (MB)
Total wire length = 284977 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138786 um.
Total wire length on LAYER met2 = 131855 um.
Total wire length on LAYER met3 = 9299 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47478.
Up-via summary (total 47478):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24604
           met2      953
           met3      110
           met4        0
------------------------
                   47478


[INFO DRT-0195] Start 6th optimization iteration.
    Completing 10% with 17 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 20% with 17 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 30% with 16 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 40% with 16 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 50% with 16 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 60% with 16 violations.
    elapsed time = 00:00:03, memory = 1113.37 (MB).
    Completing 70% with 16 violations.
    elapsed time = 00:00:03, memory = 1113.37 (MB).
    Completing 80% with 12 violations.
    elapsed time = 00:00:04, memory = 1113.37 (MB).
    Completing 90% with 12 violations.
    elapsed time = 00:00:04, memory = 1113.37 (MB).
    Completing 100% with 6 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
[INFO DRT-0199]   Number of violations = 6.
Viol/Layer        met1
Metal Spacing        5
Short                1
[INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:06, memory = 1113.37 (MB), peak = 1220.07 (MB)
Total wire length = 284973 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138759 um.
Total wire length on LAYER met2 = 131865 um.
Total wire length on LAYER met3 = 9313 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47482.
Up-via summary (total 47482):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24606
           met2      955
           met3      110
           met4        0
------------------------
                   47482


[INFO DRT-0195] Start 7th optimization iteration.
    Completing 10% with 6 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 20% with 6 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 30% with 6 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 40% with 6 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 50% with 6 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 60% with 6 violations.
    elapsed time = 00:00:07, memory = 1113.37 (MB).
    Completing 70% with 6 violations.
    elapsed time = 00:00:07, memory = 1113.37 (MB).
    Completing 80% with 6 violations.
    elapsed time = 00:00:07, memory = 1113.37 (MB).
    Completing 90% with 6 violations.
    elapsed time = 00:00:07, memory = 1113.37 (MB).
    Completing 100% with 5 violations.
    elapsed time = 00:00:08, memory = 1113.37 (MB).
[INFO DRT-0199]   Number of violations = 5.
Viol/Layer        met1
Metal Spacing        4
Short                1
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:08, memory = 1113.37 (MB), peak = 1220.07 (MB)
Total wire length = 284970 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138758 um.
Total wire length on LAYER met2 = 131863 um.
Total wire length on LAYER met3 = 9313 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47482.
Up-via summary (total 47482):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24606
           met2      955
           met3      110
           met4        0
------------------------
                   47482


[INFO DRT-0195] Start 8th optimization iteration.
    Completing 10% with 5 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 20% with 5 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 30% with 5 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 40% with 5 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 50% with 5 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 60% with 5 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 70% with 5 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 80% with 5 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 90% with 5 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 100% with 5 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
[INFO DRT-0199]   Number of violations = 5.
Viol/Layer        met1
Metal Spacing        4
Short                1
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:06, memory = 1113.37 (MB), peak = 1220.07 (MB)
Total wire length = 284970 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138758 um.
Total wire length on LAYER met2 = 131863 um.
Total wire length on LAYER met3 = 9313 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47482.
Up-via summary (total 47482):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24606
           met2      955
           met3      110
           met4        0
------------------------
                   47482


[INFO DRT-0195] Start 9th optimization iteration.
    Completing 10% with 5 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 20% with 5 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 30% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 40% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 50% with 2 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 60% with 2 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 70% with 2 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 80% with 2 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 90% with 2 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
    Completing 100% with 2 violations.
    elapsed time = 00:00:06, memory = 1113.37 (MB).
[INFO DRT-0199]   Number of violations = 2.
Viol/Layer        met1
Metal Spacing        1
Short                1
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:06, memory = 1113.37 (MB), peak = 1220.07 (MB)
Total wire length = 284968 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138757 um.
Total wire length on LAYER met2 = 131861 um.
Total wire length on LAYER met3 = 9313 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47480.
Up-via summary (total 47480):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24604
           met2      955
           met3      110
           met4        0
------------------------
                   47480


[INFO DRT-0195] Start 10th optimization iteration.
    Completing 10% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 20% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 30% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 40% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 50% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 60% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 70% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 80% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 90% with 2 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 1113.37 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1113.37 (MB), peak = 1220.07 (MB)
Total wire length = 284964 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138754 um.
Total wire length on LAYER met2 = 131858 um.
Total wire length on LAYER met3 = 9315 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47483.
Up-via summary (total 47483):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24605
           met2      957
           met3      110
           met4        0
------------------------
                   47483


[INFO DRT-0198] Complete detail routing.
Total wire length = 284964 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138754 um.
Total wire length on LAYER met2 = 131858 um.
Total wire length on LAYER met3 = 9315 um.
Total wire length on LAYER met4 = 5035 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47483.
Up-via summary (total 47483):.

------------------------
 FR_MASTERSLICE        0
            li1    21811
           met1    24605
           met2      957
           met3      110
           met4        0
------------------------
                   47483


[INFO DRT-0267] cpu time = 00:10:39, elapsed time = 00:03:02, memory = 1113.37 (MB), peak = 1220.07 (MB)

[INFO DRT-0180] Post processing.
Setting global connections for newly added cells...
Writing OpenROAD database to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/results/routing/core.odb...
Writing netlist to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/results/routing/core.nl.v...
Writing powered netlist to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/results/routing/core.pnl.v...
Writing layout to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_24/results/routing/core.def...