tree 8264eeaee59b53e6cdbd3d4d7f32a455c79661a1
parent f7cd5897f1b542eb138f506c762e0d5a72828135
author Piotro <piotro888@wp.pl> 1672408171 +0100
committer Piotro <piotro888@wp.pl> 1672408171 +0100

Verilog defines and wrapper