)]}'
{
  "commit": "f227a1ef53fb01179ab90c1637e70f03a09d7cb6",
  "tree": "e6957104da0aa57672aa8b8493edebf8fac60dfe",
  "parents": [
    "631d17359785e35fd7f2dff355a4452a261122e7"
  ],
  "author": {
    "name": "McLucifer2646",
    "email": "Anshul.Madurwar@iiitb.org",
    "time": "Wed Dec 21 16:22:11 2022 +0530"
  },
  "committer": {
    "name": "McLucifer2646",
    "email": "Anshul.Madurwar@iiitb.org",
    "time": "Wed Dec 21 16:22:11 2022 +0530"
  },
  "message": "Final Commit\n",
  "tree_diff": [
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      "old_mode": 33188,
      "old_path": "verilog/rtl/user_defines.v",
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}
