design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
/home/urielcho/Proyectos_caravel/MPW8/gf180_vs_sky130/openlane/modulador,OQPSK_PS_RCOSINE2,22_12_22_16_56,flow completed,0h3m43s0ms,0h2m53s0ms,25604.938271604937,0.09,11522.222222222223,12.34,656.61,1037,0,0,0,0,0,0,0,-1,0,-1,-1,45379,9816,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,33948173.0,0.0,14.06,15.83,1.61,3.38,-1,1455,1808,86,435,0,0,0,1422,8,4,52,43,150,118,60,552,29,52,20,204,1144,0,1348,80146.8672,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,100.0,10.0,100,AREA 0,10,45,1,153.6,153.18,0.5,0.3,sky130_fd_sc_hd,4