| { |
| "DESIGN_NAME": "divider", |
| "DESIGN_IS_CORE": 0, |
| "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/divider.v"], |
| "CLOCK_PERIOD": 100, |
| "CLOCK_PORT": "clk", |
| "CLOCK_NET": "counter.clk", |
| "FP_SIZING": "absolute", |
| "DIE_AREA": "0 0 300 300", |
| "PL_BASIC_PLACEMENT": 0, |
| "VDD_NETS": ["vccd1"], |
| "GND_NETS": ["vssd1"], |
| "DIODE_INSERTION_STRATEGY": 4, |
| "RUN_CVC": 1, |
| "pdk::sky130*": { |
| "FP_CORE_UTIL": 35, |
| "RT_MAX_LAYER": "met4", |
| "scl::sky130_fd_sc_hd": { |
| "CLOCK_PERIOD": 100 |
| }, |
| "scl::sky130_fd_sc_hdll": { |
| "CLOCK_PERIOD": 10 |
| }, |
| "scl::sky130_fd_sc_hs": { |
| "CLOCK_PERIOD": 8 |
| }, |
| "scl::sky130_fd_sc_ls": { |
| "CLOCK_PERIOD": 10, |
| "SYNTH_MAX_FANOUT": 5 |
| }, |
| "scl::sky130_fd_sc_ms": { |
| "CLOCK_PERIOD": 10 |
| } |
| }, |
| "pdk::gf180mcuC": { |
| "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", |
| "CLOCK_PERIOD": 24.0, |
| "FP_CORE_UTIL": 40, |
| "RT_MAX_LAYER": "Metal4", |
| "SYNTH_MAX_FANOUT": 4, |
| "PL_TARGET_DENSITY": 0.45 |
| } |
| } |
