diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index f2cd3b4..bd4e2e4 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -49,7 +49,6 @@
     "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
     "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
     "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
-    "FP_DEF_TEMPLATE": "/home/jeffdi/caravel_user_project_gf/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def",
     "pdk::sky130*": {
         "RT_MAX_LAYER": "met4",
         "scl::sky130_fd_sc_hd": {
@@ -68,9 +67,19 @@
         "scl::sky130_fd_sc_ms": {
             "CLOCK_PERIOD": 10
         }
-    },
+     },
     "pdk::gf180mcuC": {
         "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
-        "RT_MAX_LAYER": "Metal4"
-    }
+        "FP_PDN_CHECK_NODES": 0,
+        "FP_PDN_ENABLE_RAILS": 0,
+        "RT_MAX_LAYER": "Metal4",
+        "DIE_AREA": "0 0 3000 3000",
+        "FP_PIN_ORDER_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_project_wrapper/pin_order.cfg",
+        "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
+        "DIODE_INSERTION_STRATEGY": 0,
+        "FP_PDN_CHECK_NODES": 0,
+        "MAGIC_WRITE_FULL_LEF": 0,
+        "FP_PDN_ENABLE_RAILS": 0,
+        "GLB_RT_OBS": "Metal1 0 0 ref::$DIE_AREA, Metal2 0 0 ref::$DIE_AREA, Metal3 0 0 ref::$DIE_AREA, Metal4 0 0 ref::$DIE_AREA, Metal5 0 0 ref::$DIE_AREA"
+   }
 }
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
new file mode 100644
index 0000000..c9632da
--- /dev/null
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -0,0 +1,156 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
\ No newline at end of file