)]}'
{
  "commit": "312c72b4d16004b2729f638542327064d5b7812f",
  "tree": "ea6a3270f0a1d6cc6ffb52069fe62c971643e1d7",
  "parents": [
    "294758cd2a8a470cad1a40bffd190ddbf2ba6463"
  ],
  "author": {
    "name": "root",
    "email": "root@Janani_Aravind",
    "time": "Wed Dec 28 22:30:47 2022 -0500"
  },
  "committer": {
    "name": "root",
    "email": "root@Janani_Aravind",
    "time": "Wed Dec 28 22:30:47 2022 -0500"
  },
  "message": "\tnew file:   verilog/rtl/alu_xor_4.v\n\tnew file:   verilog/rtl/macro_10.v\n\tnew file:   verilog/rtl/macro_15.v\n\tnew file:   verilog/rtl/macro_7.v\n\tnew file:   verilog/rtl/macro_decap_12.v\n\tnew file:   verilog/rtl/macro_decap_3.v\n\tnew file:   verilog/rtl/macro_golden.v\n\tnew file:   verilog/rtl/macro_nodecap.v\n\tnew file:   verilog/rtl/macro_nofill.v\n\tdef/macro_10.def\n\tdef/macro_15.def\n\tdef/macro_7.def\n\tdef/macro_decap_12.def\n\tdef/macro_decap_3.def\n\tdef/macro_golden.def\n\tdef/macro_nodecap.def\n\tdef/macro_nofill.def\n\tgds/\n\tlef/macro_10.lef\n\tlef/macro_15.lef\n\tlef/macro_7.lef\nlef/macro_decap_12.lef\n\tlef/macro_decap_3.lef\n\tlef/macro_golden.lef\n\tlef/macro_nodecap.lef\n\tlef/macro_nofill.lef\n\tlib/\n\tmag/macro_10.mag\n\tmag/macro_15.mag\n\tmag/macro_7.mag\n\tmag/macro_decap_12.mag\n\tmag/macro_decap_3.mag\n\tmag/macro_golden.mag\n\tmag/macro_nodecap.mag\n\tmag/macro_nofill.mag\n\tmaglef/macro_10.mag\n\tmaglef/macro_15.mag\n\tmaglef/macro_7.mag\n\tmaglef/macro_decap_12.mag\n\tmaglef/macro_decap_3.mag\n\tmaglef/macro_golden.mag\n\tmaglef/macro_nodecap.mag\n\tmaglef/macro_nofill.mag\n\topenlane/user_proj_example/config_15.json\n\topenlane/user_proj_example/config_7.json\n\topenlane/user_proj_example/config_decap_12.json\nopenlane/user_proj_example/config_decap_3\n\topenlane/user_proj_example/config_golden.json\n\topenlane/user_proj_example/config_nodecap.json\n\topenlane/user_proj_example/config_nofill.json\n\topenlane/user_project_wrapper/macro_1.cfg\n\tsdc/\n\tsdf/\n\tsignoff/user_proj_example/metrics.csv\n\tsignoff/user_project_wrapper/metrics.csv\n\tspef/\n\tspi/lvs/macro_10.spice\n\tspi/lvs/macro_15.spice\n\tspi/lvs/macro_7.spice\n\tspi/lvs/macro_decap_12.spice\n\tspi/lvs/macro_decap_3.spice\n\tspi/lvs/macro_golden.spice\n\tspi/lvs/macro_nodecap.spice\n\tspi/lvs/macro_nofill.spice\n\tverilog/dv/macro_10/\n\tverilog/dv/macro_15/\n\tverilog/dv/macro_7/\nverilog/dv/macro_decap12/\n\tverilog/dv/macro_decap3/\nverilog/dv/macro_golden/\nverilog/dv/macro_no_decap/\n\tverilog/dv/macro_no_fill/\n\tverilog/gl/macro_10.nl.v\n\tverilog/gl/macro_10.v\n\tverilog/gl/macro_15.nl.v\n\tverilog/gl/macro_15.v\n\tverilog/gl/macro_7.nl.v\n\tverilog/gl/macro_7.v\n\tverilog/gl/macro_decap_12.nl.v\n\tverilog/gl/macro_decap_12.v\n\tverilog/gl/macro_decap_3.nl.v\n\tverilog/gl/macro_decap_3.v\n\tverilog/gl/macro_golden.nl.v\n\tverilog/gl/macro_golden.v\n\tverilog/gl/macro_nodecap.nl.v\n\tverilog/gl/macro_nodecap.v\n\tverilog/gl/macro_nofill.nl.v\n\tverilog/gl/macro_nofill.v\n\tverilog/gl/user_project_wrapper.nl.v\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "13ceea9fb98b3c77f21785383456dbe11bf4d9b8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/1"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "aacb883a9f33629492ce8ef801c9e95adc5052c9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/alu_xor_4.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "13ceea9fb98b3c77f21785383456dbe11bf4d9b8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_10.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9f1b0927864a22beab5aca90cef07c5d0f227a52",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_15.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5a82508770b7702158a25c10e6c3ea6d51908ca7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_7.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2d53befce7727adbffedb89bca7896d0072dd93f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_decap_12.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3545c4ea71b4063170e763e842c7dc87c6f09394",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_decap_3.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1f3968990508087b190f854a43ed73448fa3ac78",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_golden.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "08d655940c6c7ee1ebf88caee68b6bdb722f3efe",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_nodecap.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5e994df2b6c0a82d6519d78171edf7ee9ce88ee6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/macro_nofill.v"
    }
  ]
}