)]}'
{
  "commit": "340cc4a6a8be1caf0eac97c099105ec9f9ed8165",
  "tree": "3b528e04ed72977ee20da0b2c8d6060e66f78436",
  "parents": [
    "e364bd5664d3a09312d79ff7a77798a7ed7fc218"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Tue Apr 20 18:28:22 2021 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Tue Apr 20 18:28:22 2021 +0200"
  },
  "message": "Update full chip simulation to run from root\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "43e7db2b63a87a2a753837c69b5bc8195d767b5a",
      "old_mode": 33188,
      "old_path": "Makefile",
      "new_id": "16104a7f02c787dcae896f78561f512cd5a0e2e8",
      "new_mode": 33188,
      "new_path": "Makefile"
    },
    {
      "type": "modify",
      "old_id": "3b7c1f9d785161c24518b4f4cdba4f03ecf9b8bd",
      "old_mode": 33188,
      "old_path": "README.md",
      "new_id": "4215dee92d7ea4441d40d92208ade60c5d936279",
      "new_mode": 33188,
      "new_path": "README.md"
    },
    {
      "type": "modify",
      "old_id": "02393a2ffd5676ce7c16fcba89e668f94d58f21f",
      "old_mode": 57344,
      "old_path": "caravel",
      "new_id": "7a8e96cfad2222d46e02c777a97761e70824813a",
      "new_mode": 57344,
      "new_path": "caravel"
    },
    {
      "type": "modify",
      "old_id": "73d7868181b1f4d0576e7c4ddee50ca2e372b0e3",
      "old_mode": 33188,
      "old_path": "verilog/dv/Makefile",
      "new_id": "d87238f0e5affdad2cdf0f2208e94beef2bb33bc",
      "new_mode": 33188,
      "new_path": "verilog/dv/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c3a5e54a3e72d94303008d03e71fbb0a099cc7b9",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/Makefile",
      "new_id": "0ef079e9ab375323e3f5ba46c8d6ce80b556d4ad",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/Makefile"
    },
    {
      "type": "modify",
      "old_id": "adae20d44a97ba79d61ccbe36d7b1f1a736d97fa",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/Makefile",
      "new_id": "b23075de0ea71a02ce0af7ca5dbcad04894dcf56",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "6ba368fb7a870c3e84bef7bfcae6fce50a563b93",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/Makefile",
      "new_id": "14e48fc793df3d613a0ab55c5fcb39364f21fab8",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c9a6ca75000bb67bb1f112f095eebdb5e7882869",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/Makefile",
      "new_id": "304d32c25753e2fb676516fc085843bb64d5f9cb",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/Makefile"
    },
    {
      "type": "modify",
      "old_id": "70ad01fd17084868a04d4e61919f3a9de781c162",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "132a1ccbbbb13c7249232e0af9f90d6469d5040f",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_port/Makefile"
    }
  ]
}