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      "message": "EF-3367 - update make and ci precheck commands to use pdk_path argument instead of pdk_root\n"
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      },
      "committer": {
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        "time": "Thu Apr 07 08:17:48 2022 -0700"
      },
      "message": "use pdk-with-volare\n"
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    {
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      "message": "Merge pull request #19 from efabless/jeffdi-patch-1\n\nFix tag to mpw-5c"
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        "time": "Sat Mar 19 11:06:20 2022 -0700"
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      },
      "message": "Merge pull request #18 from efabless/EFIC-233\n\nEFIC-233"
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        "time": "Tue Feb 08 16:15:27 2022 +0200"
      },
      "message": "EFIC-233 - Update CI\n"
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      "message": "Merge pull request #17 from efabless/ol_fix\n\nUpdate Caravel to `mpw-5a`"
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        "time": "Thu Feb 03 20:29:50 2022 +0200"
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      "message": "Update index.rst"
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    {
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      "message": "Update Caravel to `mpw-5a`\n\nAlso remove `make pdk-nonnative`.\n"
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        "time": "Fri Jan 28 12:40:31 2022 -0800"
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        "time": "Fri Jan 28 12:40:31 2022 -0800"
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      "message": "Merge pull request #16 from efabless/EFIC-232\n\nEFIC-232 - Makefile Updates"
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        "time": "Fri Jan 28 19:56:44 2022 +0200"
      },
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      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
      },
      "message": "Modified the xschem schematics so that the wrapper level correctly\nrepresents the metal resistors that were added to the layout to\nmaintain all the pins on isolated nets.  The LVS with the xschem\nnetlist is now correct with the modified layout.  The verilog\nnetlist has not yet been updated.\n"
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    {
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      },
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        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat Dec 18 10:44:16 2021 -0500"
      },
      "message": "Updated the layout to properly use the metal resistors in front of\npins that are connected to the same net.  Updated the GDS with this\nchange, and also to properly generate hierarchical layers, which\napparently had not been done previously.  Verilog and schematic\nhave not yet been updated with the metal resistor change, and so\nwill fail LVS until they are.\n"
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        "time": "Fri Dec 17 13:40:01 2021 -0800"
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        "time": "Fri Dec 17 13:38:25 2021 -0800"
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        "time": "Fri Dec 17 13:38:25 2021 -0800"
      },
      "message": "Merge pull request #13 from efabless/caravel_openframe\n\nremove submodule"
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        "time": "Fri Dec 17 13:36:23 2021 -0800"
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      "committer": {
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        "time": "Fri Dec 17 13:36:23 2021 -0800"
      },
      "message": "Update user_project_ci.yml"
    },
    {
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        "time": "Fri Dec 17 13:35:46 2021 -0800"
      },
      "committer": {
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        "email": "noreply@github.com",
        "time": "Fri Dec 17 13:35:46 2021 -0800"
      },
      "message": "Update caravan_build.yml"
    },
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        "time": "Mon Sep 20 12:18:14 2021 +0200"
      },
      "message": "Update include netlists\n"
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        "time": "Mon Sep 20 11:30:12 2021 +0200"
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      "message": "Update README\n"
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      },
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        "time": "Mon Sep 20 11:20:34 2021 +0200"
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      "message": "[CI] Update scripts\n"
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        "time": "Thu Sep 16 23:19:48 2021 -0700"
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      "message": "Merge pull request #4 from Manarabdelaty/update_makefile\n\nUpdate Makefile to work with latest precheck"
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      },
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        "time": "Thu Sep 16 23:18:08 2021 +0200"
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      "message": "Update Makefile to work with latest precheck\n"
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