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# Created by write_sdc
# Sat Dec 24 06:37:19 2022
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current_design wb_interconnect
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# Timing Constraints
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create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
set_clock_transition 0.1500 [get_clocks {clk_i}]
set_clock_uncertainty -setup 0.5000 clk_i
set_clock_uncertainty -hold 0.2500 clk_i
set_propagated_clock [get_clocks {clk_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_sel_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_sel_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_sel_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_sel_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_sel_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_sel_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_sel_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_sel_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_stb_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_stb_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_we_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_we_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_sel_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_sel_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_sel_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_sel_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_sel_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_sel_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_sel_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_sel_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_stb_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_stb_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_we_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_we_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_sel_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_sel_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_sel_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_sel_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_sel_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_sel_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_sel_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_sel_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_stb_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_stb_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_we_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_we_i}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -max -add_delay [get_ports {rst_n}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -max -add_delay [get_ports {rst_n}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_ack_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_ack_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_ack_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_ack_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_ack_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_ack_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[9]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_ack_i}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_ack_i}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[0]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[0]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[10]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[10]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[11]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[11]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[12]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[12]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[13]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[13]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[14]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[14]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[15]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[15]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[16]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[16]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[17]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[17]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[18]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[18]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[19]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[19]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[1]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[1]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[20]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[20]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[21]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[21]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[22]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[22]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[23]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[23]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[24]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[24]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[25]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[25]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[26]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[26]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[27]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[27]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[28]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[28]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[29]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[29]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[2]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[2]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[30]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[30]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[31]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[31]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[3]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[3]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[4]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[4]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[5]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[5]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[6]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[6]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[7]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[7]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[8]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[8]}]
set_input_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_i[9]}]
set_input_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_i[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_ack_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_ack_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[15]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[16]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[17]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[18]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[19]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[20]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[21]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[22]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[23]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[24]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[25]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[26]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[27]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[28]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[29]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[30]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[31]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_err_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_err_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_ack_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_ack_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[15]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[16]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[17]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[18]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[19]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[20]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[21]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[22]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[23]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[24]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[25]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[26]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[27]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[28]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[29]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[30]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[31]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_err_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_err_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_ack_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_ack_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[15]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[16]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[17]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[18]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[19]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[20]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[21]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[22]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[23]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[24]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[25]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[26]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[27]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[28]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[29]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[30]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[31]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_err_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_err_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_cyc_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_cyc_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[15]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[16]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[17]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[18]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[19]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[20]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[21]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[22]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[23]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[24]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[25]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[26]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[27]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[28]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[29]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[30]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[31]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_we_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_we_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_cyc_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_cyc_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[15]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[16]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[17]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[18]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[19]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[20]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[21]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[22]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[23]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[24]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[25]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[26]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[27]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[28]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[29]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[30]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[31]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_we_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_we_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_cyc_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_cyc_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[15]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[16]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[17]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[18]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[19]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[20]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[21]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[22]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[23]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[24]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[25]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[26]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[27]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[28]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[29]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[30]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[31]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_we_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_we_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_adr_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_adr_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_cyc_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_cyc_o}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[10]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[11]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[12]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[13]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[14]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[15]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[16]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[17]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[18]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[19]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[20]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[21]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[22]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[23]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[24]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[25]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[26]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[27]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[28]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[29]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[30]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[31]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[4]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[5]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[6]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[7]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[8]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_dat_o[9]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_sel_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_sel_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_sel_o[1]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_sel_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_sel_o[2]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_sel_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_sel_o[3]}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_sel_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s3_wbd_we_o}]
set_output_delay 6.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s3_wbd_we_o}]
set_max_delay\
    -from [get_ports {wbd_clk_int}] 3.5000
set_false_path\
    -from [list [get_ports {cfg_cska_wi[0]}]\
           [get_ports {cfg_cska_wi[1]}]\
           [get_ports {cfg_cska_wi[2]}]\
           [get_ports {cfg_cska_wi[3]}]]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_ack_o}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_err_o}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_ack_o}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_err_o}]
set_load -pin_load 0.0334 [get_ports {mac_rx_qcnt_dec}]
set_load -pin_load 0.0334 [get_ports {mac_rx_qcnt_inc}]
set_load -pin_load 0.0334 [get_ports {mac_tx_qcnt_dec}]
set_load -pin_load 0.0334 [get_ports {mac_tx_qcnt_inc}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bry_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bry_o}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_cyc_o}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {scan_en_o}]
set_load -pin_load 0.0334 [get_ports {scan_mode_o}]
set_load -pin_load 0.0334 [get_ports {wbd_clk_skew}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[3]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[2]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[1]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[0]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[7]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[6]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[5]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[4]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[3]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[2]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[1]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[0]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[3]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[2]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[1]}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[0]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[12]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[11]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[10]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[9]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[8]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[7]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[6]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[5]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[4]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[3]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[2]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[1]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[0]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[3]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[14]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[13]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[12]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[11]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[10]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[9]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[8]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[6]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[5]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[4]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[3]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[2]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[1]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[0]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[9]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[8]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[7]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[6]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[5]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[4]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[3]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[2]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[1]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_bl_o[0]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[3]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[2]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[1]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[0]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[14]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[13]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[12]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[11]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[10]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[9]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[8]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[7]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[6]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[5]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[4]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[3]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[2]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[1]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[0]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[9]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[8]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[7]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[6]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[5]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[4]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[3]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[2]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[1]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_bl_o[0]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[3]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[2]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[1]}]
set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[0]}]
set_load -pin_load 0.0334 [get_ports {scan_so[7]}]
set_load -pin_load 0.0334 [get_ports {scan_so[6]}]
set_load -pin_load 0.0334 [get_ports {scan_so[5]}]
set_load -pin_load 0.0334 [get_ports {scan_so[4]}]
set_load -pin_load 0.0334 [get_ports {scan_so[3]}]
set_load -pin_load 0.0334 [get_ports {scan_so[2]}]
set_load -pin_load 0.0334 [get_ports {scan_so[1]}]
set_load -pin_load 0.0334 [get_ports {scan_so[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_en}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_mode}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qbase_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qbase_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[0]}]
set_case_analysis 0 [get_ports {cfg_cska_wi[0]}]
set_case_analysis 0 [get_ports {cfg_cska_wi[1]}]
set_case_analysis 0 [get_ports {cfg_cska_wi[2]}]
set_case_analysis 0 [get_ports {cfg_cska_wi[3]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 10.0000 [current_design]