)]}'
{
  "commit": "cb245fe9f3a9780458e15ea93c9a22ac5265aab2",
  "tree": "6c7c06c920bc2d2df248794a89e646714f062a65",
  "parents": [
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  ],
  "author": {
    "name": "mole99",
    "email": "leomoser99@gmail.com",
    "time": "Mon Dec 12 11:27:21 2022 +0100"
  },
  "committer": {
    "name": "mole99",
    "email": "leomoser99@gmail.com",
    "time": "Mon Dec 12 11:27:21 2022 +0100"
  },
  "message": "Add submodule\n",
  "tree_diff": [
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7fa816d426a97aab1874293f8dc4c9393bd5dbcf",
      "new_mode": 33188,
      "new_path": ".gitmodules"
    },
    {
      "type": "add",
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "28cec1753d7f99b702b8869a70b130cac502e77e",
      "new_mode": 57344,
      "new_path": "verilog/rtl/leorv-fpga"
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}
