diff --git a/README.md b/README.md
index 34b9a05..7a32576 100644
--- a/README.md
+++ b/README.md
@@ -1,12 +1,25 @@
-# Caravel User Project
+# LeoSoC
 
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
 
-| :exclamation: Important Note            |
-|-----------------------------------------|
+This is a simple SoC with the following:
 
-## Please fill in your project documentation in this README.md file 
+- 1 LeoRV32 Core (RV32I)
+- 8 kB Work RAM
+- 8 kB Video RAM (can also be used as Work RAM)
+- SVGA Core (800 x 600, 40 MHz)
+	- Resolution decreased to 100 x 75 pixel
+	- 1 Byte per Pixel with direct color format (BBGGGRRR)
+- UART
+	- 9600 baud fixed at 40 MHz
+- Blink
+	- Simple output to blink an LED
 
-Refer to [README](docs/source/index.rst#section-quickstart) for a quickstart of how to use caravel_user_project
+## Address Layout
 
-Refer to [README](docs/source/index.rst) for this sample project documentation. 
+| Peripheral | Address  |
+|------------|----------|
+| WRAM_BASE  | 0x000000 |
+| VRAM_BASE  | 0x010000 |
+| UART_BASE  | 0x0A0000 |
+| BLINK_BASE | 0x0F0000 |
\ No newline at end of file