diff --git a/verilog/rtl/leorv-fpga/LICENSE b/verilog/rtl/leorv-fpga/LICENSE
new file mode 100644
index 0000000..d41c0bd
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/LICENSE
@@ -0,0 +1,232 @@
+GNU GENERAL PUBLIC LICENSE
+Version 3, 29 June 2007
+
+Copyright © 2007 Free Software Foundation, Inc. <http://fsf.org/>
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+END OF TERMS AND CONDITIONS
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+How to Apply These Terms to Your New Programs
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+If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
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+     <program>  Copyright (C) <year>  <name of author>
+     This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
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+The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”.
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diff --git a/verilog/rtl/leorv-fpga/Makefile b/verilog/rtl/leorv-fpga/Makefile
new file mode 100644
index 0000000..58f948c
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/Makefile
@@ -0,0 +1,160 @@
+default: build
+
+BOARD ?= icebreaker
+TOOLCHAIN_PREFIX ?= riscv32-unknown-elf-
+PYTHON ?= python3
+
+FIRMWARE_OBJS = firmware/start.o firmware/main.o
+GCC_WARNS  = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
+GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
+
+# Sources
+RTL = $(wildcard leorv32/rtl/*.sv) $(wildcard soc/rtl/*.sv) $(wildcard uart/rtl/*.sv) $(wildcard util/rtl/*.sv) $(wildcard svga/rtl/*.sv) $(wildcard sram/rtl/*.sv)
+TB = $(wildcard soc/tb/*.sv)
+
+# --- Generic Targets ---
+
+sim: sim-${BOARD}
+
+view: view-${BOARD}
+
+synth: synth-${BOARD}
+
+build: build-${BOARD}
+
+upload: upload-${BOARD}
+
+# --- iCEBreaker ---
+
+sim-icebreaker.vvp: $(RTL) $(TB) firmware/firmware.hex
+	iverilog -Wall -o $@ -g2012 $(RTL) $(TB) -s icebreaker_top_tb `yosys-config --datdir/ice40/cells_sim.v`
+
+sim-icebreaker: sim-icebreaker.vvp
+	vvp $^ -fst
+	
+view-icebreaker:
+	gtkwave icebreaker_top_tb.fst --save gtkwave/save_icebreaker.gtkw
+
+synth-icebreaker: icebreaker.json
+
+build-icebreaker: icebreaker.bit
+
+upload-icebreaker: icebreaker.bit
+	iceprog icebreaker.bit
+
+icebreaker.json: $(RTL) firmware/firmware.hex
+	yosys -l $(basename $@)-yosys.log -DSYNTHESIS -p 'synth_ice40 -top icebreaker_top -json $@' $(RTL)
+
+icebreaker.asc: icebreaker.json
+	nextpnr-ice40 --up5k --json $< \
+		--pcf constraints/icebreaker.pcf \
+		--package sg48 \
+		--asc $@
+
+icebreaker.bit: icebreaker.asc
+	icepack $< $@
+
+# --- svga ---
+
+sim-svga.vvp: $(RTL) svga/tb/svga_gen_top_tb.sv
+	iverilog -Wall -o $@ -g2012 $^ -s svga_gen_top_tb
+
+sim-svga: sim-svga.vvp
+	vvp $^ -fst
+
+view-svga:
+	gtkwave svga.fst --save gtkwave/save_svga.gtkw
+
+synth-svga: svga.json
+
+build-svga: svga.bit
+
+upload-svga: svga.bit
+	iceprog svga.bit
+
+svga.json: svga/rtl/svga_gen.sv svga/rtl/svga_gen_top.sv
+	yosys -l $(basename $@)-yosys.log -DSYNTHESIS -p 'synth_ice40 -top svga_gen_top -json $@' $(RTL)
+
+svga.asc: svga.json
+	nextpnr-ice40 --up5k --json $< \
+		--pcf constraints/icebreaker.pcf \
+		--package sg48 \
+		--asc $@
+
+svga.bit: svga.asc
+	icepack $< $@
+
+# --- ULX3S ---
+
+sim-ulx3s.vvp: $(RTL) $(TB) firmware/firmware.hex
+	iverilog -Wall -o $@ -g2012 $(RTL) $(TB) -s ulx3s_top_tb `yosys-config --datdir/ecp5/cells_sim.v`
+
+sim-ulx3s: sim-ulx3s.vvp
+	vvp $^ -fst
+	
+view-ulx3s:
+	gtkwave ulx3s_top_tb.fst --save gtkwave/save_ulx3s.gtkw
+
+synth-ulx3s: ulx3s.json
+
+build-ulx3s: ulx3s.bit
+
+upload-ulx3s: ulx3s.bit
+	openFPGALoader --board=ulx3s ulx3s.bit
+
+ulx3s.json: $(RTL) firmware/firmware.hex
+	yosys -l $(basename $@)-yosys.log -DSYNTHESIS -p 'synth_ecp5 -top ulx3s_top -json $@' $(RTL)
+
+ulx3s.config: ulx3s.json
+	nextpnr-ecp5 --85k --json $< \
+		--lpf constraints/ulx3s_v20.lpf \
+		--package CABGA381 \
+		--textcfg $@
+
+ulx3s.bit: ulx3s.config
+	ecppack $< $@
+
+# --- Firmware ---
+
+firmware/%.o: firmware/%.c
+	$(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32i -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
+
+firmware/start.o: firmware/start.S
+	$(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32i -o $@ $<
+
+firmware/${BOARD}_sections.lds: firmware/sections.lds
+	$(TOOLCHAIN_PREFIX)gcc -E -x c -DBOARD=${BOARD} -o $@ $^
+
+firmware/firmware.elf: $(FIRMWARE_OBJS) firmware/${BOARD}_sections.lds
+	$(TOOLCHAIN_PREFIX)gcc  -Os -mabi=ilp32 -march=rv32i -ffreestanding -nostdlib -o $@ \
+		-Wl,--build-id=none,-Bstatic,-T,firmware/${BOARD}_sections.lds,-Map,firmware/firmware.map,--strip-debug \
+		$(FIRMWARE_OBJS) -lgcc
+
+firmware/firmware.bin: firmware/firmware.elf
+	$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
+
+firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
+	$(PYTHON) firmware/makehex.py $< 2048 > $@
+
+# --- General ---
+
+.PHONY: clean sim view synth build upload \
+        sim-icebreaker view-icebreaker synth-icebreaker build-icebreaker upload-icebreaker \
+        sim-ulx3s view-ulx3s synth-ulx3s build-ulx3s upload-ulx3s
+
+clean:
+	rm -f *.vvp *.fst *.vcd *.log *.json *.asc *.bin *.bit firmware/*.o firmware/*.elf firmware/*.bin firmware/*.hex firmware/firmware.map
+
+# --- Linting ---
+
+lint:
+	verible-verilog-lint $(RTL) $(TB) --rules=-unpacked-dimensions-range-ordering
+
+lint-autofix:
+	verible-verilog-lint $(RTL) $(TB) --autofix inplace-interactive --rules=-unpacked-dimensions-range-ordering 
+
+format:
+	verible-verilog-format --indentation_spaces 4 --module_net_variable_alignment=preserve --case_items_alignment=preserve $(RTL) --inplace --verbose
+
+check-license:
+	find . -type f -name "*.sv" -exec head -n 1 {} \;
diff --git a/verilog/rtl/leorv-fpga/README.md b/verilog/rtl/leorv-fpga/README.md
new file mode 100644
index 0000000..1f9065b
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/README.md
@@ -0,0 +1,35 @@
+# LeoRV32 FPGA
+
+This repository contains FPGA examples for LeoRV32.
+
+# Setup
+
+You need to have a RISC-V toolchain in your `PATH` variable.
+
+Next, setup `TOOLCHAIN_PREFIX` accordingly, for example:
+
+	export TOOLCHAIN_PREFIX=riscv32-unknown-elf-
+
+# Supported Boards
+
+    - icebreaker
+    - ulx3s
+
+# Usage
+
+First, export the board for which to generate the bitstream:
+
+	export BOARD=icebreaker
+
+To run a simulation and view it:
+
+	make sim
+	make view
+
+The following commands are used to synthesize the design, perform place and route and upload the design to the FPGA board.
+
+	make synth
+	make build
+	make upload
+
+After that, the green LED on your iCEBreaker should blink (you may need to reset it first).
diff --git a/verilog/rtl/leorv-fpga/constraints/icebreaker.pcf b/verilog/rtl/leorv-fpga/constraints/icebreaker.pcf
new file mode 100644
index 0000000..fb930d9
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/constraints/icebreaker.pcf
@@ -0,0 +1,83 @@
+# 12 MHz clock
+set_frequency  CLK        12
+set_io         CLK        35
+
+# RS232
+set_io -nowarn RX          6
+set_io -nowarn TX          9
+
+# LEDs and Button
+set_io -nowarn BTN_N      10
+set_io -nowarn LEDR_N     11
+set_io -nowarn LEDG_N     37
+
+# RGB LED Driver
+set_io -nowarn LED_RED_N  39
+set_io -nowarn LED_GRN_N  40
+set_io -nowarn LED_BLU_N  41
+
+# SPI Flash
+set_io -nowarn FLASH_SCK  15
+set_io -nowarn FLASH_SSB  16
+set_io -nowarn FLASH_IO0  14
+set_io -nowarn FLASH_IO1  17
+set_io -nowarn FLASH_IO2  12
+set_io -nowarn FLASH_IO3  13
+
+# PMOD 1A
+set_io -nowarn P1A1        4
+set_io -nowarn P1A2        2
+set_io -nowarn P1A3       47
+set_io -nowarn P1A4       45
+set_io -nowarn P1A7        3
+set_io -nowarn P1A8       48
+set_io -nowarn P1A9       46
+set_io -nowarn P1A10      44
+
+# PMOD 1B
+set_io -nowarn P1B1       43
+set_io -nowarn P1B2       38
+set_io -nowarn P1B3       34
+set_io -nowarn P1B4       31
+set_io -nowarn P1B7       42
+set_io -nowarn P1B8       36
+set_io -nowarn P1B9       32
+set_io -nowarn P1B10      28
+
+# PMOD 2
+set_io -nowarn P2_1       27
+set_io -nowarn P2_2       25
+set_io -nowarn P2_3       21
+set_io -nowarn P2_4       19
+set_io -nowarn P2_7       26
+set_io -nowarn P2_8       23
+set_io -nowarn P2_9       20
+set_io -nowarn P2_10      18
+
+# LEDs and Buttons (PMOD 2)
+set_io -nowarn LED1       27
+set_io -nowarn LED2       25
+set_io -nowarn LED3       21
+set_io -nowarn BTN2       19
+set_io -nowarn LED5       26
+set_io -nowarn LED4       23
+set_io -nowarn BTN1       20
+set_io -nowarn BTN3       18
+
+## 12-bit DVI Pmod on Pmod 1A/1B
+set_io -nowarn dvi_clk      38
+set_io -nowarn dvi_hsync    31
+set_io -nowarn dvi_vsync    28
+set_io -nowarn dvi_de       32
+set_io -nowarn dvi_r[0]     48
+set_io -nowarn dvi_r[1]      2
+set_io -nowarn dvi_r[2]      3
+set_io -nowarn dvi_r[3]      4
+set_io -nowarn dvi_g[0]     44
+set_io -nowarn dvi_g[1]     45
+set_io -nowarn dvi_g[2]     46
+set_io -nowarn dvi_g[3]     47
+set_io -nowarn dvi_b[0]     34
+set_io -nowarn dvi_b[1]     36
+set_io -nowarn dvi_b[2]     42
+set_io -nowarn dvi_b[3]     43
diff --git a/verilog/rtl/leorv-fpga/constraints/ulx3s_v20.lpf b/verilog/rtl/leorv-fpga/constraints/ulx3s_v20.lpf
new file mode 100644
index 0000000..63db005
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/constraints/ulx3s_v20.lpf
@@ -0,0 +1,455 @@
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
+## ULX3S v2.0 and v2.1
+
+# The clock "usb" and "gpdi" sheet
+LOCATE COMP "clk_25mhz" SITE "G2";
+IOBUF  PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk_25mhz" 25 MHZ;
+
+# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
+# write to FLASH possible any time from JTAG:
+SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
+# write to FLASH possible from user bitstream, not possible form JTAG:
+# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
+
+## USBSERIAL FTDI-FPGA serial port "usb" sheet
+LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi
+LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi
+LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives
+LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives
+LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives
+IOBUF  PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF  PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF  PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF  PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+## LED indicators "blinkey" and "gpio" sheet
+LOCATE COMP "led[7]" SITE "H3";
+LOCATE COMP "led[6]" SITE "E1";
+LOCATE COMP "led[5]" SITE "E2";
+LOCATE COMP "led[4]" SITE "D1";
+LOCATE COMP "led[3]" SITE "D2";
+LOCATE COMP "led[2]" SITE "C1";
+LOCATE COMP "led[1]" SITE "C2";
+LOCATE COMP "led[0]" SITE "B2";
+IOBUF  PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet
+LOCATE COMP "btn[0]" SITE "D6";  # BTN_PWRn (inverted logic)
+LOCATE COMP "btn[1]" SITE "R1";  # FIRE1
+LOCATE COMP "btn[2]" SITE "T1";  # FIRE2
+LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18
+LOCATE COMP "btn[4]" SITE "V1";  # DOWN
+LOCATE COMP "btn[5]" SITE "U1";  # LEFT
+LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16
+IOBUF  PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+
+## DIP switch "blinkey", "gpio" sheet
+LOCATE COMP "sw[0]" SITE "E8"; # SW1
+LOCATE COMP "sw[1]" SITE "D8"; # SW2
+LOCATE COMP "sw[2]" SITE "D7"; # SW3
+LOCATE COMP "sw[3]" SITE "E7"; # SW4
+IOBUF  PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet
+LOCATE COMP "oled_clk" SITE "P4";
+LOCATE COMP "oled_mosi" SITE "P3";
+LOCATE COMP "oled_dc" SITE "P1";
+LOCATE COMP "oled_resn" SITE "P2";
+LOCATE COMP "oled_csn" SITE "N2";
+IOBUF  PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SPI Flash chip "flash" sheet
+LOCATE COMP "flash_csn" SITE "R2";
+LOCATE COMP "flash_mosi" SITE "W2";
+LOCATE COMP "flash_miso" SITE "V2";
+LOCATE COMP "flash_holdn" SITE "W1";
+LOCATE COMP "flash_wpn" SITE "Y2";
+#LOCATE COMP "flash_clk" SITE "U3";
+#LOCATE COMP "flash_csspin" SITE "AJ3";
+#LOCATE COMP "flash_initn" SITE "AG4";
+#LOCATE COMP "flash_done" SITE "AJ4";
+#LOCATE COMP "flash_programn" SITE "AH4";
+#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
+#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
+#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
+IOBUF  PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SD card "sdcard", "usb" sheet
+LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14
+LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15
+LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2
+LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4
+LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12
+LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13
+LOCATE COMP "sd_wp" SITE "P5"; # not connected
+LOCATE COMP "sd_cdn" SITE "N5"; # not connected
+IOBUF  PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement
+IOBUF  PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## ADC SPI (MAX11123) "analog", "ram" sheet
+LOCATE COMP "adc_csn" SITE "R17";
+LOCATE COMP "adc_mosi" SITE "R16";
+LOCATE COMP "adc_miso" SITE "U16";
+LOCATE COMP "adc_sclk" SITE "P17";
+IOBUF  PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Audio 4-bit DAC "analog", "gpio" sheet
+# 4-bit mode can drive down to 75 ohm load impedance.
+# Lower impedance leads to IO overload, 
+# FPGA will stop working and need reboot.
+# For standard 17 ohm earphones:
+# use bits 2,3 as input (High-Z) and drive only bits 0,1.
+LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio)
+LOCATE COMP "audio_l[2]" SITE "C3";
+LOCATE COMP "audio_l[1]" SITE "D3";
+LOCATE COMP "audio_l[0]" SITE "E4";
+LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio)
+LOCATE COMP "audio_r[2]" SITE "D5";
+LOCATE COMP "audio_r[1]" SITE "B5";
+LOCATE COMP "audio_r[0]" SITE "A3";
+LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio)
+LOCATE COMP "audio_v[2]" SITE "F5";
+LOCATE COMP "audio_v[1]" SITE "F2";
+LOCATE COMP "audio_v[0]" SITE "H5";
+IOBUF  PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## WiFi ESP-32 "wifi", "usb", "flash" sheet
+# other pins are shared with GP/GN, SD card and JTAG
+LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi
+LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi
+LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi
+LOCATE COMP "wifi_gpio0" SITE "L2";
+LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED
+LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX
+LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX
+# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active
+IOBUF  PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+# IOBUF  PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## PCB antenna 433 MHz (may be also used for FM) "usb" sheet
+LOCATE COMP "ant_433mhz" SITE "G1";
+IOBUF  PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
+LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only
+LOCATE COMP "usb_fpga_dn" SITE "F16";
+IOBUF  PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF  PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional
+LOCATE COMP "usb_fpga_bd_dn" SITE "E15";
+IOBUF  PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF  PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4;
+LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control
+LOCATE COMP "usb_fpga_pu_dn" SITE "C12";
+IOBUF  PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF  PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+
+## JTAG ESP-32 "usb" sheet
+# connected to FT231X and ESP-32
+# commented out because those are dedicated pins, not directly useable as GPIO
+# but could be used by some vendor-specific JTAG bridging (boundary scan) module
+#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI   FPGA receives
+#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS  FPGA transmits
+#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR  FPGA receives
+#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD  FPGA receives
+#IOBUF  PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SDRAM "ram" sheet
+LOCATE COMP "sdram_clk" SITE "F19";
+LOCATE COMP "sdram_cke" SITE "F20";
+LOCATE COMP "sdram_csn" SITE "P20";
+LOCATE COMP "sdram_wen" SITE "T20";
+LOCATE COMP "sdram_rasn" SITE "R20";
+LOCATE COMP "sdram_casn" SITE "T19";
+LOCATE COMP "sdram_a[0]" SITE "M20";
+LOCATE COMP "sdram_a[1]" SITE "M19";
+LOCATE COMP "sdram_a[2]" SITE "L20";
+LOCATE COMP "sdram_a[3]" SITE "L19";
+LOCATE COMP "sdram_a[4]" SITE "K20";
+LOCATE COMP "sdram_a[5]" SITE "K19";
+LOCATE COMP "sdram_a[6]" SITE "K18";
+LOCATE COMP "sdram_a[7]" SITE "J20";
+LOCATE COMP "sdram_a[8]" SITE "J19";
+LOCATE COMP "sdram_a[9]" SITE "H20";
+LOCATE COMP "sdram_a[10]" SITE "N19";
+LOCATE COMP "sdram_a[11]" SITE "G20";
+LOCATE COMP "sdram_a[12]" SITE "G19";
+LOCATE COMP "sdram_ba[0]" SITE "P19";
+LOCATE COMP "sdram_ba[1]" SITE "N20";
+LOCATE COMP "sdram_dqm[0]" SITE "U19";
+LOCATE COMP "sdram_dqm[1]" SITE "E20";
+LOCATE COMP "sdram_d[0]" SITE "J16";
+LOCATE COMP "sdram_d[1]" SITE "L18";
+LOCATE COMP "sdram_d[2]" SITE "M18";
+LOCATE COMP "sdram_d[3]" SITE "N18";
+LOCATE COMP "sdram_d[4]" SITE "P18";
+LOCATE COMP "sdram_d[5]" SITE "T18";
+LOCATE COMP "sdram_d[6]" SITE "T17";
+LOCATE COMP "sdram_d[7]" SITE "U20";
+LOCATE COMP "sdram_d[8]" SITE "E19";
+LOCATE COMP "sdram_d[9]" SITE "D20";
+LOCATE COMP "sdram_d[10]" SITE "D19";
+LOCATE COMP "sdram_d[11]" SITE "C20";
+LOCATE COMP "sdram_d[12]" SITE "E18";
+LOCATE COMP "sdram_d[13]" SITE "F18";
+LOCATE COMP "sdram_d[14]" SITE "J18";
+LOCATE COMP "sdram_d[15]" SITE "J17";
+IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+# GPDI differential interface (Video) "gpdi" sheet
+LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue +
+LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue -
+LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green +
+LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green -
+LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red +
+LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red -
+LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock +
+LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock -
+LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet +
+LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet -
+LOCATE COMP "gpdi_cec" SITE "A18";
+LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
+LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
+IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet
+# Pins enumerated gp[0-27], gn[0-27].
+# With differential mode enabled on Lattice,
+# gp[] (+) are used, gn[] (-) are ignored from design
+# as they handle inverted signal by default.
+# To enable differential, rename LVCMOS33->LVCMOS33D
+LOCATE COMP "gp[0]"  SITE "B11"; # J1_5+  GP0
+LOCATE COMP "gn[0]"  SITE "C11"; # J1_5-  GN0
+LOCATE COMP "gp[1]"  SITE "A10"; # J1_7+  GP1
+LOCATE COMP "gn[1]"  SITE "A11"; # J1_7-  GN1
+LOCATE COMP "gp[2]"  SITE "A9";  # J1_9+  GP2
+LOCATE COMP "gn[2]"  SITE "B10"; # J1_9-  GN2
+LOCATE COMP "gp[3]"  SITE "B9";  # J1_11+ GP3
+LOCATE COMP "gn[3]"  SITE "C10"; # J1_11- GN3
+LOCATE COMP "gp[4]"  SITE "A7";  # J1_13+ GP4
+LOCATE COMP "gn[4]"  SITE "A8";  # J1_13- GN4
+LOCATE COMP "gp[5]"  SITE "C8";  # J1_15+ GP5
+LOCATE COMP "gn[5]"  SITE "B8";  # J1_15- GN5
+LOCATE COMP "gp[6]"  SITE "C6";  # J1_17+ GP6
+LOCATE COMP "gn[6]"  SITE "C7";  # J1_17- GN6
+IOBUF PORT  "gp[0]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[0]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[1]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[1]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[2]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[2]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[3]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[3]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[4]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[4]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[5]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[5]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[6]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[6]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "gp[7]"  SITE "A6";  # J1_23+ GP7
+LOCATE COMP "gn[7]"  SITE "B6";  # J1_23- GN7
+LOCATE COMP "gp[8]"  SITE "A4";  # J1_25+ GP8
+LOCATE COMP "gn[8]"  SITE "A5";  # J1_25- GN8
+LOCATE COMP "gp[9]"  SITE "A2";  # J1_27+ GP9
+LOCATE COMP "gn[9]"  SITE "B1";  # J1_27- GN9
+LOCATE COMP "gp[10]" SITE "C4";  # J1_29+ GP10  WIFI_GPIO27
+LOCATE COMP "gn[10]" SITE "B4";  # J1_29- GN10
+LOCATE COMP "gp[11]" SITE "F4";  # J1_31+ GP11  WIFI_GPIO25
+LOCATE COMP "gn[11]" SITE "E3";  # J1_31- GN11  WIFI_GPIO26
+LOCATE COMP "gp[12]" SITE "G3";  # J1_33+ GP12  WIFI_GPIO32
+LOCATE COMP "gn[12]" SITE "F3";  # J1_33- GN12  WIFI_GPIO33
+LOCATE COMP "gp[13]" SITE "H4";  # J1_35+ GP13  WIFI_GPIO34
+LOCATE COMP "gn[13]" SITE "G5";  # J1_35- GN13  WIFI_GPIO35
+IOBUF PORT  "gp[7]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[7]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[8]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[8]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[9]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[9]"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "gp[14]" SITE "U18"; # J2_5+  GP14
+LOCATE COMP "gn[14]" SITE "U17"; # J2_5-  GN14
+LOCATE COMP "gp[15]" SITE "N17"; # J2_7+  GP15
+LOCATE COMP "gn[15]" SITE "P16"; # J2_7-  GN15
+LOCATE COMP "gp[16]" SITE "N16"; # J2_9+  GP16
+LOCATE COMP "gn[16]" SITE "M17"; # J2_9-  GN16
+LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17
+LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17
+LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18
+LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18
+LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19
+LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19
+LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20
+LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20
+IOBUF PORT  "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21
+LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21
+LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15
+LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15
+LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23
+LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23
+LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24
+LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24
+LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14
+LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14
+LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26
+LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26
+LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27
+LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27
+IOBUF PORT  "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
+# PCB v2.0.5 and higher
+LOCATE COMP "user_programn" SITE "M4";
+IOBUF  PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
+# on PCB v1.7 shutdown is not connected to FPGA
+LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
+IOBUF  PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
\ No newline at end of file
diff --git a/verilog/rtl/leorv-fpga/firmware/firmware.bin b/verilog/rtl/leorv-fpga/firmware/firmware.bin
new file mode 100755
index 0000000..e253dd8
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/firmware.bin
Binary files differ
diff --git a/verilog/rtl/leorv-fpga/firmware/firmware.elf b/verilog/rtl/leorv-fpga/firmware/firmware.elf
new file mode 100755
index 0000000..aee97dc
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/firmware.elf
Binary files differ
diff --git a/verilog/rtl/leorv-fpga/firmware/firmware.map b/verilog/rtl/leorv-fpga/firmware/firmware.map
new file mode 100644
index 0000000..b2e1097
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/firmware.map
@@ -0,0 +1,110 @@
+Archive member included to satisfy reference by file (symbol)
+
+/opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+                              firmware/main.o (__divsi3)
+
+Discarded input sections
+
+ .debug_line    0x0000000000000000      0x153 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+ .debug_line_str
+                0x0000000000000000       0x9d /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+ .debug_info    0x0000000000000000       0x25 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+ .debug_abbrev  0x0000000000000000       0x14 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+ .debug_aranges
+                0x0000000000000000       0x20 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+ .debug_str     0x0000000000000000       0xa3 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+ram              0x0000000000000000 0x0000000000000800 xrw
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+
+.text           0x0000000000000000      0x410
+                0x0000000000000000                . = ALIGN (0x4)
+ *(.reset_vector*)
+ .reset_vector  0x0000000000000000        0x4 firmware/start.o
+ *(.text)
+ .text          0x0000000000000004       0x94 firmware/start.o
+ .text          0x0000000000000098       0xec firmware/main.o
+                0x0000000000000098                busy_loop
+                0x00000000000000ac                tx_uart
+                0x00000000000000c8                rx_uart
+                0x00000000000000e0                rx_uart_nonblocking
+                0x00000000000000f4                write
+                0x0000000000000128                get_instret
+                0x0000000000000130                get_cycle
+                0x0000000000000138                write_int
+ .text          0x0000000000000184       0xb4 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+                0x0000000000000184                __divsi3
+                0x000000000000018c                __udivsi3
+                0x00000000000001d4                __umodsi3
+                0x0000000000000208                __modsi3
+ *(.text*)
+ .text.startup  0x0000000000000238      0x19c firmware/main.o
+                0x0000000000000238                main
+ *(.rodata)
+ *(.rodata*)
+ .rodata.str1.4
+                0x00000000000003d4       0x3b firmware/main.o
+ *(.srodata)
+ *(.srodata*)
+                0x0000000000000410                . = ALIGN (0x4)
+ *fill*         0x000000000000040f        0x1 
+                0x0000000000000410                _etext = .
+
+.rela.dyn       0x0000000000000410        0x0
+ .rela.text     0x0000000000000410        0x0 firmware/start.o
+
+.data           0x0000000000000410        0xc
+                0x0000000000000410                . = ALIGN (0x4)
+ *(.data)
+ .data          0x0000000000000410        0x0 firmware/start.o
+ .data          0x0000000000000410        0x0 firmware/main.o
+ .data          0x0000000000000410        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+ *(.data*)
+ *(.sdata)
+ .sdata         0x0000000000000410        0xc firmware/main.o
+                0x0000000000000410                uart
+                0x0000000000000414                svga
+                0x0000000000000418                led
+ *(.sdata*)
+                0x000000000000041c                . = ALIGN (0x4)
+                0x000000000000041c                _edata = .
+
+.bss            0x000000000000041c        0x0
+                0x000000000000041c                . = ALIGN (0x4)
+                0x000000000000041c                _sbss = .
+ *(.bss)
+ .bss           0x000000000000041c        0x0 firmware/start.o
+ .bss           0x000000000000041c        0x0 firmware/main.o
+ .bss           0x000000000000041c        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+ *(.bss*)
+ *(.sbss)
+ *(.sbss*)
+ *(COMMON)
+                0x000000000000041c                . = ALIGN (0x4)
+                0x000000000000041c                _ebss = .
+                0x000000000000041c                . = ALIGN (0x4)
+                0x000000000000041c                end = .
+                0x0000000000000800                PROVIDE (_stack = (ORIGIN (ram) + LENGTH (ram)))
+LOAD firmware/start.o
+LOAD firmware/main.o
+LOAD /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a
+OUTPUT(firmware/firmware.elf elf32-littleriscv)
+
+.riscv.attributes
+                0x0000000000000000       0x20
+ .riscv.attributes
+                0x0000000000000000       0x1e firmware/start.o
+ .riscv.attributes
+                0x000000000000001e       0x1c firmware/main.o
+ .riscv.attributes
+                0x000000000000003a       0x1a /opt/riscv32i/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
+
+.comment        0x0000000000000000       0x1b
+ .comment       0x0000000000000000       0x1b firmware/main.o
+                                         0x1c (size before relaxing)
diff --git a/verilog/rtl/leorv-fpga/firmware/icebreaker_sections.lds b/verilog/rtl/leorv-fpga/firmware/icebreaker_sections.lds
new file mode 100644
index 0000000..07ac72a
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/icebreaker_sections.lds
@@ -0,0 +1,51 @@
+# 0 "firmware/sections.lds"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "firmware/sections.lds"
+OUTPUT_ARCH(riscv)
+# 11 "firmware/sections.lds"
+MEMORY {
+ ram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x800
+}
+
+SECTIONS {
+    .text : {
+        . = ALIGN(4);
+        *(.reset_vector*)
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+        . = ALIGN(4);
+        _etext = .;
+    } >ram
+
+    .data : {
+        . = ALIGN(4);
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        . = ALIGN(4);
+        _edata = .;
+    } >ram
+
+    .bss : {
+        . = ALIGN(4);
+        _sbss = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss)
+        *(.sbss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+    } >ram
+
+    . = ALIGN(4);
+    end = .;
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
diff --git a/verilog/rtl/leorv-fpga/firmware/main.c b/verilog/rtl/leorv-fpga/firmware/main.c
new file mode 100644
index 0000000..551d5d5
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/main.c
@@ -0,0 +1,172 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+void main(int mhartid);
+void tx_uart(char data);
+char rx_uart(void);
+int rx_uart_nonblocking(char* data);
+void write(const char* message);
+int get_instret(void);
+int get_cycle(void);
+void write_int(int num);
+
+volatile int*  led  = (int*) 0x000F0000;
+volatile char* svga = (char*)0x00010000;
+volatile int* uart  = (int*) 0x000A0000; 
+
+void __attribute__ ((noinline)) busy_loop(unsigned max);
+
+// 3 instructions per iteration
+void __attribute__ ((noinline)) busy_loop(unsigned max) {
+    for (unsigned i = 0; i < max; i++) {
+        __asm__ volatile("" : "+g" (i) : :);
+    }
+}
+
+#define RX_FLAG (1<<31) // high for received, clears on read
+#define TX_FLAG (1<<30) // high on tx busy
+
+void tx_uart(char data)
+{
+    while(*uart & TX_FLAG);
+    *uart = data;
+}
+
+char rx_uart(void)
+{
+    while(!(*uart & RX_FLAG));
+    return *uart;
+}
+
+int rx_uart_nonblocking(char* data)
+{
+    int value = *uart;
+    *data = value & 0xFF;
+    return((value & RX_FLAG) > 0);
+}
+
+void write(const char* message)
+{
+    while(*message != 0)
+    {
+        tx_uart(*message);
+        message++;
+    }
+}
+
+int get_instret(void)
+{
+    int instret;
+    __asm__ volatile ("rdinstret %0" : "=r"(instret));
+    return instret;
+}
+
+int get_cycle(void)
+{
+    int cycle;
+    __asm__ volatile ("rdcycle %0" : "=r"(cycle));
+    return cycle;
+}
+
+void write_int(int num)
+{
+    if (num > 9)
+    {
+        int a = num / 10;
+        num -= 10 * a;
+        write_int(a);
+    }
+    tx_uart('0' + num);
+}
+
+typedef struct {
+    char r : 3;
+    char g : 3;
+    char b : 2;
+} color_t;
+
+void main(int mhartid)
+{
+    int value = 0;
+    
+    value = !value;
+    *led = value;
+
+    value = !value;
+    *led = value;
+
+    value = !value;
+    *led = value;
+
+    if (mhartid)
+    {
+        //tx_uart('#');
+        while (1)
+        {
+            // Takes around 1s
+            //busy_loop(500000);
+
+            value = !value;
+            *led = value;
+        }
+    }
+    
+    //write("Hello World on LeoRV32 :)\n");
+    //write("Running on RV32I, f=12MHz\n");
+
+    int width = 100;
+    int height = 75;
+
+    // Draw test graphics
+    for (int y = 0; y < height; y++)
+    {
+        for (int x = 0; x < width; x++)
+        {
+            color_t color = {y * 8 / height, (height-y) * 8 / height, x * 4 / width};
+            if (x == 0 || x == width-1 || y == 0 || y == height-1)
+            {
+                if (y%2) svga[y*width+x] = 0x00;
+                else svga[y*width+x] = 0xFF;
+            }
+            else svga[y*width+x] = *(char*)&color;
+        }
+    }
+    
+    write("!");
+    
+    // Clear additional half line
+    for (int x = 0; x < width; x++)
+    {
+        svga[height*width+x] = 0xFF;
+    }
+
+    while (1)
+    {
+        value = rx_uart();
+        tx_uart(value);
+        
+        switch (value)
+        {
+            case 'I':
+                write("\ninstret: ");
+                write_int(get_instret());
+                write("\n");
+                break;
+            case 'C':
+                write("\ncycle:   ");
+                write_int(get_cycle());
+                write("\n");
+                break;
+            case 'R':
+                write("\nratio cycle / instret:   ");
+                int instret;
+                __asm__ volatile ("rdinstret %0" : "=r"(instret));
+                int cycle;
+                __asm__ volatile ("rdcycle %0" : "=r"(cycle));
+                write_int(cycle / instret);
+                write("\n");
+                break;
+        }
+    }
+}
+
diff --git a/verilog/rtl/leorv-fpga/firmware/main.o b/verilog/rtl/leorv-fpga/firmware/main.o
new file mode 100644
index 0000000..bedf17b
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/main.o
Binary files differ
diff --git a/verilog/rtl/leorv-fpga/firmware/makehex.py b/verilog/rtl/leorv-fpga/firmware/makehex.py
new file mode 100644
index 0000000..419b378
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/makehex.py
@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+#
+# This is free and unencumbered software released into the public domain.
+#
+# Anyone is free to copy, modify, publish, use, compile, sell, or
+# distribute this software, either in source code form or as a compiled
+# binary, for any purpose, commercial or non-commercial, and by any
+# means.
+
+from sys import argv
+
+binfile = argv[1]
+nwords = int(argv[2])
+
+with open(binfile, "rb") as f:
+    bindata = f.read()
+
+assert len(bindata) < 4*nwords
+assert len(bindata) % 4 == 0
+
+for i in range(nwords):
+    if i < len(bindata) // 4:
+        w = bindata[4*i : 4*i+4]
+        print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0]))
+    else:
+        print("0")
+
diff --git a/verilog/rtl/leorv-fpga/firmware/sections.lds b/verilog/rtl/leorv-fpga/firmware/sections.lds
new file mode 100644
index 0000000..8fae958
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/sections.lds
@@ -0,0 +1,55 @@
+OUTPUT_ARCH(riscv)
+
+#if BOARD == icebreaker
+#  define MEM_TOTAL 0x800 /* 8 KB */
+#elif BOARD == ULX3S
+#  define MEM_TOTAL TODO
+#else
+#  error "Please define BOARD."
+#endif
+
+MEMORY {
+	ram (rwx) : ORIGIN = 0x00000000, LENGTH = MEM_TOTAL
+}
+
+SECTIONS {
+    .text : {
+        . = ALIGN(4);
+        *(.reset_vector*)
+        *(.text)           /* .text sections (code) */
+        *(.text*)          /* .text* sections (code) */
+        *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+        *(.srodata)        /* .rodata sections (constants, strings, etc.) */
+        *(.srodata*)       /* .rodata* sections (constants, strings, etc.) */
+        . = ALIGN(4);
+        _etext = .;        /* define a global symbol at end of code */
+    } >ram
+    
+    .data : {
+        . = ALIGN(4);
+        *(.data)           /* .data sections */
+        *(.data*)          /* .data* sections */
+        *(.sdata)           /* .sdata sections */
+        *(.sdata*)          /* .sdata* sections */
+        . = ALIGN(4);
+        _edata = .;        /* define a global symbol at data end */
+    } >ram
+
+    .bss : {
+        . = ALIGN(4);
+        _sbss = .;         /* define a global symbol at bss start; used by startup code */
+        *(.bss)
+        *(.bss*)
+        *(.sbss)
+        *(.sbss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;         /* define a global symbol at bss end; used by startup code */
+    } >ram
+
+    . = ALIGN(4);
+    end = .;
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
diff --git a/verilog/rtl/leorv-fpga/firmware/start.S b/verilog/rtl/leorv-fpga/firmware/start.S
new file mode 100644
index 0000000..44a84ec
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/start.S
@@ -0,0 +1,64 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#define CSR_MHARTID 0xF14
+
+.global main
+.global _stack
+
+.section .reset_vector
+
+reset_vector:
+	j start
+	
+.section .text
+
+start:
+	// Clear all registers
+	addi x1, zero, 0
+	addi x2, zero, 0
+	addi x3, zero, 0
+	addi x4, zero, 0
+	addi x5, zero, 0
+	addi x6, zero, 0
+	addi x7, zero, 0
+	addi x8, zero, 0
+	addi x9, zero, 0
+	addi x10, zero, 0
+	addi x11, zero, 0
+	addi x12, zero, 0
+	addi x13, zero, 0
+	addi x14, zero, 0
+	addi x15, zero, 0
+	addi x16, zero, 0
+	addi x17, zero, 0
+	addi x18, zero, 0
+	addi x19, zero, 0
+	addi x20, zero, 0
+	addi x21, zero, 0
+	addi x22, zero, 0
+	addi x23, zero, 0
+	addi x24, zero, 0
+	addi x25, zero, 0
+	addi x26, zero, 0
+	addi x27, zero, 0
+	addi x28, zero, 0
+	addi x29, zero, 0
+	addi x30, zero, 0
+	addi x31, zero, 0
+
+    // Initialize stack pointer
+    la sp, _stack
+
+    // Set the machine hart id as first argument
+    csrr a0, CSR_MHARTID
+
+	// Call main
+	call main
+
+	// Trap
+	ebreak
+	
+	// Infinite loop
+	loop:
+        j loop
diff --git a/verilog/rtl/leorv-fpga/firmware/start.o b/verilog/rtl/leorv-fpga/firmware/start.o
new file mode 100644
index 0000000..9273cf7
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/start.o
Binary files differ
diff --git a/verilog/rtl/leorv-fpga/firmware/ulx3s_sections.lds b/verilog/rtl/leorv-fpga/firmware/ulx3s_sections.lds
new file mode 100644
index 0000000..07ac72a
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/ulx3s_sections.lds
@@ -0,0 +1,51 @@
+# 0 "firmware/sections.lds"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "firmware/sections.lds"
+OUTPUT_ARCH(riscv)
+# 11 "firmware/sections.lds"
+MEMORY {
+ ram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x800
+}
+
+SECTIONS {
+    .text : {
+        . = ALIGN(4);
+        *(.reset_vector*)
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+        . = ALIGN(4);
+        _etext = .;
+    } >ram
+
+    .data : {
+        . = ALIGN(4);
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+        . = ALIGN(4);
+        _edata = .;
+    } >ram
+
+    .bss : {
+        . = ALIGN(4);
+        _sbss = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss)
+        *(.sbss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+    } >ram
+
+    . = ALIGN(4);
+    end = .;
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
diff --git a/verilog/rtl/leorv-fpga/firmware/verilogmem.py b/verilog/rtl/leorv-fpga/firmware/verilogmem.py
new file mode 100644
index 0000000..e6e2b4b
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/firmware/verilogmem.py
@@ -0,0 +1,55 @@
+# SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+import os
+import sys
+import argparse
+
+def main(binfile, wordsize, output, splits=1):
+
+    print(f'Reading "{binfile}" and writing in {splits} files(s) with wordsize {wordsize}')
+
+    if output == '':
+        filename, file_extension = os.path.splitext(binfile)
+        output = filename
+
+    with open(binfile, 'rb') as f:
+        bindata = f.read()
+
+    print(f'Length of binary: {len(bindata)}')
+
+    if (len(bindata) > 4*wordsize*splits):
+        print('Error: Binary too big!')
+        sys.exit(-1)
+        
+    if (len(bindata) % 4 != 0):
+        print('Error: Binary not a multiple of 4!')
+        sys.exit(-1)
+
+    for i in range(splits):
+    
+        out_file = f'{output}_{i}.hex'
+    
+        print(f'Writing to {out_file}...')
+    
+        with open(out_file, 'w') as f:
+    
+            for j in range(wordsize):
+                word = 0x00000000
+                if len(bindata) > 0:
+                    word = bindata[0:4]
+                    bindata = bindata[4:]
+                    word = int.from_bytes(bytes(word), "little")
+                
+                
+                f.write(f'{word:08X}\n')
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser()
+    parser.add_argument('binary')
+    parser.add_argument('wordsize', type=int)
+    parser.add_argument('--splits', '-s', type=int, default=1)
+    parser.add_argument('--output', '-o', type=str, default='')
+    args = parser.parse_args()
+
+    main(args.binary, args.wordsize, args.output, args.splits)
diff --git a/verilog/rtl/leorv-fpga/images/color_test_chart.png b/verilog/rtl/leorv-fpga/images/color_test_chart.png
new file mode 100644
index 0000000..a07597d
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/images/color_test_chart.png
Binary files differ
diff --git a/verilog/rtl/leorv-fpga/images/image_converter.py b/verilog/rtl/leorv-fpga/images/image_converter.py
new file mode 100644
index 0000000..7c81a66
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/images/image_converter.py
@@ -0,0 +1,49 @@
+from PIL import Image
+import argparse
+
+HEIGHT = 75
+WIDTH = 100
+
+def main(filename):
+
+    im = Image.open(filename)
+    print(f'Loading {filename}')
+    print(f'Original size: {im.size}')
+
+    im = im.resize((WIDTH, HEIGHT))
+    pix = im.load()
+    print(f'New size: {im.size}')
+
+
+    def convertColor(color):
+        
+        r = int(color[0]/255*7)
+        g = int(color[1]/255*7)
+        b = int(color[2]/255*3)
+        
+        return ((b&3) << 6) | ((g&7) << 3) | r&7
+
+    content = ""
+
+    for y in range(HEIGHT):
+        for x in range(WIDTH//4):
+            byte0 = convertColor(pix[x*4+0, y])
+            byte1 = convertColor(pix[x*4+1, y])
+            byte2 = convertColor(pix[x*4+2, y])
+            byte3 = convertColor(pix[x*4+3, y])
+            content += '{0:08X}\n'.format(byte3<<24|byte2<<16|byte1<<8|byte0)
+
+    index = filename.rfind(".")
+    filename = filename[:index] + ".hex"
+
+    print(f'Saving {filename}')
+    f = open(filename, "w")
+    f.write(content)
+    f.close()
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser()
+    parser.add_argument('filename')
+    args = parser.parse_args()
+    
+    main(args.filename)
diff --git a/verilog/rtl/leorv-fpga/images/kathi.png b/verilog/rtl/leorv-fpga/images/kathi.png
new file mode 100644
index 0000000..5b51b45
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/images/kathi.png
Binary files differ
diff --git a/verilog/rtl/leorv-fpga/leorv32/LICENSE b/verilog/rtl/leorv-fpga/leorv32/LICENSE
new file mode 100644
index 0000000..d41c0bd
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/leorv32/LICENSE
@@ -0,0 +1,232 @@
+GNU GENERAL PUBLIC LICENSE
+Version 3, 29 June 2007
+
+Copyright © 2007 Free Software Foundation, Inc. <http://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
+
+Preamble
+
+The GNU General Public License is a free, copyleft license for software and other kinds of works.
+
+The licenses for most software and other practical works are designed to take away your freedom to share and change the works. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change all versions of a program--to make sure it remains free software for all its users. We, the Free Software Foundation, use the GNU General Public License for most of our software; it applies also to any other work released this way by its authors. You can apply it to your programs, too.
+
+When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for them if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs, and that you know you can do these things.
+
+To protect your rights, we need to prevent others from denying you these rights or asking you to surrender the rights. Therefore, you have certain responsibilities if you distribute copies of the software, or if you modify it: responsibilities to respect the freedom of others.
+
+For example, if you distribute copies of such a program, whether gratis or for a fee, you must pass on to the recipients the same freedoms that you received. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.
+
+Developers that use the GNU GPL protect your rights with two steps: (1) assert copyright on the software, and (2) offer you this License giving you legal permission to copy, distribute and/or modify it.
+
+For the developers' and authors' protection, the GPL clearly explains that there is no warranty for this free software. For both users' and authors' sake, the GPL requires that modified versions be marked as changed, so that their problems will not be attributed erroneously to authors of previous versions.
+
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+
+Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law.
+
+12. No Surrender of Others' Freedom.
+If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program.
+
+13. Use with the GNU Affero General Public License.
+Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such.
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+14. Revised Versions of this License.
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+
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+
+Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version.
+
+15. Disclaimer of Warranty.
+THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+16. Limitation of Liability.
+IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+17. Interpretation of Sections 15 and 16.
+If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee.
+
+END OF TERMS AND CONDITIONS
+
+How to Apply These Terms to Your New Programs
+
+If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found.
+
+     <one line to give the program's name and a brief idea of what it does.>
+     Copyright (C) <year>  <name of author>
+
+     This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
+
+     This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+
+     You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode:
+
+     <program>  Copyright (C) <year>  <name of author>
+     This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+     This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”.
+
+You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see <http://www.gnu.org/licenses/>.
+
+The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read <http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/verilog/rtl/leorv-fpga/leorv32/README.md b/verilog/rtl/leorv-fpga/leorv32/README.md
new file mode 100644
index 0000000..32949f5
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/leorv32/README.md
@@ -0,0 +1,5 @@
+# LeoRV32
+
+LeoRV32 is a simple RV32I RISC-V CPU written in SystemVerilog.
+
+All SystemVerilog features used are supported by Yosys and Icarus Verilog.
\ No newline at end of file
diff --git a/verilog/rtl/leorv-fpga/leorv32/rtl/leorv32.sv b/verilog/rtl/leorv-fpga/leorv32/rtl/leorv32.sv
new file mode 100644
index 0000000..9e9ffaa
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/leorv32/rtl/leorv32.sv
@@ -0,0 +1,487 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module leorv32_alu (
+    input [31:0] input1,
+    input [31:0] input2,
+
+    output wire [31:0] result_add,
+    output wire [31:0] result_subtract,
+
+    output wire [31:0] result_and,
+    output wire [31:0] result_or,
+    output wire [31:0] result_xor,
+
+    output wire result_lt,
+    output wire result_ltu,
+    output wire result_eq
+);
+
+    assign result_add = input1 + input2;
+    assign result_subtract = input1 - input2;
+
+    assign result_and = input1 & input2;
+    assign result_or = input1 | input2;
+    assign result_xor = input1 ^ input2;
+
+    assign result_lt = $signed(input1) < $signed(input2);
+    assign result_ltu = input1 < input2;
+    assign result_eq = (result_subtract == 0);
+
+endmodule
+
+module shifter_right (
+    input  [31:0] data_in,
+    input  [ 4:0] shift,
+    input         arith,
+    output [31:0] data_out
+);
+
+    assign data_out = $signed({arith && data_in[31], data_in}) >>> shift;
+
+endmodule
+
+module barrel_shifter_right (
+    input        [31:0] data_in,
+    input        [ 4:0] shift,
+    input               arith,
+    output logic [31:0] data_out
+);
+
+    logic [32:0] tmp;
+
+    always_comb begin
+        tmp = {arith && data_in[31], data_in};
+        if (shift[4]) tmp = $signed(tmp) >>> 16;
+        if (shift[3]) tmp = $signed(tmp) >>> 8;
+        if (shift[2]) tmp = $signed(tmp) >>> 4;
+        if (shift[1]) tmp = $signed(tmp) >>> 2;
+        if (shift[0]) tmp = $signed(tmp) >>> 1;
+        data_out = tmp;
+    end
+
+endmodule
+
+
+module leorv32 #(
+    parameter int RESET_ADDR = 32'h00000000,
+    parameter int ADDR_WIDTH = 24,
+    parameter int MHARTID    = 0
+) (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+    input clk,
+    input reset,
+
+    output [31:0] mem_addr,   // address
+    output [31:0] mem_wdata,  // write data
+    output [ 3:0] mem_wmask,  // write mask
+    input  [31:0] mem_rdata,  // read data
+    output        mem_rstrb,  // read strobe
+    input         mem_rbusy,  // read busy
+    input         mem_wbusy,  // write busy
+
+    input mhartid_0 // ored with the last bit of MAHRTID
+);
+    // Registers
+
+    logic [ADDR_WIDTH-1:0] PC;
+    logic [31: 0] regs [32];
+
+    // Instruction and subfields
+
+    logic [31: 0] instr;
+    logic [ 6: 0] opcode;
+    logic [ 4: 0] rd;
+    logic [ 4: 0] rs1;
+    logic [ 4: 0] rs2;
+    logic [ 2: 0] funct3;
+    logic [ 6: 0] funct7;
+
+    assign opcode = instr[6:0];
+    assign rd     = instr[11:7];
+    assign rs1    = instr[19:15];
+    assign rs2    = instr[24:20];
+    assign funct3 = instr[14:12];
+    assign funct7 = instr[31:25];
+
+    // Sign-extended immediates
+
+    logic [31: 0] I_type_imm;
+    logic [31: 0] S_type_imm;
+    logic [31: 0] B_type_imm;
+    logic [31: 0] U_type_imm;
+    logic [31: 0] J_type_imm;
+
+    assign I_type_imm = {{21{instr[31]}}, instr[30:20]};
+    assign S_type_imm = {{21{instr[31]}}, instr[30:25], instr[11:7]};
+    assign B_type_imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
+    assign U_type_imm = {instr[31:12], {12{1'b0}}};
+    assign J_type_imm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
+
+    // Debug
+
+    logic is_nop;
+    assign is_nop = instr === {{12{1'b0}}, {5{1'b0}}, leorv32_pkg::FUNC_ADDI, {5{1'b0}}, leorv32_pkg::OP_IMM};
+
+    // Memory access
+
+    logic [31: 0] store_data;
+    logic [ 3: 0] store_wmask;
+
+    logic [ADDR_WIDTH-1: 0] store_address;
+    logic [ADDR_WIDTH-1: 0] load_address;
+
+    assign mem_wmask = store_wmask;
+    assign mem_wdata = store_data;
+
+    assign store_address = rs1_content + S_type_imm;
+    assign load_address = rs1_content + I_type_imm;
+
+    assign mem_addr  = core_state == ST_EXECUTE && opcode == leorv32_pkg::OP_LOAD  ? load_address
+                     : core_state == ST_EXECUTE && opcode == leorv32_pkg::OP_STORE ? store_address
+                     : PC;
+
+    assign mem_rstrb = core_state == ST_FETCH || (core_state == ST_EXECUTE && opcode == leorv32_pkg::OP_LOAD);
+
+    // Core state machine
+
+    typedef enum {
+        ST_FETCH,
+        ST_FETCH_WAIT,
+        ST_EXECUTE,
+        ST_EXECUTE_WAIT
+    } state_t;
+
+    state_t core_state;
+
+    logic [31: 0] rs1_content;
+    logic [31: 0] rs2_content;
+
+    always_ff @(posedge clk) begin
+        if (reset) regs[0] <= '0;
+        else if (writeBack && rd != 0) regs[rd] <= writeBackData;
+    end
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            core_state  <= ST_FETCH;
+            instret     <= '0;
+            PC          <= RESET_ADDR;
+            instr       <= '0;
+            rs1_content <= '0;
+            rs2_content <= '0;
+        end else begin
+            case (core_state)
+                ST_FETCH:
+                    core_state <= ST_FETCH_WAIT;
+                ST_FETCH_WAIT: begin
+                    if (!mem_rbusy) begin
+                        instr <= mem_rdata;
+                        rs1_content <= regs[mem_rdata[19:15]];
+                        rs2_content <= regs[mem_rdata[24:20]];
+                        core_state <= ST_EXECUTE;
+                    end
+                end
+                ST_EXECUTE: begin
+                    PC <= newPC;
+                    core_state <= ST_EXECUTE_WAIT;
+                end
+                ST_EXECUTE_WAIT: begin
+                    if (!mem_wbusy && !mem_rbusy) begin
+                        core_state <= ST_FETCH;
+                        instret <= instret + 1;
+                    end
+                end
+            endcase
+        end
+    end
+
+`ifndef SYNTHESIS
+    logic [7:0][15:0] core_state_text;
+    always_comb begin
+        case (core_state)
+            ST_FETCH:           core_state_text = "ST_FETCH";
+            ST_FETCH_WAIT:      core_state_text = "ST_FETCH_WAIT";
+            ST_EXECUTE:         core_state_text = "ST_EXECUTE";
+            ST_EXECUTE_WAIT:    core_state_text = "ST_EXECUTE_WAIT";
+            default:            core_state_text = "UNKNOWN";
+        endcase
+    end
+`endif
+
+    // Store
+
+    always_comb begin
+        store_wmask = '0;
+        store_data  = '0;
+
+        if (core_state == ST_EXECUTE && opcode == leorv32_pkg::OP_STORE) begin
+            case (funct3)  // Width
+                leorv32_pkg::FUNC_SB:
+                case (store_address[1:0])
+                    2'b00: begin
+                        store_wmask = 4'b0001;
+                        store_data  = rs2_content & 32'h000000FF;
+                    end
+                    2'b01: begin
+                        store_wmask = 4'b0010;
+                        store_data  = (rs2_content & 32'h000000FF) << 8;
+                    end
+                    2'b10: begin
+                        store_wmask = 4'b0100;
+                        store_data  = (rs2_content & 32'h000000FF) << 16;
+                    end
+                    2'b11: begin
+                        store_wmask = 4'b1000;
+                        store_data  = (rs2_content & 32'h000000FF) << 24;
+                    end
+                endcase
+                leorv32_pkg::FUNC_SH:
+                case (store_address[1:0])
+                    2'b00: begin
+                        store_wmask = 4'b0011;
+                        store_data  = rs2_content & 32'h0000FFFF;
+                    end
+                    2'b10: begin
+                        store_wmask = 4'b1100;
+                        store_data  = rs2_content << 16;
+                    end
+                endcase
+                leorv32_pkg::FUNC_SW: begin
+                    store_wmask = 4'b1111;
+                    store_data  = rs2_content;
+                end
+            endcase
+        end
+    end
+
+    // ALU
+
+    logic [31: 0] alu_input1;
+    logic [31: 0] alu_input2;
+
+    assign alu_input1 = rs1_content;
+    assign alu_input2 = opcode == leorv32_pkg::OP_ARITH ? rs2_content : I_type_imm;
+
+    logic [31: 0] alu_add;
+    logic [31: 0] alu_subtract;
+
+    logic [31: 0] alu_and;
+    logic [31: 0] alu_or;
+    logic [31: 0] alu_xor;
+
+    logic alu_lt;
+    logic alu_ltu;
+    logic alu_eq;
+
+    leorv32_alu leorv32_alu (
+        .input1(alu_input1),
+        .input2(alu_input2),
+
+        .result_add(alu_add),
+        .result_subtract(alu_subtract),
+
+        .result_and(alu_and),
+        .result_or (alu_or),
+        .result_xor(alu_xor),
+
+        .result_lt (alu_lt),
+        .result_ltu(alu_ltu),
+        .result_eq (alu_eq)
+    );
+
+    // Shifter
+
+    logic [4:0] shift_amount;
+    assign shift_amount = opcode == leorv32_pkg::OP_IMM ? I_type_imm[4:0] : rs2_content[4:0];
+
+    logic [31:0] rs1_content_r;
+    genvar i;
+    for (i = 0; i < 32; i = i + 1) assign rs1_content_r[i] = rs1_content[31-i];
+
+    logic [31:0] shifter_input;
+    assign shifter_input = funct3[2] ? rs1_content : rs1_content_r;
+
+    logic [31:0] shifter_out;
+
+    barrel_shifter_right barrel_shifter_right (
+        .data_in (shifter_input),
+        .shift   (shift_amount),
+        .arith   (funct7[5]),      // TODO own signals
+        .data_out(shifter_out)
+    );
+
+    logic [31:0] shifter_out_r;
+
+    for (i = 0; i < 32; i = i + 1) assign shifter_out_r[i] = shifter_out[31-i];
+
+    logic [31:0] shifter_result;
+    assign shifter_result = funct3[2] ? shifter_out : shifter_out_r;
+
+
+    // Write back logic
+
+    logic writeBack;
+    logic [31: 0] writeBackData;
+
+    always_comb begin
+        writeBack = 1'b0;
+        if (core_state == ST_EXECUTE) begin
+            case (opcode)
+                leorv32_pkg::OP_IMM:    writeBack = 1'b1;
+                leorv32_pkg::OP_ARITH:  writeBack = 1'b1;
+                leorv32_pkg::OP_LUI:    writeBack = 1'b1;
+                leorv32_pkg::OP_AUIPC:  writeBack = 1'b1;
+                leorv32_pkg::OP_JAL:    writeBack = 1'b1;
+                leorv32_pkg::OP_JALR:   writeBack = 1'b1;
+                leorv32_pkg::OP_SYSTEM: if (rs1_content == 0) writeBack = 1'b1;
+            endcase
+        end else if (core_state == ST_EXECUTE_WAIT) begin
+            case (opcode)
+                leorv32_pkg::OP_LOAD: writeBack = 1'b1;
+            endcase
+        end
+    end
+
+    always_comb begin
+        writeBackData = '0;
+        if (core_state == ST_EXECUTE) begin
+            case (opcode)
+                leorv32_pkg::OP_IMM:
+                    case (funct3)
+                        leorv32_pkg::FUNC_ADDI:       writeBackData = alu_add;
+                        leorv32_pkg::FUNC_SLTI:       writeBackData = {31'b0, alu_lt};
+                        leorv32_pkg::FUNC_SLTIU:      writeBackData = {31'b0, alu_ltu};
+                        leorv32_pkg::FUNC_ANDI:       writeBackData = alu_and;
+                        leorv32_pkg::FUNC_ORI:        writeBackData = alu_or;
+                        leorv32_pkg::FUNC_XORI:       writeBackData = alu_xor;
+                        leorv32_pkg::FUNC_SLLI:       writeBackData = shifter_result;
+                        leorv32_pkg::FUNC_SRLI_SRAI:
+                            case(I_type_imm[11:5])
+                                7'b0000000: writeBackData = shifter_result;
+                                7'b0100000: writeBackData = shifter_result;
+                            endcase
+                    endcase
+                leorv32_pkg::OP_ARITH:
+                    case (funct3)
+                        leorv32_pkg::FUNC_ADD_SUB:
+                            case(funct7)
+                                7'b0000000: writeBackData = alu_add;
+                                7'b0100000: writeBackData = alu_subtract;
+                            endcase
+                        leorv32_pkg::FUNC_SLT:          writeBackData = {31'b0, alu_lt};
+                        leorv32_pkg::FUNC_SLTU:         writeBackData = {31'b0, alu_ltu};
+                        leorv32_pkg::FUNC_AND:          writeBackData = alu_and;
+                        leorv32_pkg::FUNC_OR:           writeBackData = alu_or;
+                        leorv32_pkg::FUNC_XOR:          writeBackData = alu_xor;
+                        leorv32_pkg::FUNC_SLL:          writeBackData = shifter_result;
+                        leorv32_pkg::FUNC_SRL_SRA:
+                            case(funct7)
+                                7'b0000000: writeBackData = shifter_result;
+                                7'b0100000: writeBackData = shifter_result;
+                            endcase
+                    endcase
+                leorv32_pkg::OP_LUI:    writeBackData = U_type_imm;
+                leorv32_pkg::OP_AUIPC:  writeBackData = PC + U_type_imm;
+                leorv32_pkg::OP_JAL:    writeBackData = PCplus4;
+                leorv32_pkg::OP_JALR:   writeBackData = PCplus4;
+                leorv32_pkg::OP_SYSTEM:
+                    case (funct3)
+                        leorv32_pkg::FUNC_CSRRW: ;
+                        leorv32_pkg::FUNC_CSRRS:
+                            case (I_type_imm[11:0]) // CSR
+                                leorv32_pkg::CSR_RDCYCLE:     writeBackData = cycles[31:0];
+                                leorv32_pkg::CSR_RDCYCLEH:    writeBackData = cycles[63:32];
+                                leorv32_pkg::CSR_RDTIME:      writeBackData = cycles[31:0];
+                                leorv32_pkg::CSR_RDTIMEH:     writeBackData = cycles[63:32];
+                                leorv32_pkg::CSR_RDINSTRET:   writeBackData = instret[31:0];
+                                leorv32_pkg::CSR_RDINSTRETH:  writeBackData = instret[63:32];
+                                leorv32_pkg::CSR_MHARTID:     writeBackData = MHARTID | {31'b0, mhartid_0};
+                            endcase
+                        leorv32_pkg::FUNC_CSRRC:  ;
+                        leorv32_pkg::FUNC_CSRRWI: ;
+                        leorv32_pkg::FUNC_CSRRSI: ;
+                        leorv32_pkg::FUNC_CSRRCI: ;
+                    endcase
+            endcase
+        end else if (core_state == ST_EXECUTE_WAIT) begin
+            case (opcode)
+                leorv32_pkg::OP_LOAD:
+                case (funct3)  // Width
+                    leorv32_pkg::FUNC_LB:
+                            case (load_address[1:0])
+                                2'b00: writeBackData = {{24{mem_rdata[7]}}, mem_rdata[7:0]};
+                                2'b01: writeBackData = {{24{mem_rdata[15]}}, mem_rdata[15:8]};
+                                2'b10: writeBackData = {{24{mem_rdata[23]}}, mem_rdata[23:16]};
+                                2'b11: writeBackData = {{24{mem_rdata[31]}}, mem_rdata[31:24]};
+                            endcase
+                    leorv32_pkg::FUNC_LH:
+                            case (load_address[1])
+                                1'b0: writeBackData = {{16{mem_rdata[15]}}, mem_rdata[15:0]};
+                                1'b1: writeBackData = {{16{mem_rdata[23]}}, mem_rdata[31:16]};
+                            endcase
+                    leorv32_pkg::FUNC_LW:
+                            begin
+                                writeBackData = mem_rdata;
+                            end
+                    leorv32_pkg::FUNC_LBU:
+                            case (load_address[1:0])
+                                2'b00: writeBackData = {{24{1'b0}}, mem_rdata[7:0]};
+                                2'b01: writeBackData = {{24{1'b0}}, mem_rdata[15:8]};
+                                2'b10: writeBackData = {{24{1'b0}}, mem_rdata[23:16]};
+                                2'b11: writeBackData = {{24{1'b0}}, mem_rdata[31:24]};
+                            endcase
+                    leorv32_pkg::FUNC_LHU:
+                            case (load_address[1])
+                                1'b0: writeBackData = {{16{1'b0}}, mem_rdata[15:0]};
+                                1'b1: writeBackData = {{16{1'b0}}, mem_rdata[31:16]};
+                            endcase
+                endcase
+            endcase
+        end
+    end
+
+    // PC
+
+    logic [ADDR_WIDTH-1: 0] newPC;
+    logic [ADDR_WIDTH-1: 0] PCplus4;
+
+    assign PCplus4 = PC + 4;
+
+    always_comb begin
+        // Increment PC, overwritten by jumps and branches
+        newPC = PCplus4;
+        if (core_state == ST_EXECUTE) begin
+            case (opcode)
+                leorv32_pkg::OP_JAL:    newPC = PC + J_type_imm;
+                leorv32_pkg::OP_JALR:   newPC = ((rs1_content + I_type_imm) & 32'hFFFFFFFE);
+                leorv32_pkg::OP_BRANCH:
+                    case (funct3)
+                        leorv32_pkg::FUNC_BEQ:  newPC = rs1_content == rs2_content ? PC + B_type_imm : PCplus4;
+                        leorv32_pkg::FUNC_BNE:  newPC = rs1_content != rs2_content ? PC + B_type_imm : PCplus4;
+                        leorv32_pkg::FUNC_BLTU: newPC = rs1_content <  rs2_content ? PC + B_type_imm : PCplus4;
+                        leorv32_pkg::FUNC_BGEU: newPC = rs1_content >= rs2_content ? PC + B_type_imm : PCplus4;
+                        leorv32_pkg::FUNC_BLT:  newPC = $signed(rs1_content) <  $signed(rs2_content) ? PC + B_type_imm : PCplus4;
+                        leorv32_pkg::FUNC_BGE:  newPC = $signed(rs1_content) >= $signed(rs2_content) ? PC + B_type_imm : PCplus4;
+                    endcase
+            endcase
+        end
+    end
+
+    // Counters
+
+    logic [63: 0]  cycles;
+    logic [63: 0]  instret;
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            cycles <= '0;
+        end else cycles <= cycles + 1;
+    end
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/leorv32/rtl/leorv32_pkg.sv b/verilog/rtl/leorv-fpga/leorv32/rtl/leorv32_pkg.sv
new file mode 100644
index 0000000..dd694ba
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/leorv32/rtl/leorv32_pkg.sv
@@ -0,0 +1,77 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+package leorv32_pkg;
+
+    // Opcodes
+    parameter bit [6:0] OP_IMM      = 7'b0010011;
+    parameter bit [6:0] OP_LUI      = 7'b0110111;
+    parameter bit [6:0] OP_AUIPC    = 7'b0010111;
+    parameter bit [6:0] OP_ARITH    = 7'b0110011;
+    parameter bit [6:0] OP_JAL      = 7'b1101111;
+    parameter bit [6:0] OP_JALR     = 7'b1100111;
+    parameter bit [6:0] OP_BRANCH   = 7'b1100011;
+    parameter bit [6:0] OP_LOAD     = 7'b0000011;
+    parameter bit [6:0] OP_STORE    = 7'b0100011;
+    parameter bit [6:0] OP_MISC_MEM = 7'b0001111;
+    parameter bit [6:0] OP_SYSTEM   = 7'b1110011;
+    
+    // Functions for OP_IMM
+    parameter bit [2:0] FUNC_ADDI   = 3'b000;
+    parameter bit [2:0] FUNC_SLTI   = 3'b010;
+    parameter bit [2:0] FUNC_SLTIU  = 3'b011;
+    parameter bit [2:0] FUNC_ANDI   = 3'b111;
+    parameter bit [2:0] FUNC_ORI    = 3'b110;
+    parameter bit [2:0] FUNC_XORI   = 3'b100;
+    parameter bit [2:0] FUNC_SLLI       = 3'b001;
+    parameter bit [2:0] FUNC_SRLI_SRAI  = 3'b101;
+    
+    // Functions for OP_ARITH
+    parameter bit [2:0] FUNC_ADD_SUB    = 3'b000;
+    parameter bit [2:0] FUNC_SLT        = 3'b010;
+    parameter bit [2:0] FUNC_SLTU       = 3'b011;
+    parameter bit [2:0] FUNC_AND        = 3'b111;
+    parameter bit [2:0] FUNC_OR         = 3'b110;
+    parameter bit [2:0] FUNC_XOR        = 3'b100;
+    parameter bit [2:0] FUNC_SLL        = 3'b001;
+    parameter bit [2:0] FUNC_SRL_SRA    = 3'b101;
+    
+    // Functions for OP_BRANCH
+    parameter bit [2:0] FUNC_BEQ    = 3'b000;
+    parameter bit [2:0] FUNC_BNE    = 3'b001;
+    parameter bit [2:0] FUNC_BLT    = 3'b100;
+    parameter bit [2:0] FUNC_BLTU   = 3'b110;
+    parameter bit [2:0] FUNC_BGE    = 3'b101;
+    parameter bit [2:0] FUNC_BGEU   = 3'b111;
+    
+    // Functions for OP_STORE
+    parameter bit [2:0] FUNC_SB  = 3'b000;
+    parameter bit [2:0] FUNC_SH  = 3'b001;
+    parameter bit [2:0] FUNC_SW  = 3'b010;
+    
+    // Functions for OP_LOAD
+    parameter bit [2:0] FUNC_LB  = 3'b000;
+    parameter bit [2:0] FUNC_LH  = 3'b001;
+    parameter bit [2:0] FUNC_LW  = 3'b010;
+    parameter bit [2:0] FUNC_LBU = 3'b100;
+    parameter bit [2:0] FUNC_LHU = 3'b101;
+
+    
+    // Functions for OP_SYSTEM
+    parameter bit [2:0] FUNC_CSRRW  = 3'b001;
+    parameter bit [2:0] FUNC_CSRRS  = 3'b010;
+    parameter bit [2:0] FUNC_CSRRC  = 3'b011;
+    parameter bit [2:0] FUNC_CSRRWI = 3'b101;
+    parameter bit [2:0] FUNC_CSRRSI = 3'b110;
+    parameter bit [2:0] FUNC_CSRRCI = 3'b111;
+    
+    // CSRs
+    parameter bit [11:0] CSR_RDCYCLE     = 12'hC00;
+    parameter bit [11:0] CSR_RDCYCLEH    = 12'hC80;
+    parameter bit [11:0] CSR_RDTIME      = 12'hC01;
+    parameter bit [11:0] CSR_RDTIMEH     = 12'hC81;
+    parameter bit [11:0] CSR_RDINSTRET   = 12'hC02;
+    parameter bit [11:0] CSR_RDINSTRETH  = 12'hC82;
+    parameter bit [11:0] CSR_MHARTID     = 12'hF14;
+
+endpackage
diff --git a/verilog/rtl/leorv-fpga/mem_port_switch/rtl/mem_port_switch.sv b/verilog/rtl/leorv-fpga/mem_port_switch/rtl/mem_port_switch.sv
new file mode 100644
index 0000000..45eef3a
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/mem_port_switch/rtl/mem_port_switch.sv
@@ -0,0 +1,56 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module mem_port_switch #(
+    parameter NUM_WMASKS = 4,
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 11
+) (
+    input port_select,
+
+    // Input Memory Port 0 - R/W
+    input  input_web0,
+    input  [NUM_WMASKS-1:0] input_wmask0,
+    input  [ADDR_WIDTH-1:0] input_addr0,
+    input  [DATA_WIDTH-1:0] input_din0,
+    output [DATA_WIDTH-1:0] input_dout0,
+    
+    // Input Memory Port 1 - R/W
+    input  input_web1,
+    input  [NUM_WMASKS-1:0] input_wmask1,
+    input  [ADDR_WIDTH-1:0] input_addr1,
+    input  [DATA_WIDTH-1:0] input_din1,
+    output [DATA_WIDTH-1:0] input_dout1,
+    
+    // Output Memory Port 0 - R/W
+    output output_web0,
+    output [NUM_WMASKS-1:0] output_wmask0,
+    output [ADDR_WIDTH-1:0] output_addr0,
+    output [DATA_WIDTH-1:0] output_din0,
+    input  [DATA_WIDTH-1:0] output_dout0,
+    
+    // Output Memory Port 1 - R
+    output [ADDR_WIDTH-1:0] output_addr1,
+    input  [DATA_WIDTH-1:0] output_dout1
+);
+
+    // port_select == 0 -> Input Memory Port 0 goes to Output Memory Port 0
+    // port_select == 0 -> Input Memory Port 1 goes to Output Memory Port 1
+    
+    // port_select == 1 -> Input Memory Port 0 goes to Output Memory Port 1
+    // port_select == 1 -> Input Memory Port 1 goes to Output Memory Port 0
+
+
+    assign output_web0   = !port_select ? input_web0   : input_web1;
+    assign output_wmask0 = !port_select ? input_wmask0 : input_wmask1;
+    assign output_addr0  = !port_select ? input_addr0  : input_addr1;
+    assign output_din0   = !port_select ? input_din0   : input_din1;
+    
+    assign output_addr1  = !port_select ? input_addr1  : input_addr0;
+    
+    assign input_dout0   = !port_select ? output_dout0 : output_dout1;
+    assign input_dout1   = !port_select ? output_dout1 : output_dout0;
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/rtl/dual_soc.sv b/verilog/rtl/leorv-fpga/soc/rtl/dual_soc.sv
new file mode 100644
index 0000000..0d91d5b
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/rtl/dual_soc.sv
@@ -0,0 +1,231 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module dual_soc #(
+    parameter int FREQUENCY = 12_000_000,
+    parameter int BAUDRATE  = 9600
+) (
+    input clk,
+    input reset,
+
+    input        uart_rx,
+    output logic uart_tx,
+
+    output logic blink
+);
+
+    // Synchronization
+
+    logic uart_rx_sync;
+
+    synchronizer #(
+        .FF_COUNT(3)
+    ) synchronizer (
+        .clk(clk),
+        .resetn(!reset),
+        .in(uart_rx),
+
+        .out(uart_rx_sync)
+    );
+
+    // CPU
+
+    logic [31: 0] mem_addr_core0;
+    logic [31: 0] mem_wdata_core0;
+    logic [ 3: 0] mem_wmask_core0;
+    logic         mem_rstrb_core0;
+
+    logic [31: 0] mem_addr_core1;
+    logic [31: 0] mem_wdata_core1;
+    logic [ 3: 0] mem_wmask_core1;
+    logic         mem_rstrb_core1;
+
+    logic [31: 0] mem_rdata;
+    logic         mem_rbusy;
+    logic         mem_wbusy;
+
+
+
+    leorv32 #(
+        .RESET_ADDR(32'h00000000),
+        .ADDR_WIDTH(16),
+        .MHARTID(0)
+    ) leorv32_core0 (
+        .clk(clk),
+        .reset(reset),
+
+        .mem_addr (mem_addr_core0),
+        .mem_wdata(mem_wdata_core0),
+        .mem_wmask(mem_wmask_core0),
+        .mem_rdata(mem_rdata),
+        .mem_rstrb(mem_rstrb_core0),
+        .mem_rbusy(mem_rbusy),
+        .mem_wbusy(mem_wbusy),
+        
+        .mhartid_0(1'b0)
+    );
+
+    logic reset_delayed;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            reset_delayed <= 1'b1;
+        end else begin
+            reset_delayed <= reset;
+        end
+    end
+
+    leorv32 #(
+        .RESET_ADDR(32'h00000000),
+        .ADDR_WIDTH(16),
+        .MHARTID(1)
+    ) leorv32_core1 (
+        .clk(clk),
+        .reset(reset_delayed),
+
+        .mem_addr (mem_addr_core1),
+        .mem_wdata(mem_wdata_core1),
+        .mem_wmask(mem_wmask_core1),
+        .mem_rdata(mem_rdata),
+        .mem_rstrb(mem_rstrb_core1),
+        .mem_rbusy(mem_rbusy),
+        .mem_wbusy(mem_wbusy),
+        
+        .mhartid_0(1'b0)
+    );
+
+    // Bus arbitration
+
+    logic mem_arbiter;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_arbiter <= 1'b0;
+        end else begin
+            mem_arbiter = !mem_arbiter;
+        end
+    end
+
+    logic [31: 0] mem_addr_shared;
+    logic [31: 0] mem_wdata_shared;
+    logic [ 3: 0] mem_wmask_shared;
+    logic         mem_rstrb_shared;
+
+    assign mem_addr_shared  = mem_arbiter ? mem_addr_core1 : mem_addr_core0;
+    assign mem_wdata_shared = mem_arbiter ? mem_wdata_core1 : mem_wdata_core0;
+    assign mem_wmask_shared = mem_arbiter ? mem_wmask_core1 : mem_wmask_core0;
+    assign mem_rstrb_shared = mem_arbiter ? mem_rstrb_core1 : mem_rstrb_core0;
+
+    logic [31:0] mem_addr_shared_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_addr_shared_delayed <= 1'b0;
+        end else begin
+            mem_addr_shared_delayed <= mem_addr_shared;
+        end
+    end
+
+    // Memory
+
+    localparam MEMORY_WIDTH = 11;  // 2048 words
+    wire [MEMORY_WIDTH-3:0] ram_word_address = mem_addr_shared[MEMORY_WIDTH-1:2];
+    logic [31:0] memory[0:(2**MEMORY_WIDTH)-1];
+
+    initial begin
+        $readmemh("firmware/firmware.hex", memory);
+    end
+
+    logic [31:0] mem_rdata_memory;
+
+    always_ff @(posedge clk) begin
+        if (mem_wmask_shared[0]) memory[ram_word_address][7:0] <= mem_wdata_shared[7:0];
+        if (mem_wmask_shared[1]) memory[ram_word_address][15:8] <= mem_wdata_shared[15:8];
+        if (mem_wmask_shared[2]) memory[ram_word_address][23:16] <= mem_wdata_shared[23:16];
+        if (mem_wmask_shared[3]) memory[ram_word_address][31:24] <= mem_wdata_shared[31:24];
+        if (mem_rstrb_shared) mem_rdata_memory <= memory[ram_word_address];
+    end
+
+    always_comb begin
+        if (mem_addr_shared_delayed == 16'hBEEF) begin
+            mem_rdata = uart_reg;
+        end else begin
+            mem_rdata = mem_rdata_memory;
+        end
+    end
+
+    assign mem_wbusy = 1'b0;
+    assign mem_rbusy = 1'b0;
+
+    // Blinky
+
+    always @(posedge clk, posedge reset) begin
+        if (reset) begin
+            blink <= 1'b0;
+        end else if (mem_addr_shared == 32'h0000FFFF && (|mem_wmask_shared)) begin
+            blink = mem_wdata_shared[0];
+        end
+    end
+
+    // Uart
+
+    logic mem_rstrb_delayed;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_rstrb_delayed <= 1'b0;
+        end else begin
+            mem_rstrb_delayed <= mem_rstrb_shared;
+        end
+    end
+
+    logic rx_flag;
+    logic [31: 0] uart_reg;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_flag  <= 1'b0;
+            uart_reg <= '0;
+        end else if (!rx_done_delayed && rx_done) rx_flag <= 1'b1;
+        else if (mem_addr_shared == 16'hBEEF && mem_rstrb_shared) rx_flag <= 1'b0;
+
+        uart_reg <= {rx_flag, tx_busy, {22{1'b0}}, rx_received};
+    end
+
+    logic [7:0] rx_received;
+    logic rx_done;
+    logic rx_done_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_done_delayed <= 1'b0;
+        end else begin
+            rx_done_delayed <= rx_done;
+        end
+    end
+
+    my_uart_rx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_rx (
+        .clk(clk),
+        .rst(reset),
+        .rx(uart_rx_sync),
+        .data(rx_received),
+        .valid(rx_done)
+    );
+
+    logic tx_busy;
+
+    my_uart_tx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_tx (
+        .clk(clk),
+        .rst(reset),
+        .data(mem_wdata_shared[7:0]),
+        .start(mem_addr_shared == 16'hBEEF && (|mem_wmask_shared)),
+        .tx(uart_tx),
+        .busy(tx_busy)
+    );
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv b/verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv
new file mode 100644
index 0000000..5ce2ac2
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv
@@ -0,0 +1,442 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module soc #(
+    parameter int FREQUENCY = 40_000_000,
+    parameter int BAUDRATE  = 9600
+) (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+    input clk, // 40 MHz
+    input reset,
+
+    input        uart_rx,
+    output logic uart_tx,
+
+    output logic blink,
+
+    // PMOD DVI TODO
+    output       dvi_clk,    // DVI pixel clock
+    output       dvi_hsync,  // DVI horizontal sync
+    output       dvi_vsync,  // DVI vertical sync
+    output       dvi_de,     // DVI data enable
+    output [3:0] dvi_r,      // 4-bit DVI red
+    output [3:0] dvi_g,      // 4-bit DVI green
+    output [3:0] dvi_b,      // 4-bit DVI blue
+    
+    // Wishbone Port
+    
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+    
+    input port_select
+);
+
+    logic video_clk;
+    assign video_clk = clk;
+
+    // Synchronization
+
+    logic uart_rx_sync;
+
+    synchronizer #(
+        .FF_COUNT(3)
+    ) synchronizer (
+        .clk(clk),
+        .resetn(!reset),
+        .in(uart_rx),
+
+        .out(uart_rx_sync)
+    );
+
+    // Configuration
+
+    localparam SOC_ADDRW = 24;
+    
+    localparam NUM_WMASKS = 4;
+    localparam DATA_WIDTH = 32;
+    localparam ADDR_WIDTH = 11;
+    
+    localparam WRAM_MASK = 8'h00;
+    localparam VRAM_MASK = 8'h01;
+    localparam UART_MASK = 8'h0A;
+    localparam BLINK_MASK = 8'h0F;
+    
+    logic soc_wram_sel;
+    logic soc_vram_sel;
+    logic soc_uart_sel;
+    logic soc_blink_sel;
+    
+    assign soc_wram_sel = mem_addr_shared[23:16] == WRAM_MASK;
+    assign soc_vram_sel = mem_addr_shared[23:16] == VRAM_MASK;
+    assign soc_uart_sel = mem_addr_shared[23:16] == UART_MASK;
+    assign soc_blink_sel = mem_addr_shared[23:16] == BLINK_MASK;
+    
+    logic soc_wram_sel_del;
+    logic soc_vram_sel_del;
+    logic soc_uart_sel_del;
+    logic soc_blink_sel_del;
+    
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            soc_wram_sel_del <= 1'b0;
+            soc_vram_sel_del <= 1'b0;
+            soc_uart_sel_del <= 1'b0;
+            soc_blink_sel_del <= 1'b0;
+        end else begin
+            soc_wram_sel_del <= soc_wram_sel;
+            soc_vram_sel_del <= soc_vram_sel;
+            soc_uart_sel_del <= soc_uart_sel;
+            soc_blink_sel_del <= soc_blink_sel;
+        end
+    end
+    
+    
+
+    logic [SOC_ADDRW-1: 0] mem_addr_core0;
+    logic [31: 0] mem_wdata_core0;
+    logic [ 3: 0] mem_wmask_core0;
+    logic         mem_rstrb_core0;
+
+    logic [SOC_ADDRW-1: 0] mem_addr_core1;
+    logic [31: 0] mem_wdata_core1;
+    logic [ 3: 0] mem_wmask_core1;
+    logic         mem_rstrb_core1;
+
+    logic [31: 0] mem_rdata;
+    logic         mem_rbusy;
+    logic         mem_wbusy;
+
+    // Peripherals have no latency
+    assign mem_wbusy = 1'b0;
+    assign mem_rbusy = 1'b0;
+
+    // CPU
+
+    leorv32 leorv32_core0 (
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),	// User area 1 1.8V power
+        .vssd1(vssd1),	// User area 1 digital ground
+`endif
+        .clk(clk),
+        .reset(reset),
+
+        .mem_addr (mem_addr_core0),
+        .mem_wdata(mem_wdata_core0),
+        .mem_wmask(mem_wmask_core0),
+        .mem_rdata(mem_rdata),
+        .mem_rstrb(mem_rstrb_core0),
+        .mem_rbusy(mem_rbusy),
+        .mem_wbusy(mem_wbusy),
+        
+        .mhartid_0(1'b0)
+    );
+
+    logic reset_delayed;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            reset_delayed <= 1'b1;
+        end else begin
+            reset_delayed <= reset;
+        end
+    end
+
+    leorv32 leorv32_core1 (
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),	// User area 1 1.8V power
+        .vssd1(vssd1),	// User area 1 digital ground
+`endif
+        .clk(1'b0), // TODO core1 is deactivated because of interference, investigate
+        .reset(reset_delayed),
+
+        .mem_addr (mem_addr_core1),
+        .mem_wdata(mem_wdata_core1),
+        .mem_wmask(mem_wmask_core1),
+        .mem_rdata(mem_rdata),
+        .mem_rstrb(mem_rstrb_core1),
+        .mem_rbusy(mem_rbusy),
+        .mem_wbusy(mem_wbusy),
+        
+        .mhartid_0(1'b1)
+    );
+
+    // Bus arbitration
+
+    logic mem_arbiter;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_arbiter <= 1'b0;
+        end else begin
+            mem_arbiter = !mem_arbiter;
+        end
+    end
+
+    logic [SOC_ADDRW-1: 0] mem_addr_shared;
+    logic [31: 0] mem_wdata_shared;
+    logic [ 3: 0] mem_wmask_shared;
+    logic         mem_rstrb_shared;
+
+    assign mem_addr_shared  = mem_arbiter ? mem_addr_core1 : mem_addr_core0;
+    assign mem_wdata_shared = mem_arbiter ? mem_wdata_core1 : mem_wdata_core0;
+    assign mem_wmask_shared = mem_arbiter ? mem_wmask_core1 : mem_wmask_core0;
+    assign mem_rstrb_shared = mem_arbiter ? mem_rstrb_core1 : mem_rstrb_core0;
+
+    logic [31:0] mem_addr_shared_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_addr_shared_delayed <= 1'b0;
+        end else begin
+            mem_addr_shared_delayed <= mem_addr_shared;
+        end
+    end
+    
+    // Wishbone Memory Module
+    
+    logic wb_web;
+    logic [NUM_WMASKS-1:0] wb_wmask;
+    logic [ADDR_WIDTH-1:0] wb_addr;
+    logic [DATA_WIDTH-1:0] wb_din;
+    logic [DATA_WIDTH-1:0] wb_dout;
+    
+    logic periph_select;
+    assign periph_select = wbs_adr_i[31:28] == 4'h3; // From 0x30000000 to 0x3FFFFFFF
+    
+    wb_memory #(
+        .ADDR_WIDTH(ADDR_WIDTH)
+    ) wb_memory_inst (
+
+        // Wishbone port
+        .io_wbs_clk(wb_clk_i),
+        .io_wbs_rst(wb_rst_i),
+        .io_wbs_adr(wbs_adr_i),
+        .io_wbs_datwr(wbs_dat_i),
+        .io_wbs_datrd(wbs_dat_o),
+        .io_wbs_we(wbs_we_i),
+        .io_wbs_sel(wbs_sel_i),
+        .io_wbs_stb(wbs_stb_i && periph_select),
+        .io_wbs_ack(wbs_ack_o),
+        .io_wbs_cyc(wbs_cyc_i && periph_select),
+
+        // Memory Port
+        .web(wb_web),
+        .wmask(wb_wmask),
+        .addr(wb_addr),
+        .din(wb_din),
+        .dout(wb_dout)
+    );
+    
+    // Memory Port Switch
+    
+    mem_port_switch #(
+        .ADDR_WIDTH(ADDR_WIDTH)
+    ) mem_port_switch_inst (
+        .port_select(port_select),
+
+        // Input Memory Port 0 - R/W
+        .input_web0(wb_web),
+        .input_wmask0(wb_wmask),
+        .input_addr0(wb_addr),
+        .input_din0(wb_din),
+        .input_dout0(wb_dout),
+        
+        // Input Memory Port 1 - R/W
+        .input_web1(!(|mem_wmask_shared && soc_wram_sel)),
+        .input_wmask1(mem_wmask_shared),
+        .input_addr1(mem_addr_shared >> 2),
+        .input_din1(mem_wdata_shared),
+        .input_dout1(mem_rdata_memory),
+        
+        // Output Memory Port 0 - R/W
+        .output_web0(wram_web0),
+        .output_wmask0(wram_wmask0),
+        .output_addr0(wram_addr0),
+        .output_din0(wram_din0),
+        .output_dout0(wram_dout0),
+        
+        // Output Memory Port 1 - R
+        .output_addr1(wram_addr1),
+        .output_dout1(wram_dout1)
+    );
+
+    // WRAM Memory
+    
+    // Memory Port 1 - R/W
+    logic wram_web0;
+    logic [NUM_WMASKS-1:0] wram_wmask0;
+    logic [ADDR_WIDTH-1:0] wram_addr0;
+    logic [DATA_WIDTH-1:0] wram_din0;
+    logic [DATA_WIDTH-1:0] wram_dout0;
+    
+    // Memory Port 2 - R
+    logic [ADDR_WIDTH-1:0] wram_addr1;
+    logic [DATA_WIDTH-1:0] wram_dout1;
+
+    logic [31:0] mem_rdata_memory;
+    
+    sram #(
+        .ADDR_WIDTH(ADDR_WIDTH)
+    ) wram (
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),	// User area 1 1.8V power
+        .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    
+        // Port 0: RW
+        .clk0  (clk),
+        .csb0  (1'b0),
+        .web0  (wram_web0),
+        .wmask0(wram_wmask0),
+        .addr0 (wram_addr0),
+        .din0  (wram_din0),
+        .dout0 (wram_dout0),
+
+        // Port 1: R
+        .clk1 (clk),
+        .csb1 (1'b0),
+        .addr1(wram_addr1),
+        .dout1(wram_dout1)
+    );
+
+    // SoC read data
+
+    always_comb begin
+        // VRAM
+        if (soc_vram_sel_del) begin
+            mem_rdata = vram_dout0;
+        // UART
+        end else if (soc_uart_sel_del) begin
+            mem_rdata = uart_reg;
+        // Blink
+        end else if (soc_blink_sel_del) begin
+            mem_rdata = {32{blink}};
+        // WRAM
+        end else begin
+            mem_rdata = mem_rdata_memory;
+        end
+    end
+
+    // Blinky
+
+    always @(posedge clk, posedge reset) begin
+        if (reset) begin
+            blink <= 1'b0;
+        end else if (soc_blink_sel && (|mem_wmask_shared)) begin
+            blink = mem_wdata_shared[0];
+        end
+    end
+
+    // Uart
+
+    logic mem_rstrb_delayed;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_rstrb_delayed <= 1'b0;
+        end else begin
+            mem_rstrb_delayed <= mem_rstrb_shared;
+        end
+    end
+
+    logic rx_flag;
+    logic [31: 0] uart_reg;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_flag  <= 1'b0;
+            uart_reg <= '0;
+        end else if (!rx_done_delayed && rx_done) rx_flag <= 1'b1;
+        else if (soc_uart_sel && mem_rstrb_shared) rx_flag <= 1'b0;
+
+        uart_reg <= {rx_flag, tx_busy, {22{1'b0}}, rx_received};
+    end
+
+    logic [7:0] rx_received;
+    logic rx_done;
+    logic rx_done_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_done_delayed <= 1'b0;
+        end else begin
+            rx_done_delayed <= rx_done;
+        end
+    end
+
+    my_uart_rx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_rx (
+        .clk(clk),
+        .rst(reset),
+        .rx(uart_rx_sync),
+        .data(rx_received),
+        .valid(rx_done)
+    );
+
+    logic tx_busy;
+
+    my_uart_tx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_tx (
+        .clk(clk),
+        .rst(reset),
+        .data(mem_wdata_shared[7:0]),
+        .start(soc_uart_sel && (|mem_wmask_shared)),
+        .tx(uart_tx),
+        .busy(tx_busy)
+    );
+
+    // *** SVGA ***
+
+    logic [3:0] paint_r, paint_g, paint_b;
+    logic horizontal_sync, vertical_sync, enable;
+    logic [31: 0] vram_dout0;
+
+    svga_gen_top svga_gen_top (
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),	// User area 1 1.8V power
+        .vssd1(vssd1),	// User area 1 digital ground
+`endif
+        .reset,
+
+        // VRAM Port
+        .clk,
+        .mem_addr_shared,
+        .mem_wdata_shared,
+        .mem_wmask_shared,
+        .vram_dout0,
+        .soc_vram_sel,
+
+        // SVGA Signals
+        .video_clk,
+        .horizontal_sync,
+        .vertical_sync,
+        .enable,
+        .paint_r,
+        .paint_g,
+        .paint_b
+    );
+
+    assign dvi_hsync = horizontal_sync;
+    assign dvi_vsync = vertical_sync;
+    assign dvi_de = enable;
+    assign dvi_r = paint_r;
+    assign dvi_g = paint_g;
+    assign dvi_b = paint_b;
+    
+    assign dvi_clk = video_clk; // TODO 180° phase
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/rtl/icebreaker_top.sv b/verilog/rtl/leorv-fpga/soc/rtl/icebreaker_top.sv
new file mode 100644
index 0000000..6572133
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/rtl/icebreaker_top.sv
@@ -0,0 +1,65 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module icebreaker_top (
+    input CLK,
+
+    // On-board
+    input RX,
+    output logic TX,
+
+    input BTN_N,
+    output logic LEDR_N,
+    output logic LEDG_N,
+
+    // PMOD 2
+    input BTN1,
+    input BTN2,
+    input BTN3,
+
+    // PMOD DVI
+    output logic       dvi_clk,    // DVI pixel clock
+    output logic       dvi_hsync,  // DVI horizontal sync
+    output logic       dvi_vsync,  // DVI vertical sync
+    output logic       dvi_de,     // DVI data enable
+    output logic [3:0] dvi_r,      // 4-bit DVI red
+    output logic [3:0] dvi_g,      // 4-bit DVI green
+    output logic [3:0] dvi_b       // 4-bit DVI blue
+);
+
+    localparam int FREQUENCY = 12_000_000;
+    localparam int BAUDRATE = 9600;
+
+    logic reset;
+
+    SB_GB reset_buffer (
+        .USER_SIGNAL_TO_GLOBAL_BUFFER(!BTN_N),
+        .GLOBAL_BUFFER_OUTPUT(reset)
+    );
+
+    simple_soc_svga #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) simple_soc_svga (
+        .clk_in(CLK),
+        .reset (reset),
+
+        .uart_rx(RX),
+        .uart_tx(TX),
+
+        .blink(LEDG_N),
+
+        .dvi_clk  (dvi_clk),    // DVI pixel clock
+        .dvi_hsync(dvi_hsync),  // DVI horizontal sync
+        .dvi_vsync(dvi_vsync),  // DVI vertical sync
+        .dvi_de   (dvi_de),     // DVI data enable
+        .dvi_r    (dvi_r),      // 4-bit DVI red
+        .dvi_g    (dvi_g),      // 4-bit DVI green
+        .dvi_b    (dvi_b)       // 4-bit DVI blue
+    );
+
+    assign LEDR_N = 1'b0;
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/rtl/simple_soc.sv b/verilog/rtl/leorv-fpga/soc/rtl/simple_soc.sv
new file mode 100644
index 0000000..a4ffa76
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/rtl/simple_soc.sv
@@ -0,0 +1,194 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module simple_soc #(
+    parameter int FREQUENCY = 12_000_000,
+    parameter int BAUDRATE  = 9600
+) (
+    input clk,
+    input reset,
+
+    input        uart_rx,
+    output logic uart_tx,
+
+    output logic blink
+);
+
+    // Synchronization
+
+    logic uart_rx_sync;
+
+    synchronizer #(
+        .FF_COUNT(3)
+    ) synchronizer (
+        .clk(clk),
+        .resetn(!reset),
+        .in(uart_rx),
+
+        .out(uart_rx_sync)
+    );
+
+    // CPU
+
+    logic [31: 0] mem_addr;
+    logic [31: 0] mem_wdata;
+    logic [ 3: 0] mem_wmask;
+    logic [31: 0] mem_rdata;
+    logic         mem_rstrb;
+    logic         mem_rbusy;
+    logic         mem_wbusy;
+
+    leorv32 #(
+        .RESET_ADDR(32'h00000000),
+        .ADDR_WIDTH(16)
+    ) leorv32 (
+        .clk(clk),
+        .reset(reset),
+
+        .mem_addr (mem_addr),
+        .mem_wdata(mem_wdata),
+        .mem_wmask(mem_wmask),
+        .mem_rdata(mem_rdata),
+        .mem_rstrb(mem_rstrb),
+        .mem_rbusy(mem_rbusy),
+        .mem_wbusy(mem_wbusy),
+        
+        .mhartid_0(1'b0)
+    );
+
+    // Bus arbitration
+
+    logic mem_arbiter;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_arbiter <= 1'b0;
+        end else begin
+            mem_arbiter = !mem_arbiter;
+        end
+    end
+
+    logic [31: 0] mem_addr_shared;
+    logic [31: 0] mem_wdata_shared;
+    logic [ 3: 0] mem_wmask_shared;
+    logic         mem_rstrb_shared;
+
+    assign mem_addr_shared  = mem_arbiter ? 'x : mem_addr;
+    assign mem_wdata_shared = mem_arbiter ? 'x : mem_wdata;
+    assign mem_wmask_shared = mem_arbiter ? 'x : mem_wmask;
+    assign mem_rstrb_shared = mem_arbiter ? 'x : mem_rstrb;
+
+    logic [31:0] mem_addr_shared_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_addr_shared_delayed <= 1'b0;
+        end else begin
+            mem_addr_shared_delayed <= mem_addr_shared;
+        end
+    end
+
+    // Memory
+
+    localparam MEMORY_WIDTH = 11;  // 2048 words
+    wire [MEMORY_WIDTH-3:0] ram_word_address = mem_addr_shared[MEMORY_WIDTH-1:2];
+    logic [31:0] memory[0:(2**MEMORY_WIDTH)-1];
+
+    initial begin
+        $readmemh("firmware/firmware.hex", memory);
+    end
+
+    logic [31:0] mem_rdata_memory;
+
+    always_ff @(posedge clk) begin
+        if (mem_wmask_shared[0]) memory[ram_word_address][7:0] <= mem_wdata_shared[7:0];
+        if (mem_wmask_shared[1]) memory[ram_word_address][15:8] <= mem_wdata_shared[15:8];
+        if (mem_wmask_shared[2]) memory[ram_word_address][23:16] <= mem_wdata_shared[23:16];
+        if (mem_wmask_shared[3]) memory[ram_word_address][31:24] <= mem_wdata_shared[31:24];
+        if (mem_rstrb_shared) mem_rdata_memory <= memory[ram_word_address];
+    end
+
+    always_comb begin
+        if (mem_addr_shared_delayed == 16'hBEEF) begin
+            mem_rdata = uart_reg;
+        end else begin
+            mem_rdata = mem_rdata_memory;
+        end
+    end
+
+    assign mem_wbusy = 1'b0;
+    assign mem_rbusy = 1'b0;
+
+    // Blinky
+
+    always @(posedge clk, posedge reset) begin
+        if (reset) begin
+            blink <= 1'b0;
+        end else if (mem_addr_shared == 32'h0000FFFF && (|mem_wmask_shared)) begin
+            blink = mem_wdata_shared[0];
+        end
+    end
+
+    // Uart
+
+    logic mem_rstrb_delayed;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_rstrb_delayed <= 1'b0;
+        end else begin
+            mem_rstrb_delayed <= mem_rstrb_shared;
+        end
+    end
+
+    logic rx_flag;
+    logic [31: 0] uart_reg;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_flag  <= 1'b0;
+            uart_reg <= '0;
+        end else if (!rx_done_delayed && rx_done) rx_flag <= 1'b1;
+        else if (mem_addr_shared == 16'hBEEF && mem_rstrb) rx_flag <= 1'b0;
+
+        uart_reg <= {rx_flag, tx_busy, {22{1'b0}}, rx_received};
+    end
+
+    logic [7:0] rx_received;
+    logic rx_done;
+    logic rx_done_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_done_delayed <= 1'b0;
+        end else begin
+            rx_done_delayed <= rx_done;
+        end
+    end
+
+    my_uart_rx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_rx (
+        .clk(clk),
+        .rst(reset),
+        .rx(uart_rx_sync),
+        .data(rx_received),
+        .valid(rx_done)
+    );
+
+    logic tx_busy;
+
+    my_uart_tx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_tx (
+        .clk(clk),
+        .rst(reset),
+        .data(mem_wdata_shared[7:0]),
+        .start(mem_addr_shared == 16'hBEEF && (|mem_wmask_shared)),
+        .tx(uart_tx),
+        .busy(tx_busy)
+    );
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/rtl/simple_soc_svga.sv b/verilog/rtl/leorv-fpga/soc/rtl/simple_soc_svga.sv
new file mode 100644
index 0000000..929cfd5
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/rtl/simple_soc_svga.sv
@@ -0,0 +1,293 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module simple_soc_svga #(
+    parameter int FREQUENCY = 12_000_000,
+    parameter int BAUDRATE  = 9600
+) (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+    input clk_in,
+    input reset,
+
+    input        uart_rx,
+    output logic uart_tx,
+
+    output logic blink,
+
+    // PMOD DVI
+    output logic       dvi_clk,    // DVI pixel clock
+    output logic       dvi_hsync,  // DVI horizontal sync
+    output logic       dvi_vsync,  // DVI vertical sync
+    output logic       dvi_de,     // DVI data enable
+    output logic [3:0] dvi_r,      // 4-bit DVI red
+    output logic [3:0] dvi_g,      // 4-bit DVI green
+    output logic [3:0] dvi_b       // 4-bit DVI blue
+);
+
+    // * Given input frequency:        12.000 MHz
+    // * Requested output frequency:   40.000 MHz
+    // * Achieved output frequency:    39.750 MHz
+
+    logic video_clk;
+    logic clk;
+    logic locked;
+
+`ifdef SYNTHESIS
+    SB_PLL40_2_PAD #(
+        .FEEDBACK_PATH("SIMPLE"),
+        .DIVR         (4'b0000),     // DIVR =  0
+        .DIVF         (7'b0110100),  // DIVF = 52
+        .DIVQ         (3'b100),      // DIVQ =  4
+        .FILTER_RANGE (3'b001)       // FILTER_RANGE = 1
+    ) uut (
+        .LOCK  (locked),
+        .RESETB(1'b1),
+        .BYPASS(1'b0),
+
+        .PACKAGEPIN(clk_in),
+        .PLLOUTGLOBALA(clk),  // buffered input clock
+        .PLLOUTGLOBALB(video_clk)  // synthesized clock
+    );
+`else
+    assign video_clk = clk_in;
+    assign clk = clk_in;
+    assign locked = 1'b1;
+`endif
+
+    // Synchronization
+
+    logic uart_rx_sync;
+
+    synchronizer #(
+        .FF_COUNT(3)
+    ) synchronizer (
+        .clk(clk),
+        .resetn(!reset),
+        .in(uart_rx),
+
+        .out(uart_rx_sync)
+    );
+
+    // CPU
+
+    logic [31: 0] mem_addr;
+    logic [31: 0] mem_wdata;
+    logic [ 3: 0] mem_wmask;
+    logic [31: 0] mem_rdata;
+    logic         mem_rstrb;
+    logic         mem_rbusy;
+    logic         mem_wbusy;
+
+    leorv32 #(
+        .RESET_ADDR(32'h00000000),
+        .ADDR_WIDTH(32)  // TODO 24
+    ) leorv32 (
+        .clk(clk),
+        .reset(reset),
+
+        .mem_addr (mem_addr),
+        .mem_wdata(mem_wdata),
+        .mem_wmask(mem_wmask),
+        .mem_rdata(mem_rdata),
+        .mem_rstrb(mem_rstrb),
+        .mem_rbusy(mem_rbusy),
+        .mem_wbusy(mem_wbusy),
+        
+        .mhartid_0(1'b0)
+    );
+
+    // Bus arbitration
+
+    logic mem_arbiter;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_arbiter <= 1'b0;
+        end else begin
+            mem_arbiter <= !mem_arbiter;
+        end
+    end
+
+    logic [31: 0] mem_addr_shared;
+    logic [31: 0] mem_wdata_shared;
+    logic [ 3: 0] mem_wmask_shared;
+    logic         mem_rstrb_shared;
+
+    assign mem_addr_shared  = mem_arbiter ? 'x : mem_addr;
+    assign mem_wdata_shared = mem_arbiter ? 'x : mem_wdata;
+    assign mem_wmask_shared = mem_arbiter ? 'x : mem_wmask;
+    assign mem_rstrb_shared = mem_arbiter ? 'x : mem_rstrb;
+
+    logic [31:0] mem_addr_shared_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_addr_shared_delayed <= 'b0;
+        end else begin
+            mem_addr_shared_delayed <= mem_addr_shared;
+        end
+    end
+
+    // Memory
+
+    localparam MEMORY_WIDTH = 10;  // 1024 words
+    wire [MEMORY_WIDTH-1:0] ram_word_address = mem_addr_shared[MEMORY_WIDTH-1+2:2];
+    logic [31:0] memory[0:(2**MEMORY_WIDTH)-1];
+
+    initial begin
+        $readmemh("firmware/firmware.hex", memory);
+    end
+
+    logic [31:0] mem_rdata_memory;
+
+    always_ff @(posedge clk) begin
+        if (mem_wmask_shared[0] && mem_addr_shared[31:16] == 16'h0000)
+            memory[ram_word_address][7:0] <= mem_wdata_shared[7:0];
+        if (mem_wmask_shared[1] && mem_addr_shared[31:16] == 16'h0000)
+            memory[ram_word_address][15:8] <= mem_wdata_shared[15:8];
+        if (mem_wmask_shared[2] && mem_addr_shared[31:16] == 16'h0000)
+            memory[ram_word_address][23:16] <= mem_wdata_shared[23:16];
+        if (mem_wmask_shared[3] && mem_addr_shared[31:16] == 16'h0000)
+            memory[ram_word_address][31:24] <= mem_wdata_shared[31:24];
+        if (mem_rstrb_shared) mem_rdata_memory <= memory[ram_word_address];
+    end
+
+    always_comb begin
+        if (mem_addr_shared_delayed[31:16] == 16'hDEAD) begin
+            mem_rdata = vram_dout0;
+        end else if (mem_addr_shared_delayed == 32'h0000BEEF) begin
+            mem_rdata = uart_reg;
+        end else begin
+            mem_rdata = mem_rdata_memory;
+        end
+    end
+
+    assign mem_wbusy = 1'b0;
+    assign mem_rbusy = 1'b0;
+
+    // Blinky
+
+    always @(posedge clk, posedge reset) begin
+        if (reset) begin
+            blink <= 1'b0;
+        end else if (mem_addr_shared == 32'h0000FFFF && (|mem_wmask_shared)) begin
+            blink = mem_wdata_shared[0];
+        end
+    end
+
+    // Uart
+
+    logic mem_rstrb_delayed;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            mem_rstrb_delayed <= 1'b0;
+        end else begin
+            mem_rstrb_delayed <= mem_rstrb_shared;
+        end
+    end
+
+    logic rx_flag;
+    logic [31: 0] uart_reg;
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_flag  <= 1'b0;
+            uart_reg <= '0;
+        end else if (!rx_done_delayed && rx_done) rx_flag <= 1'b1;
+        else if (mem_addr_shared == 32'h0000BEEF && mem_rstrb) rx_flag <= 1'b0;
+
+        uart_reg <= {rx_flag, tx_busy, {22{1'b0}}, rx_received};
+    end
+
+    logic [7:0] rx_received;
+    logic rx_done;
+    logic rx_done_delayed;
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            rx_done_delayed <= 1'b0;
+        end else begin
+            rx_done_delayed <= rx_done;
+        end
+    end
+
+    my_uart_rx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_rx (
+        .clk(clk),
+        .rst(reset),
+        .rx(uart_rx_sync),
+        .data(rx_received),
+        .valid(rx_done)
+    );
+
+    logic tx_busy;
+
+    my_uart_tx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_tx (
+        .clk(clk),
+        .rst(reset),
+        .data(mem_wdata_shared[7:0]),
+        .start(mem_addr_shared == 16'hBEEF && (|mem_wmask_shared)),
+        .tx(uart_tx),
+        .busy(tx_busy)
+    );
+
+    // *** SVGA ***
+
+    logic [3:0] paint_r, paint_g, paint_b;
+    logic horizontal_sync, vertical_sync, enable;
+    logic [31: 0] vram_dout0;
+
+    svga_gen_top svga_gen_top (
+        .reset,
+
+        // VRAM Port
+        .clk,
+        .mem_addr_shared,
+        .mem_wdata_shared,
+        .mem_wmask_shared,
+        .vram_dout0,
+
+        // SVGA Signals
+        .video_clk,
+        .horizontal_sync,
+        .vertical_sync,
+        .enable,
+        .paint_r,
+        .paint_g,
+        .paint_b
+    );
+
+`ifdef SYNTHESIS
+
+    // DVI Pmod output
+    SB_IO #(
+        .PIN_TYPE(6'b010100)  // PIN_OUTPUT_REGISTERED
+    ) dvi_signal_io[14:0] (
+        .PACKAGE_PIN({dvi_hsync, dvi_vsync, dvi_de, dvi_r, dvi_g, dvi_b}),
+        .OUTPUT_CLK(video_clk),
+        .D_OUT_0({horizontal_sync, vertical_sync, enable, paint_r, paint_g, paint_b}),
+        .D_OUT_1()
+    );
+
+    // DVI Pmod clock output: 180° out of phase with other DVI signals
+    SB_IO #(
+        .PIN_TYPE(6'b010000)  // PIN_OUTPUT_DDR
+    ) dvi_clk_io (
+        .PACKAGE_PIN(dvi_clk),
+        .OUTPUT_CLK(video_clk),
+        .D_OUT_0(1'b0),
+        .D_OUT_1(1'b1)
+    );
+
+`endif
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/rtl/ulx3s_top.sv b/verilog/rtl/leorv-fpga/soc/rtl/ulx3s_top.sv
new file mode 100644
index 0000000..794d1ec
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/rtl/ulx3s_top.sv
@@ -0,0 +1,31 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module ulx3s_top (
+    input clk_25mhz,
+
+    input  ftdi_txd,
+    output ftdi_rxd,
+
+    input  [6:0] btn,
+    output [7:0] led
+);
+    localparam FREQUENCY = 25_000_000;
+    localparam BAUDRATE = 9600;
+
+    simple_soc #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) simple_soc (
+        .clk  (clk_25mhz),
+        .reset(!btn[0]),
+
+        .uart_rx(ftdi_txd),
+        .uart_tx(ftdi_rxd),
+
+        .blink(led[7])
+    );
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/tb/icebreaker_top_tb.sv b/verilog/rtl/leorv-fpga/soc/tb/icebreaker_top_tb.sv
new file mode 100644
index 0000000..e8d667c
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/tb/icebreaker_top_tb.sv
@@ -0,0 +1,130 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1 ns / 1 ps
+
+module icebreaker_top_tb;
+
+    parameter int CLOCK_PERIOD_NS = 83;  // 12 MHz clock
+    parameter int SER_BIT_PERIOD_NS = 104167;
+
+    initial begin
+        $dumpfile("icebreaker_top_tb.fst");
+        $dumpvars(0, icebreaker_top_tb);
+        for (int i = 0; i < 32; i++) $dumpvars(0, icebreaker_top.simple_soc_svga.leorv32.regs[i]);
+        //for (int i=0;i<32;i++) $dumpvars(0, icebreaker_top.simple_soc_svga.leorv32_core1.regs[i]);
+    end
+
+    logic led_r;
+    logic led_g;
+
+    logic ser_tx;
+    logic ser_rx;
+
+    logic button_run;
+    logic button_step;
+    logic button_stop;
+
+    logic clk = 0;
+    always #(CLOCK_PERIOD_NS / 2) clk = !clk;
+
+    logic resetn;
+
+    initial begin
+        resetn = 0;
+        button_run = 0;
+        button_step = 0;
+        button_stop = 0;
+        ser_rx = 1;
+
+        $display("Starting simulation.");
+
+        #(CLOCK_PERIOD_NS * 2);
+        resetn = 1;
+        button_run = 1;
+
+        #(CLOCK_PERIOD_NS * 300);
+        send_byte_ser("!");
+        #(CLOCK_PERIOD_NS * 60000);
+
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+        #(CLOCK_PERIOD_NS * 60000);
+
+
+        $display("Completed simulation.");
+        $finish;
+    end
+
+    icebreaker_top icebreaker_top (
+        .CLK(clk),
+
+        .TX(ser_tx),
+        .RX(ser_rx),
+
+        .BTN1(button_run),
+        .BTN2(button_step),
+        .BTN3(button_stop),
+
+        .LEDR_N(led_r),
+        .LEDG_N(led_g),
+        .BTN_N (resetn)
+    );
+
+    logic [7:0] recv_byte = 0;
+
+    always @(negedge ser_tx) begin
+        read_byte_ser;
+    end
+
+    task automatic read_byte_ser;
+        #(SER_BIT_PERIOD_NS / 2);  // Wait half baud
+        if ((ser_tx == 0)) begin
+
+            #SER_BIT_PERIOD_NS;
+
+            // Read data LSB first
+            for (int j = 0; j < 8; j++) begin
+                recv_byte[j] = ser_tx;
+                #SER_BIT_PERIOD_NS;
+            end
+
+            if ((ser_tx == 1)) begin
+
+                //$write(colors::Green);
+                $display("leorv32 --> uart: 0x%h '%c'", recv_byte, recv_byte);
+                //$write(colors::None);
+            end
+        end
+    endtask
+
+    task automatic send_byte_ser(input bit [7:0] data);
+        //$write(colors::Blue);
+        $display("uart --> leorv32: 0x%h '%c'", data, data);
+        //$write(colors::None);
+
+        // Start bit
+        ser_rx = 0;
+        #SER_BIT_PERIOD_NS;
+
+        // Send data LSB first
+        for (int i = 0; i < 8; i++) begin
+            ser_rx = data[i];
+            #SER_BIT_PERIOD_NS;
+        end
+
+        // Stop bit
+        ser_rx = 1;
+        #SER_BIT_PERIOD_NS;
+    endtask
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/soc/tb/ulx3s_top_tb.sv b/verilog/rtl/leorv-fpga/soc/tb/ulx3s_top_tb.sv
new file mode 100644
index 0000000..8251a6b
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/soc/tb/ulx3s_top_tb.sv
@@ -0,0 +1,56 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1 ns / 1 ps
+
+module ulx3s_top_tb;
+
+    parameter int CLOCK_PERIOD_NS = 40;  // 25 MHz clock
+
+    initial begin
+        $dumpfile("ulx3s_top_tb.fst");
+        $dumpvars(0, ulx3s_top_tb);
+        for (int i = 0; i < 32; i++) $dumpvars(0, ulx3s_top.simple_soc.leorv32.regs[i]);
+    end
+
+    logic [7:0] leds;
+
+    logic ser_tx;
+    logic ser_rx;
+
+    logic [6:0] buttons;
+
+    logic clk = 0;
+    always #(CLOCK_PERIOD_NS / 2) clk = !clk;
+
+    logic resetn;
+
+    assign buttons[0]   = resetn;
+    assign buttons[6:1] = '1;
+
+    initial begin
+        resetn = 1'b0;
+        ser_rx = 1'b1;
+
+        $display("Starting simulation.");
+
+        #(CLOCK_PERIOD_NS * 2);
+        resetn = 1'b1;
+        #(CLOCK_PERIOD_NS * 3000);
+
+        $display("Completed simulation.");
+        $finish;
+    end
+
+    ulx3s_top ulx3s_top (
+        .clk_25mhz(clk),
+
+        .ftdi_rxd(ser_tx),
+        .ftdi_txd(ser_rx),
+
+        .btn(buttons),
+
+        .led(leds)
+    );
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/sram/rtl/sram.sv b/verilog/rtl/leorv-fpga/sram/rtl/sram.sv
new file mode 100644
index 0000000..a7eb276
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/sram/rtl/sram.sv
@@ -0,0 +1,246 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module sram #(
+    parameter NUM_WMASKS = 4,
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 11,
+    parameter INIT_F = ""
+) (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+
+    // Port 0: RW
+    input clk0,
+    input csb0,
+    input web0,
+    input [NUM_WMASKS-1:0] wmask0,
+    input [ADDR_WIDTH-1:0] addr0,
+    input [DATA_WIDTH-1:0] din0,
+    output [DATA_WIDTH-1:0] dout0,
+
+    // Port 1: R
+    input clk1,
+    input csb1,
+    input [ADDR_WIDTH-1:0] addr1,
+    output [DATA_WIDTH-1:0] dout1
+);
+
+`define SKY130
+
+`ifdef SKY130
+
+    localparam OPENRAM_ADDR_WIDTH = 9;
+
+    //11 - 9 = 2 -> 2^2 = 4 instances
+
+    localparam NUM_INSTANCES = 2**(ADDR_WIDTH - OPENRAM_ADDR_WIDTH); //11 - 9 = 2 -> 2^2 = 4 instances
+
+    initial begin
+        $display("NUM_INSTANCES %d", NUM_INSTANCES);
+    end
+
+    logic [NUM_INSTANCES-1:0] select_instance_0;
+    logic [NUM_INSTANCES-1:0] select_instance_1;
+
+    logic [NUM_INSTANCES*DATA_WIDTH-1:0] select_dout0;
+    logic [NUM_INSTANCES*DATA_WIDTH-1:0] select_dout1;
+
+
+    generate
+        if (ADDR_WIDTH > OPENRAM_ADDR_WIDTH) begin
+            assign select_instance_0 = 1'b1 << (addr0[ADDR_WIDTH-1:OPENRAM_ADDR_WIDTH]);  // addr0[10:9]
+            assign select_instance_1 = 1'b1 << (addr1[ADDR_WIDTH-1:OPENRAM_ADDR_WIDTH]);  // addr1[10:9]
+        end else begin
+            assign select_instance_0 = 1'b1;
+            assign select_instance_1 = 1'b1;
+        end
+    endgenerate
+
+
+    initial begin
+        //$monitor("select_instance_0 %b address %b", select_instance_0, addr0);
+        //$monitor("addr0[ADDR_WIDTH-1:OPENRAM_ADDR_WIDTH] %b", addr0[ADDR_WIDTH-1:OPENRAM_ADDR_WIDTH]);
+    end
+
+    // TODO generate does not seem to work with the PDN
+    /*generate
+        genvar i;
+        for (i = 0; i < NUM_INSTANCES; i++) begin : memory
+            sky130_sram_2kbyte_1rw1r_32x512_8 sky130_sram_2kbyte_1rw1r_32x512_8 (
+
+`ifdef USE_POWER_PINS
+                .vccd1(vccd1),  // User area 1 1.8V power
+                .vssd1(vssd1),  // User area 1 digital ground
+`endif
+
+                // Port 0: RW
+                .clk0  (clk0),
+                .csb0  (!select_instance_0[i] || csb0),
+                .web0  (web0),
+                .wmask0(wmask0),
+                .addr0 (addr0[OPENRAM_ADDR_WIDTH-1:0]),
+                .din0  (din0),
+                .dout0 (select_dout0[i*DATA_WIDTH+:DATA_WIDTH]),
+
+                // Port 1: R
+                .clk1 (clk1),
+                .csb1 (!select_instance_1[i] || csb1),
+                .addr1(addr1[OPENRAM_ADDR_WIDTH-1:0]),
+                .dout1(select_dout1[i*DATA_WIDTH+:DATA_WIDTH])
+            );
+        end
+    endgenerate*/
+    
+    sky130_sram_2kbyte_1rw1r_32x512_8 mem0 (
+
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),  // User area 1 1.8V power
+        .vssd1(vssd1),  // User area 1 digital ground
+`endif
+
+        // Port 0: RW
+        .clk0  (clk0),
+        .csb0  (!select_instance_0[0] || csb0),
+        .web0  (web0),
+        .wmask0(wmask0),
+        .addr0 (addr0[OPENRAM_ADDR_WIDTH-1:0]),
+        .din0  (din0),
+        .dout0 (select_dout0[0*DATA_WIDTH+:DATA_WIDTH]),
+
+        // Port 1: R
+        .clk1 (clk1),
+        .csb1 (!select_instance_1[0] || csb1),
+        .addr1(addr1[OPENRAM_ADDR_WIDTH-1:0]),
+        .dout1(select_dout1[0*DATA_WIDTH+:DATA_WIDTH])
+        
+    );
+        
+    sky130_sram_2kbyte_1rw1r_32x512_8 mem1 (
+
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),  // User area 1 1.8V power
+        .vssd1(vssd1),  // User area 1 digital ground
+`endif
+
+        // Port 0: RW
+        .clk0  (clk0),
+        .csb0  (!select_instance_0[1] || csb0),
+        .web0  (web0),
+        .wmask0(wmask0),
+        .addr0 (addr0[OPENRAM_ADDR_WIDTH-1:0]),
+        .din0  (din0),
+        .dout0 (select_dout0[1*DATA_WIDTH+:DATA_WIDTH]),
+
+        // Port 1: R
+        .clk1 (clk1),
+        .csb1 (!select_instance_1[1] || csb1),
+        .addr1(addr1[OPENRAM_ADDR_WIDTH-1:0]),
+        .dout1(select_dout1[1*DATA_WIDTH+:DATA_WIDTH])
+        
+    );
+        
+    sky130_sram_2kbyte_1rw1r_32x512_8 mem2 (
+
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),  // User area 1 1.8V power
+        .vssd1(vssd1),  // User area 1 digital ground
+`endif
+
+        // Port 0: RW
+        .clk0  (clk0),
+        .csb0  (!select_instance_0[2] || csb0),
+        .web0  (web0),
+        .wmask0(wmask0),
+        .addr0 (addr0[OPENRAM_ADDR_WIDTH-1:0]),
+        .din0  (din0),
+        .dout0 (select_dout0[2*DATA_WIDTH+:DATA_WIDTH]),
+
+        // Port 1: R
+        .clk1 (clk1),
+        .csb1 (!select_instance_1[2] || csb1),
+        .addr1(addr1[OPENRAM_ADDR_WIDTH-1:0]),
+        .dout1(select_dout1[2*DATA_WIDTH+:DATA_WIDTH])
+        
+    );
+        
+    sky130_sram_2kbyte_1rw1r_32x512_8 mem3 (
+
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),  // User area 1 1.8V power
+        .vssd1(vssd1),  // User area 1 digital ground
+`endif
+
+        // Port 0: RW
+        .clk0  (clk0),
+        .csb0  (!select_instance_0[3] || csb0),
+        .web0  (web0),
+        .wmask0(wmask0),
+        .addr0 (addr0[OPENRAM_ADDR_WIDTH-1:0]),
+        .din0  (din0),
+        .dout0 (select_dout0[3*DATA_WIDTH+:DATA_WIDTH]),
+
+        // Port 1: R
+        .clk1 (clk1),
+        .csb1 (!select_instance_1[3] || csb1),
+        .addr1(addr1[OPENRAM_ADDR_WIDTH-1:0]),
+        .dout1(select_dout1[3*DATA_WIDTH+:DATA_WIDTH])
+        
+    );
+
+    generate
+        if (ADDR_WIDTH > OPENRAM_ADDR_WIDTH) begin
+            assign dout0 = select_dout0[addr0[ADDR_WIDTH-1:OPENRAM_ADDR_WIDTH]*DATA_WIDTH+:DATA_WIDTH];
+            assign dout1 = select_dout1[addr1[ADDR_WIDTH-1:OPENRAM_ADDR_WIDTH]*DATA_WIDTH+:DATA_WIDTH];
+        end else begin
+            assign dout0 = select_dout0[DATA_WIDTH:0];
+            assign dout1 = select_dout1[DATA_WIDTH:0];
+        end
+    endgenerate
+
+`else
+
+    localparam RAM_DEPTH = 1 << ADDR_WIDTH;
+    logic [DATA_WIDTH-1:0] mem[RAM_DEPTH];
+
+    initial begin
+        if (INIT_F != 0) begin
+            $display("Initializing BRAM with: '%s'", INIT_F);
+            $readmemh(INIT_F, mem);
+        end
+    end
+
+    // Memory Write Block Port 0
+    // Write Operation : When web0 = 0, csb0 = 0
+    always_ff @(posedge clk0) begin
+        if (!csb0 && !web0) begin
+            if (wmask0[0]) mem[addr0][7:0] <= din0[7:0];
+            if (wmask0[1]) mem[addr0][15:8] <= din0[15:8];
+            if (wmask0[2]) mem[addr0][23:16] <= din0[23:16];
+            if (wmask0[3]) mem[addr0][31:24] <= din0[31:24];
+        end
+    end
+
+    // Memory Read Block Port 0
+    // Read Operation : When web0 = 1, csb0 = 0
+    always_ff @(posedge clk0) begin
+        if (!csb0 && web0) begin
+            dout0 <= mem[addr0];
+        end
+    end
+
+    // Memory Read Block Port 1
+    // Read Operation : When csb1 = 0
+    always_ff @(posedge clk1) begin
+        if (!csb1) begin
+            dout1 <= mem[addr1];
+        end
+    end
+
+`endif
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv b/verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv
new file mode 100644
index 0000000..31ca603
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv
@@ -0,0 +1,95 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module svga_gen (
+    input reset,
+    input video_clk, // 40 MHz for SVGA
+
+    output logic signed [10:0] screen_x,  // -1024/1023
+    output logic signed [10:0] screen_y,  // -1024/1023
+
+    output logic horizontal_enable,
+    output logic vertical_enable,
+    output logic enable,
+
+    output logic horizontal_pulse,
+    output logic vertical_pulse,
+
+    output logic horizontal_sync,
+    output logic vertical_sync,
+
+    output logic frame
+);
+    localparam FREQUENCY = 40_000_000;
+    localparam WIDTH = 800;
+    localparam HEIGHT = 600;
+
+    localparam H_FRONT_PORCH = 40;
+    localparam H_SYNC_WIDTH = 128;
+    localparam H_BACK_PORCH = 88;
+
+    localparam V_FRONT_PORCH = 1;
+    localparam V_SYNC_WIDTH = 4;
+    localparam V_BACK_PORCH = 23;
+
+    logic signed [10:0] tmp_x; // -1024/1023
+    logic signed [10:0] tmp_y; // -1024/1023
+
+    always_ff @(posedge video_clk, posedge reset) begin
+        if (reset) begin
+            tmp_x <= 0 - H_FRONT_PORCH;
+            tmp_y <= 0 - V_FRONT_PORCH;
+
+            screen_x <= 0 - H_FRONT_PORCH;
+            screen_y <= 0 - V_FRONT_PORCH;
+            frame <= 1'b0;
+        end else begin
+            frame <= 1'b0;
+            tmp_x <= tmp_x + 1;
+
+            // Have we reached the right side?
+            if (tmp_x >= WIDTH + H_SYNC_WIDTH + H_BACK_PORCH - 1) begin
+                tmp_x <= 0 - H_FRONT_PORCH;
+                tmp_y <= tmp_y + 1;
+
+                // Have we reached the last line?
+                if (tmp_y >= HEIGHT + V_SYNC_WIDTH + V_BACK_PORCH - 1) begin
+                    tmp_y <= 0 - V_FRONT_PORCH;
+                    frame <= 1'b1;
+                end
+
+            end
+
+            // Delay coordinates to sync with other signals
+            screen_x <= tmp_x;
+            screen_y <= tmp_y;
+        end
+    end
+
+    always_ff @(posedge video_clk, posedge reset) begin
+        if (reset) begin
+            horizontal_sync <= '0;
+            vertical_sync <= '0;
+
+            horizontal_enable <= '0;
+            vertical_enable <= '0;
+            enable <= '0;
+
+            horizontal_pulse <= '0;
+            vertical_pulse <= '0;
+        end else begin
+            horizontal_sync <= tmp_x >= WIDTH && tmp_x < (WIDTH + H_SYNC_WIDTH);
+            vertical_sync <= tmp_y >= HEIGHT && tmp_y < (HEIGHT + V_SYNC_WIDTH);
+
+            horizontal_enable <= tmp_x >= 0 && tmp_x < WIDTH;
+            vertical_enable <= tmp_y >= 0 && tmp_y < HEIGHT;
+            enable <= tmp_x >= 0 && tmp_x < WIDTH && tmp_y >= 0 && tmp_y < HEIGHT;
+
+            horizontal_pulse <= tmp_x == 0;
+            vertical_pulse <= (tmp_x == 0 && tmp_y == 0);
+        end
+    end
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv b/verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv
new file mode 100644
index 0000000..04a69db
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv
@@ -0,0 +1,162 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module svga_gen_top #(
+    parameter bit [12:0] FRAME_BUFFER_START = 0 // 75/2*100-1;
+) (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+
+    input reset,
+
+    // VRAM Port
+    input clk,
+    input [31: 0] mem_addr_shared,
+    input [31: 0] mem_wdata_shared,
+    input [ 3: 0] mem_wmask_shared,
+    output [31: 0] vram_dout0,
+    input soc_vram_sel,
+
+    // SVGA Signals
+    input video_clk,
+    output horizontal_sync,
+    output vertical_sync,
+    output enable,
+    output [ 3: 0] paint_r,
+    output [ 3: 0] paint_g,
+    output [ 3: 0] paint_b
+);
+
+    logic signed [10:0] screen_x; // -1024/1023
+    logic signed [10:0] screen_y; // -1024/1023
+
+    logic frame;
+
+    svga_gen svga_gen (
+        .reset,
+        .video_clk,  // 40 MHz for SVGA
+
+        .screen_x,  // -1024/1023
+        .screen_y,  // -1024/1023
+
+        .horizontal_enable(),
+        .vertical_enable(),
+        .enable,
+
+        .horizontal_pulse(),
+        .vertical_pulse(),
+
+        .horizontal_sync,
+        .vertical_sync,
+
+        .frame
+    );
+
+    // The current address in the framebuffer
+    logic [12:0] fb_addr_read;
+
+    // This is needed if we don't read from bram
+    logic [12:0] fb_addr_read_delayed;
+
+    // TODO prescaler determine actual screen size
+    // make configurable?
+
+    // WIDTH = 100
+    // HEIGHT = 75
+    logic [2:0] prescaler_x;
+    logic [2:0] prescaler_y;
+
+    logic [12:0] fb_addr_stored;
+    logic read_fb;
+
+    localparam LAT = 3;  // read_fb+1, BRAM+1, color+1
+
+    always_ff @(posedge video_clk) begin
+        if (reset || frame) begin  // reset address at start of frame
+            fb_addr_read         <= FRAME_BUFFER_START;
+            fb_addr_stored       <= FRAME_BUFFER_START;
+            fb_addr_read_delayed <= FRAME_BUFFER_START;
+            prescaler_x          <= '0;
+            prescaler_y          <= '0;
+            read_fb              <= '0;
+        end else begin
+            read_fb <= (screen_y >= 0 && screen_y < (600) && screen_x >= -LAT && screen_x < (800)-LAT);
+            fb_addr_read_delayed <= fb_addr_read;
+
+            // Inside painting area
+            if (read_fb) begin
+                prescaler_x <= prescaler_x + 1;
+
+                // Reached end of pixel horizontally
+                if (&prescaler_x) begin
+
+                    // Reached end of line
+                    if (screen_x == 800 - LAT) begin
+                        prescaler_y <= prescaler_y + 1;
+
+                        // Reached end of pixel vertically, store new line address
+                        if (&prescaler_y) begin
+                            fb_addr_stored <= fb_addr_read + 1;
+                            fb_addr_read   <= fb_addr_read + 1;
+                            // If not end of pixel, restore line address
+                        end else begin
+                            fb_addr_read <= fb_addr_stored;
+                        end
+                        // Else just incrment the address
+                    end else begin
+                        fb_addr_read <= fb_addr_read + 1;
+                    end
+                end
+            end
+        end
+    end
+
+    logic [31:0] vram_dout1;
+
+    sram #(
+        .ADDR_WIDTH(11),
+        .INIT_F("images/kathi.hex")
+    ) vram (
+`ifdef USE_POWER_PINS
+        .vccd1(vccd1),	// User area 1 1.8V supply
+        .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    
+        // Port 0: RW
+        .clk0  (clk),
+        .csb0  (1'b0),
+        .web0  (!(|mem_wmask_shared && soc_vram_sel)),
+        .wmask0(mem_wmask_shared),
+        .addr0 (mem_addr_shared >> 2),
+        .din0  (mem_wdata_shared),
+        .dout0 (vram_dout0),
+
+        // Port 1: R
+        .clk1 (video_clk),
+        .csb1 (1'b0),
+        .addr1(fb_addr_read >> 2),
+        .dout1(vram_dout1)
+    );
+
+    logic [7:0] color;
+
+    // TODO palettes
+    always_ff @(posedge video_clk) begin
+        case (fb_addr_read_delayed[1:0])
+            2'b00: color <= vram_dout1[ 7: 0];
+            2'b01: color <= vram_dout1[15: 8];
+            2'b10: color <= vram_dout1[23:16];
+            2'b11: color <= vram_dout1[31:24];
+        endcase
+    end
+
+    assign paint_r = enable ? {color[2:0], color[0]} : 4'b0000;
+    assign paint_g = enable ? {color[5:3], color[3]} : 4'b0000;
+    assign paint_b = enable ? {color[7:6], color[6], color[6]} : 4'b0000;
+
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/svga/tb/svga_gen_top_tb.sv b/verilog/rtl/leorv-fpga/svga/tb/svga_gen_top_tb.sv
new file mode 100644
index 0000000..e68ddb6
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/svga/tb/svga_gen_top_tb.sv
@@ -0,0 +1,62 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns/1ps
+
+module svga_gen_top_tb;
+    
+    logic reset = 1;
+    
+    initial begin
+        $dumpfile("svga.fst");
+        $dumpvars(0, svga_gen_top_tb);
+        #10;
+        reset = 0;
+        #(4*600*800);
+        $finish;
+    end
+    
+    logic btn1, btn2, btn3;
+    
+    initial begin
+        #10;
+        btn1 = 1'b0;
+        btn2 = 1'b0;
+        btn3 = 1'b0;
+        #10;
+        //btn1 = 1'b1;
+    end
+    
+    logic clk = 1'b0;
+    
+    always begin
+        #1 clk = !clk;
+    end
+    
+    logic ser_tx, ser_rx;
+    logic led_r, led_g;
+    
+    svga_gen_top svga_gen_top (
+        .CLK(clk),
+
+        .TX(ser_tx),
+        .RX(ser_rx),
+
+        .BTN1(btn1),
+        .BTN2(btn2),
+        .BTN3(btn3),
+
+        .LEDR_N(led_r),
+        .LEDG_N(led_g),
+        .BTN_N (!reset),
+
+        .dvi_clk(),      // DVI pixel clock
+        .dvi_hsync(),    // DVI horizontal sync
+        .dvi_vsync(),    // DVI vertical sync
+        .dvi_de(),       // DVI data enable
+        .dvi_r(),  // 4-bit DVI red
+        .dvi_g(),  // 4-bit DVI green
+        .dvi_b()   // 4-bit DVI blue
+    );
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv b/verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv
new file mode 100644
index 0000000..d85eedf
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv
@@ -0,0 +1,110 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module my_uart_rx #(
+    parameter int BAUDRATE,
+    parameter int FREQUENCY
+) (
+    input logic clk,
+    input logic rst,
+    input logic rx,
+    output logic [7:0] data,
+    output logic valid
+);
+    localparam int WAIT_CYCLES = FREQUENCY / BAUDRATE;
+
+    logic [$clog2(WAIT_CYCLES+1)-1 : 0] counter;
+
+    typedef enum {
+        ST_IDLE,
+        ST_CHECK_START,
+        ST_READ_DATA,
+        ST_CHECK_STOP
+    } my_uart_states_t;
+
+    my_uart_states_t cur_state, next_state;
+
+    logic transitioning;
+    assign transitioning = cur_state != next_state;
+
+    logic [2:0] current_bit;
+
+    always_ff @(posedge clk, posedge rst) begin
+        if (rst) cur_state <= ST_IDLE;
+        else cur_state <= next_state;
+    end
+
+    always_comb begin
+        next_state = cur_state;
+        case (cur_state)
+            ST_IDLE: begin
+                if (rx == 1'b0) next_state = ST_CHECK_START;
+            end
+            ST_CHECK_START: begin
+                if (counter == 0) begin
+                    if (rx == 1'b0) next_state = ST_READ_DATA;
+                    else next_state = ST_IDLE;
+                end
+            end
+            ST_READ_DATA: begin
+                if (counter == 0 && current_bit == 7) next_state = ST_CHECK_STOP;
+            end
+            ST_CHECK_STOP: begin
+                if (counter == 0) next_state = ST_IDLE;
+            end
+            default: next_state = ST_IDLE;
+        endcase
+    end
+
+    always_ff @(posedge clk, posedge rst) begin
+        if (rst) begin
+            counter <= '0;
+            current_bit <= '0;
+            data <= 1'b0;
+            valid <= 1'b0;
+        end else begin
+            valid <= 1'b0;
+
+            case (cur_state)
+                ST_IDLE: begin
+                    counter <= '0;
+
+                    if (transitioning) counter <= WAIT_CYCLES / 2;
+                end
+                ST_CHECK_START: begin
+                    counter <= counter - 1;
+
+                    if (transitioning) begin
+                        counter <= WAIT_CYCLES;
+                        current_bit <= '0;
+                    end
+                end
+                ST_READ_DATA: begin
+                    counter <= counter - 1;
+
+                    if (counter == 0) begin
+                        data[current_bit] <= rx;
+                        current_bit <= current_bit + 1;
+                        counter <= WAIT_CYCLES;
+                    end
+
+                    if (transitioning) counter <= WAIT_CYCLES;
+                end
+                ST_CHECK_STOP: begin
+                    counter <= counter - 1;
+
+                    if (transitioning) begin
+                        if (rx == 1'b1) valid <= 1'b1;
+                    end
+                end
+                default: begin
+                    data  <= 'x;
+                    valid <= 'x;
+                end
+            endcase
+        end
+    end
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv b/verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv
new file mode 100644
index 0000000..bc7f6f2
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv
@@ -0,0 +1,114 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module my_uart_tx #(
+    parameter int BAUDRATE,
+    parameter int FREQUENCY
+) (
+    input logic clk,
+    input logic rst,
+    input logic [7:0] data,
+    input logic start,
+    output logic tx,
+    output logic busy
+);
+    localparam int WAIT_CYCLES = FREQUENCY / BAUDRATE;
+
+    logic [$clog2(WAIT_CYCLES+1)-1 : 0] counter;
+
+    typedef enum {
+        ST_IDLE,
+        ST_SEND_START,
+        ST_SEND_DATA,
+        ST_SEND_STOP
+    } my_uart_states_t;
+
+    my_uart_states_t cur_state, next_state;
+
+    logic transitioning;
+    assign transitioning = cur_state != next_state;
+
+    logic [2:0] current_bit;
+    logic [7:0] data_stored;
+
+    always_ff @(posedge clk, posedge rst) begin
+        if (rst) cur_state <= ST_IDLE;
+        else cur_state <= next_state;
+    end
+
+    always_comb begin
+        next_state = cur_state;
+        case (cur_state)
+            ST_IDLE: begin
+                if (start == 1'b1) next_state = ST_SEND_START;
+            end
+            ST_SEND_START: begin
+                if (counter == 0) begin
+                    next_state = ST_SEND_DATA;
+                end
+            end
+            ST_SEND_DATA: begin
+                if (counter == 0 && current_bit == 7) next_state = ST_SEND_STOP;
+            end
+            ST_SEND_STOP: begin
+                if (counter == 0) next_state = ST_IDLE;
+            end
+            default: next_state = ST_IDLE;
+        endcase
+    end
+
+    always_ff @(posedge clk, posedge rst) begin
+        if (rst) begin
+            counter <= '0;
+            current_bit <= '0;
+            busy <= 1'b0;
+        end else begin
+            busy <= 1'b1;
+
+            case (cur_state)
+                ST_IDLE: begin
+                    tx <= 1'b1;
+                    counter <= '0;
+                    busy <= 1'b0;
+
+                    if (transitioning) begin
+                        data_stored <= data;
+                        counter <= WAIT_CYCLES;
+                        busy <= 1'b1;
+                    end
+                end
+                ST_SEND_START: begin
+                    tx <= 1'b0;
+                    counter <= counter - 1;
+
+                    if (transitioning) begin
+                        counter <= WAIT_CYCLES;
+                        current_bit <= 0;
+                    end
+                end
+                ST_SEND_DATA: begin
+                    tx <= data_stored[current_bit];
+                    counter <= counter - 1;
+
+                    if (counter == 0) begin
+                        current_bit <= current_bit + 1;
+                        counter <= WAIT_CYCLES;
+                    end
+
+                    if (transitioning) counter <= WAIT_CYCLES;
+                end
+                ST_SEND_STOP: begin
+                    tx <= 1'b1;
+                    counter <= counter - 1;
+                end
+                default: begin
+                    busy <= 'x;
+                    tx   <= 'x;
+                end
+            endcase
+        end
+    end
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/uart/tb/my_uart_rx_tb.sv b/verilog/rtl/leorv-fpga/uart/tb/my_uart_rx_tb.sv
new file mode 100644
index 0000000..a7658ab
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/uart/tb/my_uart_rx_tb.sv
@@ -0,0 +1,80 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+module my_uart_rx_tb ();
+    timeunit 1ns;
+    timeprecision 1ps;
+
+    parameter int FREQUENCY = 1_000_000;
+    parameter int BAUDRATE = 9600;
+    parameter int BAUDRATE_WAIT = 1.0 / BAUDRATE * 1e9;
+
+    logic clk;
+    logic rst;
+
+    initial begin
+        $dumpfile("uart_rx.vcd");
+        $dumpvars(0, my_uart_rx_tb);
+    end
+
+    initial begin
+        clk <= 0;
+        rst <= 1;
+        #10;
+        rst <= 0;
+    end
+
+    always begin
+        #(1.0 / FREQUENCY / 2 * 1e9);
+        clk <= ~clk;
+    end
+
+    logic rx;
+    logic [7:0] data;
+    logic valid;
+
+    my_uart_rx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_rx (
+        .clk(clk),
+        .rst(rst),
+        .rx(rx),
+        .data(data),
+        .valid(valid)
+    );
+
+    task automatic send_byte_ser(input bit [7:0] data);
+        $display("sending: %h ", data);
+
+        // Start bit
+        rx = 0;
+        #BAUDRATE_WAIT;
+
+        // Send data LSB first
+        for (int i = 0; i < 8; i++) begin
+            rx = data[i];
+            #BAUDRATE_WAIT;
+        end
+
+        // Stop bit
+        rx = 1;
+        #BAUDRATE_WAIT;
+    endtask
+
+    bit [7:0] random_value;
+
+    initial begin
+        rx = 1;
+
+        for (int i = 0; i < 10; i++) begin
+            #BAUDRATE_WAIT;
+            random_value = $urandom_range(0, 255);
+            send_byte_ser(random_value);
+            assert (random_value == data)
+            else $display("%h != %h", random_value, data);
+        end
+
+        $finish;
+    end
+endmodule
diff --git a/verilog/rtl/leorv-fpga/uart/tb/my_uart_tx_tb.sv b/verilog/rtl/leorv-fpga/uart/tb/my_uart_tx_tb.sv
new file mode 100644
index 0000000..56ecbeb
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/uart/tb/my_uart_tx_tb.sv
@@ -0,0 +1,98 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+module my_uart_tx_tb ();
+    timeunit 1ns;
+    timeprecision 1ps;
+    
+    parameter int FREQUENCY = 1_000_000;
+    parameter int BAUDRATE = 9600;
+    parameter int BAUDRATE_WAIT = 1.0 / BAUDRATE * 1e9;
+
+    logic clk;
+    logic rst;
+
+    initial begin
+        $dumpfile("uart_tx.vcd");
+        $dumpvars(0, my_uart_tx_tb);
+    end
+
+    initial begin
+        clk <= 0;
+        rst <= 1;
+        #10;
+        rst <= 0;
+    end
+
+    always begin
+        #(1.0 / FREQUENCY / 2 * 1e9);
+        clk <= ~clk;
+    end
+
+    logic tx;
+    logic [7:0] data;
+    logic start;
+    logic busy;
+
+    my_uart_tx #(
+        .FREQUENCY(FREQUENCY),
+        .BAUDRATE (BAUDRATE)
+    ) my_uart_tx (
+        .clk(clk),
+        .rst(rst),
+        .data(data),
+        .start(start),
+        .tx(tx),
+        .busy(busy)
+    );
+
+    logic [7:0] recv_byte = 0;
+
+    always @(negedge tx) begin
+        read_byte_ser;
+    end
+
+    bit [7:0] random_value;
+
+    initial begin
+        start = 0;
+        data  = 0;
+        for (int i = 0; i < 10; i++) begin
+            #BAUDRATE_WAIT;
+            random_value = $urandom_range(0, 255);
+            data = random_value;
+            start = 1;
+            #(1.0 / FREQUENCY * 1e9);
+            start = 0;
+            @(negedge busy);
+            assert (random_value == recv_byte)
+            else $display("%h != %h", random_value, recv_byte);
+        end
+        $finish;
+    end
+
+    initial begin
+        #(BAUDRATE_WAIT * 12 * 10);
+        $display("Error: timeout");
+        $error;
+    end
+
+    task automatic read_byte_ser;
+        #(BAUDRATE_WAIT / 2);  // Wait half baud
+        if ((tx == 0)) begin
+
+            #BAUDRATE_WAIT;
+
+            // Read data LSB first
+            for (int j = 0; j < 8; j++) begin
+                recv_byte[j] = tx;
+                #BAUDRATE_WAIT;
+            end
+
+            if ((tx == 1)) begin
+                $display("received: %h", recv_byte);
+            end
+        end
+    endtask
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/util/rtl/T_ff.sv b/verilog/rtl/leorv-fpga/util/rtl/T_ff.sv
new file mode 100644
index 0000000..1517614
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/rtl/T_ff.sv
@@ -0,0 +1,21 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module T_ff (
+    input resetn,
+    input clk,
+    input in,
+
+    output logic out
+);
+    always_ff @(posedge clk) begin
+        if (!resetn) begin
+            out <= 1;
+        end else if (in) begin
+            out <= !out;
+        end
+    end
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/util/rtl/debouncer.sv b/verilog/rtl/leorv-fpga/util/rtl/debouncer.sv
new file mode 100644
index 0000000..93cc42f
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/rtl/debouncer.sv
@@ -0,0 +1,30 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module debouncer #(
+    parameter int MAX_COUNT = 512
+) (
+    input clk,
+    input resetn,
+    input in,
+
+    output logic out
+);
+
+    logic [$clog2(MAX_COUNT+1)-1:0] counter;
+
+    always_ff @(posedge clk) begin
+        if (!resetn || !in) begin
+            counter <= 0;
+        end else begin
+            if (counter < MAX_COUNT) begin
+                counter <= counter + 1;
+            end
+        end
+    end
+
+    assign out = (counter == MAX_COUNT);
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/util/rtl/edge_detection.sv b/verilog/rtl/leorv-fpga/util/rtl/edge_detection.sv
new file mode 100644
index 0000000..5eb07aa
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/rtl/edge_detection.sv
@@ -0,0 +1,38 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module edge_detection #(
+    parameter bit RISING_EDGE  = 1,
+    parameter bit FALLING_EDGE = 0
+) (
+    input clk,
+    input in,
+
+    output logic out
+);
+
+    reg old_in;
+
+    always_ff @(posedge clk) begin
+        old_in <= in;
+    end
+
+    logic rising_edge;
+    logic falling_edge;
+
+    assign rising_edge  = ~old_in && in;
+    assign falling_edge = old_in && ~in;
+
+    generate
+        if (RISING_EDGE && FALLING_EDGE) begin : gen_both_edges
+            assign out = rising_edge || falling_edge;
+        end else if (RISING_EDGE) begin : gen_rising_edge
+            assign out = rising_edge;
+        end else if (FALLING_EDGE) begin : gen_falling_edge
+            assign out = falling_edge;
+        end
+    endgenerate
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv b/verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv
new file mode 100644
index 0000000..40f281a
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv
@@ -0,0 +1,31 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module synchronizer #(
+    parameter int FF_COUNT = 3
+) (
+    input clk,
+    input resetn,
+    input in,
+
+    output logic out
+);
+
+    reg [FF_COUNT-1:0] pipe;
+
+    always_ff @(posedge clk) begin
+        if (!resetn) begin
+            pipe <= 0;
+        end else begin
+
+            pipe[0] <= in;
+            for (int i = 0; i < FF_COUNT - 1; i++) begin : loopName
+                pipe[i+1] <= pipe[i];
+            end
+            out <= pipe[FF_COUNT-1];
+        end
+    end
+
+endmodule
diff --git a/verilog/rtl/leorv-fpga/util/tb/T_ff_tb.sv b/verilog/rtl/leorv-fpga/util/tb/T_ff_tb.sv
new file mode 100644
index 0000000..0d5da98
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/tb/T_ff_tb.sv
@@ -0,0 +1,40 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+module T_ff_tb;
+
+    logic clk;
+    logic in;
+    logic out;
+    logic resetn;
+
+    always #5 clk = !clk;
+
+    T_ff T_ff (
+        .resetn(resetn),
+        .clk   (clk),
+        .in    (in),
+
+        .out(out)
+    );
+
+    initial begin
+        $dumpfile("T_ff_tb.vcd");
+        $dumpvars(0, T_ff_tb);
+    end
+
+    initial begin
+        resetn = 0;
+        clk = 0;
+        in = 0;
+        #50 resetn = 1;
+        #15 in = 1;
+        #20 in = 0;
+        #15 in = 1;
+        #10 in = 0;
+        #20 $finish;
+    end
+
+endmodule
+
+
diff --git a/verilog/rtl/leorv-fpga/util/tb/debouncer_tb.sv b/verilog/rtl/leorv-fpga/util/tb/debouncer_tb.sv
new file mode 100644
index 0000000..4c6d1dd
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/tb/debouncer_tb.sv
@@ -0,0 +1,39 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+module debouncer_tb;
+
+    logic clk;
+    logic resetn;
+    logic in;
+    logic out;
+
+    always #1 clk = !clk;
+
+    debouncer #(10) debouncer (
+        .clk   (clk),
+        .resetn(resetn),
+        .in    (in),
+
+        .out(out)
+    );
+
+    initial begin
+        $dumpfile("debouncer_tb.vcd");
+        $dumpvars(0, debouncer_tb);
+
+    end
+
+    initial begin
+        clk = 0;
+        resetn = 0;
+        in = 0;
+        #10 resetn = 1;
+        #100 in = 1;
+        #1000 in = 0;
+        #100 $finish;
+    end
+
+endmodule
+
+
diff --git a/verilog/rtl/leorv-fpga/util/tb/edge_detection_tb.sv b/verilog/rtl/leorv-fpga/util/tb/edge_detection_tb.sv
new file mode 100644
index 0000000..90c5622
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/tb/edge_detection_tb.sv
@@ -0,0 +1,39 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+module edge_detection_tb;
+
+    logic clk;
+    logic in;
+    logic out;
+
+    always #5 clk = !clk;
+
+    edge_detection #(
+        .RISING_EDGE (0),
+        .FALLING_EDGE(1)
+    ) flank_detection (
+        .clk(clk),
+        .in (in),
+
+        .out(out)
+    );
+
+    initial begin
+        $dumpfile("edge_detection_tb.vcd");
+        $dumpvars(0, edge_detection_tb);
+    end
+
+    initial begin
+        clk = 0;
+        in  = 0;
+        #15 in = 1;
+        #20 in = 0;
+        #15 in = 1;
+        #10 in = 0;
+        #20 $finish;
+    end
+
+endmodule
+
+
diff --git a/verilog/rtl/leorv-fpga/util/tb/synchronizer_tb.sv b/verilog/rtl/leorv-fpga/util/tb/synchronizer_tb.sv
new file mode 100644
index 0000000..abf6463
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/util/tb/synchronizer_tb.sv
@@ -0,0 +1,39 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+module synchronizer_tb;
+
+    logic clk;
+    logic resetn;
+    logic in;
+    logic out;
+
+    always #1 clk = !clk;
+
+    synchronizer synchronizer (
+        .clk   (clk),
+        .resetn(resetn),
+        .in    (in),
+
+        .out(out)
+    );
+
+    initial begin
+        $dumpfile("synchronizer_tb.vcd");
+        $dumpvars(0, synchronizer_tb);
+
+    end
+
+    initial begin
+        clk = 0;
+        resetn = 0;
+        in = 0;
+        #10 resetn = 1;
+        #100 in = 1;
+        #1000 in = 0;
+        #100 $finish;
+    end
+
+endmodule
+
+
diff --git a/verilog/rtl/leorv-fpga/wb_memory/rtl/wb_memory.sv b/verilog/rtl/leorv-fpga/wb_memory/rtl/wb_memory.sv
new file mode 100644
index 0000000..091853e
--- /dev/null
+++ b/verilog/rtl/leorv-fpga/wb_memory/rtl/wb_memory.sv
@@ -0,0 +1,60 @@
+// SPDX-FileCopyrightText: © 2022 Leo Moser <https://codeberg.org/mole99>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+`timescale 1ns / 1ps
+
+module wb_memory #(
+    parameter NUM_WMASKS = 4,
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 11
+) (
+
+    // Wishbone port
+    input         io_wbs_clk,
+    input         io_wbs_rst,
+    input  [31:0] io_wbs_adr,
+    input  [31:0] io_wbs_datwr,
+    output [31:0] io_wbs_datrd,
+    input         io_wbs_we,
+    input  [ 3:0] io_wbs_sel,
+    input         io_wbs_stb,
+    output logic  io_wbs_ack,
+    input         io_wbs_cyc,
+
+    // Memory Port
+    output logic web,
+    output [NUM_WMASKS-1:0] wmask,
+    output [ADDR_WIDTH-1:0] addr,
+    output [DATA_WIDTH-1:0] din,
+    input  [DATA_WIDTH-1:0] dout
+
+);
+
+    // Assign address, ignore two lowest bits
+    assign addr = io_wbs_adr[ADDR_WIDTH+1:2];
+    assign wmask = io_wbs_sel;
+    assign din = io_wbs_datwr;
+    assign io_wbs_datrd = dout;
+
+    always_ff @(posedge io_wbs_clk, posedge io_wbs_rst) begin
+        if (io_wbs_rst) begin
+            web <= 1'b1;
+            io_wbs_ack <= 1'b0;
+        end else begin
+            web <= 1'b1;
+            io_wbs_ack <= 1'b0;
+            
+            // Write operation, ack immediately
+            if (io_wbs_cyc && io_wbs_stb && !io_wbs_ack && io_wbs_we) begin
+                web <= 1'b0;
+                io_wbs_ack <= 1'b1;
+            end
+            
+            // Read operation, ack immediately
+            if (io_wbs_cyc && io_wbs_stb && !io_wbs_ack && !io_wbs_we) begin
+                io_wbs_ack <= 1'b1;
+            end
+        end
+    end
+
+endmodule