openlane/tiny_user_project/config.json

{
    "DESIGN_NAME": "tiny_user_project",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/user_module.v",
        "dir::../../verilog/rtl/cells.v",
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/tiny_user_project.v"
    ],
    "CLOCK_TREE_SYNTH": 1,
    "CLOCK_PORT": "clk",
    "CLOCK_NET": "ref::$CLOCK_PORT",
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 300 300",
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "PL_BASIC_PLACEMENT": 1,
    "PL_TARGET_DENSITY": 0.7,
    "SYNTH_READ_BLACKBOX_LIB": 1,
    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 1,
    "RUN_KLAYOUT_XOR": 0,
    "RUN_KLAYOUT_DRC": 0,
    "pdk::sky130*": {
        "DECAP_CELL": [
            "sky130_fd_sc_hd__decap_3",
            "sky130_fd_sc_hd__decap_4",
            "sky130_fd_sc_hd__decap_6",
            "sky130_fd_sc_hd__decap_8",
            "sky130_ef_sc_hd__decap_12"
        ],
        "CLOCK_PERIOD": 3,
        "RT_MAX_LAYER": "met4",
        "VDD_NETS": [
            "vccd1"
        ],
        "GND_NETS": [
            "vssd1"
        ]
    },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "CLOCK_PERIOD": 3,
        "RT_MAX_LAYER": "Metal4",
        "SYNTH_MAX_FANOUT": 4,
        "VDD_NETS": [
            "vdd"
        ],
        "GND_NETS": [
            "vss"
        ]
    }
}