diff --git a/info.yaml b/info.yaml
index 95a6bfd..639b2c9 100644
--- a/info.yaml
+++ b/info.yaml
@@ -30,8 +30,6 @@
     - clock_selector_bit0
     - clock_selector_bit1
     - clock_A_division_factor_bit0
-    - clock_A_division_factor_bit0
-    - clock_A_division_factor_bit0
     - clock_A_division_factor_bit1
     - clock_A_division_factor_bit2
     - clock_A_division_factor_bit3
@@ -63,7 +61,6 @@
     - clock_D_division_factor_bit5
     - clock_D_division_factor_bit6
     - clock_D_division_factor_bit7
-    - enable
   outputs:
     - clock_selected
 
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index b071f4f..ef37643 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -1,7 +1,7 @@
 
 module user_module(
         input   wire    clk,
-        input   wire    [34:0] io_in,
+        input   wire    [33:0] io_in,
         output  wire    out
     );
     
@@ -16,12 +16,10 @@
     wire [7:0]  clock_div_factor_c;
     wire [7:0]  clock_div_factor_d;
     wire [1:0]  clock_select;
-    wire        enable;
     wire        clock_syn;
     
     assign  clock_select = io_in[1:0];
-    assign  enable = io_in[34];
-    assign  clock_syn = (enable)? div_clock[clock_select]:0;
+    assign  clock_syn = div_clock[clock_select];
     assign  clock_div_factor_a = io_in[9:2];
     assign  clock_div_factor_b = io_in[17:10];
     assign  clock_div_factor_c = io_in[25:18];