diff --git a/VERIFICATION.md b/VERIFICATION.md
index cc7dd5c..2717bb5 100644
--- a/VERIFICATION.md
+++ b/VERIFICATION.md
@@ -38,14 +38,18 @@
 * Edit openlane/scan_controller/config.tcl and change NUM_DESIGNS=250 to NUM_DESIGNS=20.
 * Then from the top level directory:
 
+
     make scan_controller
     make user_project_wrapper
 
+
 * Then run the GL test
 
+
     cd verilog/dv/scan_controller
     make test_scan_controller_gl
 
+
 #### single
 
 Just check one inverter module. Mainly for easy understanding of the traces.
diff --git a/configure.py b/configure.py
index 53da091..601176d 100755
--- a/configure.py
+++ b/configure.py
@@ -618,7 +618,7 @@
             fh.write('-v $(USER_PROJECT_VERILOG)/gl/scanchain.v\n')
             for project in self.projects:
                 if not project.is_fill():
-                    fh.write(f'-v $(USER_PROJECT_VERILOG)/gl/{project.get_gl_verilog_filename()}"\n')
+                    fh.write(f'-v $(USER_PROJECT_VERILOG)/gl/{project.get_gl_verilog_filename()}\n')
 
     def list(self):
         for project in self.projects: