diff --git a/configure.py b/configure.py
index f4b1d73..1715442 100755
--- a/configure.py
+++ b/configure.py
@@ -93,7 +93,7 @@
                     project.copy_files_to_caravel()
 
                 # check all top level module ports are correct
-#                project.check_ports()
+                project.check_ports()
                 project.check_num_cells()
 
             self.projects.append(project)
@@ -137,7 +137,12 @@
         source_list = " ".join(sources)
 
         json_file = 'ports.json'
-        os.system("yosys -qp 'read_verilog -sv %s; hierarchy -top %s ; proc; json -o %s x:*'" % (source_list, top, json_file))
+        yosys_cmd = f"yosys -qp 'read_verilog -lib -sv {source_list}; hierarchy -top {top} ; proc; write_json {json_file}'"
+        p = subprocess.run(yosys_cmd, shell=True)
+        if p.returncode != 0:
+            logging.error(f"yosys port read failed for {self}")
+            exit(1)
+
         with open(json_file) as fh:
             ports = json.load(fh)
         os.unlink(json_file)
@@ -145,10 +150,10 @@
         module_ports = ports['modules'][top]['ports']
         for port in ['io_in', 'io_out']:
             if port not in module_ports:
-                logging.error(f"{port} not found in top")
+                logging.error(f"{self} {port} not found in top")
                 exit(1)
             if len(module_ports[port]['bits']) != 8:
-                logging.error(f"{port} doesn't have 8 bits")
+                logging.error(f"{self} {port} doesn't have 8 bits")
                 exit(1)
 
     def check_num_cells(self):
@@ -273,7 +278,7 @@
             configure_cmd = 'python ./configure.py --create-user-config'
         p = subprocess.run(configure_cmd, shell=True)
         if p.returncode != 0:
-            logging.error("configure failed")
+            logging.error(f"configure failed for {self}")
             exit(1)
 
         # requires PDK_ROOT, OPENLANE_ROOT & OPENLANE_IMAGE_NAME to be set in local environment
@@ -281,7 +286,7 @@
         env = os.environ.copy()
         p = subprocess.run(harden_cmd, shell=True, env=env)
         if p.returncode != 0:
-            logging.error("harden failed")
+            logging.error(f"harden failed for {self}")
             exit(1)
 
         os.chdir(cwd)
diff --git a/datasheet.pdf b/datasheet.pdf
index 8339d52..7331f67 100644
--- a/datasheet.pdf
+++ b/datasheet.pdf
Binary files differ
diff --git a/project_urls.py b/project_urls.py
index e58e901..547e3e6 100644
--- a/project_urls.py
+++ b/project_urls.py
@@ -60,7 +60,7 @@
     "https://github.com/QuantamHD/ethan-evan-random-numbers",
     "https://github.com/QuantamHD/evan-submission",
     "https://github.com/FlyGoat/tt02-play-tune-flygoat",
-    "https://github.com/jleightcap/clash-silicon-tinytapeout",
+#    "https://github.com/jleightcap/clash-silicon-tinytapeout", # missing files
     "https://github.com/89Mods/tt2-lcd-namebadge",
     "https://github.com/Christina-Cyr/tt02-submission-UART-CC",
     "https://github.com/krasin/tt02-verilog-3-bit-8-channel-pwm-driver",
diff --git a/projects.pkl b/projects.pkl
deleted file mode 100644
index 3b72b70..0000000
--- a/projects.pkl
+++ /dev/null
Binary files differ
diff --git a/projects_test.pkl b/projects_test.pkl
deleted file mode 100644
index e04ae5f..0000000
--- a/projects_test.pkl
+++ /dev/null
Binary files differ
diff --git a/ttlogo.png b/ttlogo.png
index e231dd4..91902db 100644
--- a/ttlogo.png
+++ b/ttlogo.png
Binary files differ