# name must be valid verilog module name set in scan_wrapper.v
project_urls = [
            'https://github.com/mattvenn/wokwi-verilog-gds-test',
            'https://github.com/mattvenn/animation_tinytapeout_demo',
            'https://github.com/mattvenn/wokwi_inverters',
            'https://github.com/wokwi/tiny-tapeout-test-simple',
            'https://github.com/omerk/tinytapeout-demo1',
            'https://github.com/mattvenn/tinytapeout-7seg-decoder',
            'https://github.com/omerk/tinytapeout-verilog-test',
            'https://github.com/gregdavill/tinytapeout_spin0',
    ]