We are not trying to verify every single design. That is up to the person who makes it. What we want is to ensure that every design is accessible, even if some designs are broken.
We can split the verification effort into functional testing (simulation), static tests (formal verification), timing tests (STA) and physical tests (LVS & DRC).
See the sections below for details on each type of verification.
You will need the GitHub tokens setup as described in INFO.
The default of 250 projects takes a very long time to simulate, so I advise overriding the configuration:
# fetch the test projects ./configure.py --test --clone-all # rebuild config with only 20 projects ./configure.py --test --update-caravel --limit 20
You will also need iVerilog & cocotb. The easist way to install these are to download and install the oss-cad-suite.
This test only instantiates user_project_wrapper (which contains all the small projects). It doesn't simulate the rest of the ASIC.
cd verilog/dv/scan_controller make test_scan_controller
The Gate Level simulation requires scan_controller and user_project_wrapper to be re-hardened to get the correct gate level netlists:
Edit openlane/scan_controller/config.tcl and change NUM_DESIGNS=250 to NUM_DESIGNS=20.
Then from the top level directory:
make scan_controller make user_project_wrapper
Then run the GL test
cd verilog/dv/scan_controller make test_scan_controller_gl
Just check one inverter module. Mainly for easy understanding of the traces.
make test_single
Just check one inverter module. Set a custom wait state value.
make test_wait_state
Test one inverter module with an automatically generated clock on input 0. Sets the clock rate to 1/2 of the scan refresh rate.
make test_clock_div
For all the top level tests, you will also need a RISCV compiler to build the firmware.
You will also need to install the ‘management core’ for the Caravel ASIC submission wrapper. This is done automatically by following the PDK install instructions.
Uses the scan controller, instantiated inside the whole chip.
cd verilog/dv/scan_controller_int make coco_test
Uses external signals to control the scan chain. Simulates the whole chip.
cd verilog/dv/scan_controller_ext make coco_test
Uses the RISCV co-processor to drive the scanchain with firmware. Simulates the whole chip.
cd verilog/dv/scan_controller_la make coco_test
Each GL netlist for each small project is proven to be equivalent to the reference scan chain implementation. The verification is done on the GL netlist, so an RTL version of the cells used needed to be created. See here for more info.
In case the internal scan controller doesn't work, we also have ability to control the chain from external pins or the Caravel Logic Analyser. We implement a simple MUX to achieve this and formally prove it is correct.
Due to limitations in OpenLane - a top level timing analyis is not possible. This would allow us to detect setup and hold violations in the scan chain.
Instead, we design the chain and the timing constraints for each project and the scan controller with this in mind.
Each project is built with OpenLane, which will check LVS for each small project. Then when we combine all the projects together we run a top level LVS & DRC for routing, power supply and macro placement.
The extracted netlist from the GDS is what is used in the formal scan chain proof.
DRC is checked by OpenLane for each small project, and then again at the top level when we combine all the projects.
Mitch Bailey' CVC checker is a device level static verification system for quickly and easily detecting common circuit errors in CDL (Circuit Definition Language) netlists. We ran the test on the final design and found no errors.