diff --git a/README.md b/README.md
index bcc28af..84ccd72 100644
--- a/README.md
+++ b/README.md
@@ -18,54 +18,54 @@
 
 # Project Index
 
-| Author | Title | Git Repo |
-| ------ | ------| ---------|
-| Matt Venn | Test Straight Project | https://github.com/TinyTapeout/tt02-test-straight |
-| Chris | Scrolling Binary Matrix display | https://github.com/chrisruk/matrixchip |
-| Jon Klein | Power supply sequencer | https://github.com/loxodes/tt02-submission-loxodes |
-| Marcelo Pouso / Miguel Correia | Duty Controler | https://github.com/migcorre/tt02-dc |
-| Jan Gray | S4GA: Super Slow Serial SRAM FPGA | https://github.com/grayresearch/tt02-s4ga |
-| Ryan C | CPU | https://github.com/ryancor/tt02-submission-template |
-| Aidan Good | The McCoy 6-bit Microprocessor | https://github.com/AidanGood/tt02-McCoy |
-| Azdle | binary clock | https://github.com/azdle/binary-clock-asic |
-| Justin Pelan | TinySensor | https://github.com/justinP-wrk/tt02-TinySensor |
-| James Ross | 8x8 SRAM | https://github.com/jar/tt02_sram |
-| Jens Schleusner | German Traffic Light State Machine | https://github.com/JensIMS/tt02-trafficlight |
-| Seppe Van Dyck | 4-spin Ising Chain Simulation | https://github.com/svd321/tt02-Ising |
-| Tholin | Avalon Semiconductors '5401' 4-bit Microprocessor | https://github.com/89Mods/tt2-AvalonSemi-5401 |
-| Rice Shelley | small FFT | https://github.com/RiceShelley/tiny-fft |
-| William Moyes | Stream Integrator | https://github.com/moyesw/tt02-moyesw-StreamIntegrator |
-| Tom Schucker | tiny-fir | https://github.com/Tschucker/tt02-submission-tiny-fir |
-| Greg Steiert | Configurable SR | https://github.com/steieio/tt02-submission-universal-sr |
-| Luis Ardila | LUTRAM | https://github.com/leardilap/tt02-LUTRAM |
-| Emil J Tywoniak | chase the beat | https://github.com/ekliptik/tt02-chase-the-beat |
-| maehw | BCD to 7-segment encoder | https://github.com/maehw/tt02-bcd-7segment-encoder |
-| Ben Everard | A LED Flasher | https://github.com/benevpi/tt02-LED-flasher |
-| Fernando Dominguez Pousa | 4-bit Multiplier | https://github.com/kuriousd/tt02-4bit-multiplier |
-| Tholin | Avalon Semiconductors 'TBB1143' Programmable Sound Generator | https://github.com/89Mods/tt2-avalonsemi-TBB1143 |
-| Tom Keddie | Transmit UART | https://github.com/TomKeddie/tinytapeout-2022-2a |
-| Matt M | RGB LED Matrix Driver | https://github.com/mm21/tinytapeout2-led-matrix |
-| argunda | Tiny Phase/Frequency Detector | https://github.com/argunda/tt02-TinyPFD |
-| Andre & Milosch Meriac | Loading Animation | https://github.com/meriac/loading-animation |
-| yubex | tiny egg timer | https://github.com/yubex/tt02-tiny_egg_timer |
-| Pepper Gray (they/them) | Potato-1 (Brainfuck CPU) | https://github.com/peppergrayxyz/Potato-1 |
-| zoe nguyen.  taylor | heart zoe mom dad | https://github.com/zoent/tt02-zoe-chip |
-| Nanik Adnani | Tiny Synth | https://github.com/nanikgeorge/tt02-submission-template |
-| Michael Bikovitsky | 5-bit Galois LFSR | https://github.com/mbikovitsky/tt02-lfsr |
-| Tom Schucker | prbs15 | https://github.com/teaandtechtime/tt02-submission-prbs15 |
-| Rolf Widenfelt | 4-bit badge ALU | https://github.com/rolfmobile99/tt02-submission-template |
-| James Ross | Illegal Logic | https://github.com/jar/tt02_freespeech |
-| Alan Green | Siren | https://github.com/alanvgreen/tt02-siren |
-| Frans Skarman | YaFPGA | https://github.com/TheZoq2/smolfpga |
-| William Moyes | M0 | https://github.com/moyesw/TT02-M0 |
-| Jake "ferris" Taylor | bitslam | https://github.com/yupferris/bitslam |
-| Thorsten Knoll | 8x8 Bit Pattern Player | https://github.com/ThorKn/tinytapeout02_pattern_player |
-| proppy | XLS: bit population count | https://github.com/proppy/tt02-xls-popcount |
-| Jean THOMAS | RC5 decoder | https://github.com/jeanthom/tt02-rc5-receiver |
-| Maria CHiara Molteni | chiDOM | https://github.com/mmolteni-secpat/tinytapeout02_chiDOM |
-| Milosch Meriac | Super Mario Tune on A Piezo Speaker | https://github.com/meriac/tt02-play-tune |
-| Phase Noise | Tiny rot13 | https://github.com/phasenoisepon/tt02-phasenoisepon |
-| 13arn | 4 bit counter on steamdeck | https://github.com/13arn/tt02_counter_steamdeck |
-| Thorsten Knoll | Shiftregister Challenge 40 Bit | https://github.com/ThorKn/tinytapeout02_shiftregister_challenge |
-| Tholin | TinyTapeout2 4-bit multiplier. | https://github.com/89Mods/tt2-4x4-multiply |
-| Tholin | TinyTapeout2 multiplexed segment display timer. | https://github.com/89Mods/tt2-multiplexed-counter |
+| Author | Title | Type | Git Repo |
+| ------ | ------| -----| ---------|
+| Matt Venn | Test Straight Project | [Wokwi](https://wokwi.com/projects/339501025136214612) | https://github.com/TinyTapeout/tt02-test-straight |
+| Chris | Scrolling Binary Matrix display | HDL | https://github.com/chrisruk/matrixchip |
+| Jon Klein | Power supply sequencer | HDL | https://github.com/loxodes/tt02-submission-loxodes |
+| Marcelo Pouso / Miguel Correia | Duty Controler | HDL | https://github.com/migcorre/tt02-dc |
+| Jan Gray | S4GA: Super Slow Serial SRAM FPGA | HDL | https://github.com/grayresearch/tt02-s4ga |
+| Ryan C | CPU | HDL | https://github.com/ryancor/tt02-submission-template |
+| Aidan Good | The McCoy 6-bit Microprocessor | HDL | https://github.com/AidanGood/tt02-McCoy |
+| Azdle | binary clock | HDL | https://github.com/azdle/binary-clock-asic |
+| Justin Pelan | TinySensor | [Wokwi](https://wokwi.com/projects/347787021138264660) | https://github.com/justinP-wrk/tt02-TinySensor |
+| James Ross | 8x8 SRAM | HDL | https://github.com/jar/tt02_sram |
+| Jens Schleusner | German Traffic Light State Machine | [Wokwi](https://wokwi.com/projects/347690870424732244) | https://github.com/JensIMS/tt02-trafficlight |
+| Seppe Van Dyck | 4-spin Ising Chain Simulation | [Wokwi](https://wokwi.com/projects/347592305412145748) | https://github.com/svd321/tt02-Ising |
+| Tholin | Avalon Semiconductors '5401' 4-bit Microprocessor | HDL | https://github.com/89Mods/tt2-AvalonSemi-5401 |
+| Rice Shelley | small FFT | HDL | https://github.com/RiceShelley/tiny-fft |
+| William Moyes | Stream Integrator | [Wokwi](https://wokwi.com/projects/346553315158393428) | https://github.com/moyesw/tt02-moyesw-StreamIntegrator |
+| Tom Schucker | tiny-fir | [Wokwi](https://wokwi.com/projects/347894637149553236) | https://github.com/Tschucker/tt02-submission-tiny-fir |
+| Greg Steiert | Configurable SR | [Wokwi](https://wokwi.com/projects/346916357828248146) | https://github.com/steieio/tt02-submission-universal-sr |
+| Luis Ardila | LUTRAM | [Wokwi](https://wokwi.com/projects/347594509754827347) | https://github.com/leardilap/tt02-LUTRAM |
+| Emil J Tywoniak | chase the beat | HDL | https://github.com/ekliptik/tt02-chase-the-beat |
+| maehw | BCD to 7-segment encoder | [Wokwi](https://wokwi.com/projects/347688030570545747) | https://github.com/maehw/tt02-bcd-7segment-encoder |
+| Ben Everard | A LED Flasher | [Wokwi](https://wokwi.com/projects/342981109408072274) | https://github.com/benevpi/tt02-LED-flasher |
+| Fernando Dominguez Pousa | 4-bit Multiplier | HDL | https://github.com/kuriousd/tt02-4bit-multiplier |
+| Tholin | Avalon Semiconductors 'TBB1143' Programmable Sound Generator | HDL | https://github.com/89Mods/tt2-avalonsemi-TBB1143 |
+| Tom Keddie | Transmit UART | HDL | https://github.com/TomKeddie/tinytapeout-2022-2a |
+| Matt M | RGB LED Matrix Driver | HDL | https://github.com/mm21/tinytapeout2-led-matrix |
+| argunda | Tiny Phase/Frequency Detector | [Wokwi](https://wokwi.com/projects/348195845106041428) | https://github.com/argunda/tt02-TinyPFD |
+| Andre & Milosch Meriac | Loading Animation | [Wokwi](https://wokwi.com/projects/348121131386929746) | https://github.com/meriac/loading-animation |
+| yubex | tiny egg timer | HDL | https://github.com/yubex/tt02-tiny_egg_timer |
+| Pepper Gray (they/them) | Potato-1 (Brainfuck CPU) | HDL | https://github.com/peppergrayxyz/Potato-1 |
+| zoe nguyen.  taylor | heart zoe mom dad | HDL | https://github.com/zoent/tt02-zoe-chip |
+| Nanik Adnani | Tiny Synth | [Wokwi](https://wokwi.com/projects/348255968419643987) | https://github.com/nanikgeorge/tt02-submission-template |
+| Michael Bikovitsky | 5-bit Galois LFSR | HDL | https://github.com/mbikovitsky/tt02-lfsr |
+| Tom Schucker | prbs15 | [Wokwi](https://wokwi.com/projects/348260124451668562) | https://github.com/teaandtechtime/tt02-submission-prbs15 |
+| Rolf Widenfelt | 4-bit badge ALU | HDL | https://github.com/rolfmobile99/tt02-submission-template |
+| James Ross | Illegal Logic | HDL | https://github.com/jar/tt02_freespeech |
+| Alan Green | Siren | [Wokwi](https://wokwi.com/projects/348242239268323922) | https://github.com/alanvgreen/tt02-siren |
+| Frans Skarman | YaFPGA | HDL | https://github.com/TheZoq2/smolfpga |
+| William Moyes | M0 | HDL | https://github.com/moyesw/TT02-M0 |
+| Jake "ferris" Taylor | bitslam | HDL | https://github.com/yupferris/bitslam |
+| Thorsten Knoll | 8x8 Bit Pattern Player | [Wokwi](https://wokwi.com/projects/341620484740219475) | https://github.com/ThorKn/tinytapeout02_pattern_player |
+| proppy | XLS: bit population count | HDL | https://github.com/proppy/tt02-xls-popcount |
+| Jean THOMAS | RC5 decoder | HDL | https://github.com/jeanthom/tt02-rc5-receiver |
+| Maria CHiara Molteni | chiDOM | [Wokwi](https://wokwi.com/projects/341614374571475540) | https://github.com/mmolteni-secpat/tinytapeout02_chiDOM |
+| Milosch Meriac | Super Mario Tune on A Piezo Speaker | HDL | https://github.com/meriac/tt02-play-tune |
+| Phase Noise | Tiny rot13 | HDL | https://github.com/phasenoisepon/tt02-phasenoisepon |
+| 13arn | 4 bit counter on steamdeck | [Wokwi](https://wokwi.com/projects/341541108650607187) | https://github.com/13arn/tt02_counter_steamdeck |
+| Thorsten Knoll | Shiftregister Challenge 40 Bit | [Wokwi](https://wokwi.com/projects/341516949939814994) | https://github.com/ThorKn/tinytapeout02_shiftregister_challenge |
+| Tholin | TinyTapeout2 4-bit multiplier. | HDL | https://github.com/89Mods/tt2-4x4-multiply |
+| Tholin | TinyTapeout2 multiplexed segment display timer. | HDL | https://github.com/89Mods/tt2-multiplexed-counter |
diff --git a/configure.py b/configure.py
index f124456..8835961 100755
--- a/configure.py
+++ b/configure.py
@@ -76,6 +76,7 @@
 
                 # check all top level module ports are correct
                 project.check_ports()
+                project.check_num_cells()
 
             self.projects.append(project)
         
@@ -116,17 +117,37 @@
         sources = [ os.path.join(self.local_dir, 'src', src) for src in self.src_files ]
         source_list = " ".join(sources)
         
-        json_file = '/tmp/ports.json'
+        json_file = 'ports.json'
         os.system("yosys -qp 'read_verilog -sv %s; hierarchy -top %s ; proc; json -o %s x:*'" % (source_list, top, json_file))
         with open(json_file) as fh:                                                                                                                                                                                         
             ports = json.load(fh)                                                                                                                                                                                           
+        os.unlink(json_file)
+
         module_ports = ports['modules'][top]['ports']
         for port in ['io_in', 'io_out']:
-            assert port in module_ports
-            assert len(module_ports[port]['bits']) == 8
+            if port not in module_ports:
+                logging.error(f"{port} not found in top")
+                exit(1)
+            if len(module_ports[port]['bits']) != 8:
+                logging.error(f"{port} doesn't have 8 bits")
+                exit(1)
+
 
     def check_num_cells(self):
-        pass
+        num_cells = 0
+        yosys_report = glob.glob(f'{self.local_dir}/runs/wokwi/reports/synthesis/1-synthesis.*0.stat.rpt')[0] # can't open a file with \ in the path
+        with open(yosys_report) as fh:
+            for line in fh.readlines():
+                m = re.search(r'Number of cells:\s+(\d+)', line)
+                if m is not None:
+                    num_cells = int(m.group(1))
+        if not self.fill and self.index != 0:
+            if self.is_hdl():
+                if num_cells < 20:
+                    logging.error(f"{self} only has {num_cells} cells")
+            else:
+                if num_cells < 11:
+                    logging.error(f"{self} only has {num_cells} cells")
 
     def is_wokwi(self):
         if self.wokwi_id != 0:
@@ -158,7 +179,12 @@
         self.scanchain_instance     = f"scanchain_{self.index}"
   
     def get_index_row(self):
-        return f'| {self.yaml["documentation"]["author"]} | {self.yaml["documentation"]["title"]} | {self.git_url} |\n'
+        if self.is_wokwi():
+            type_string = f"[Wokwi](https://wokwi.com/projects/{self.wokwi_id})"
+        else:
+            type_string = f"HDL"
+
+        return f'| {self.yaml["documentation"]["author"]} | {self.yaml["documentation"]["title"]} | {type_string} | {self.git_url} |\n'
 
     # top module name is defined in one of the source files, which one?
     def find_top_verilog(self):
@@ -539,8 +565,8 @@
             readme = fh.read()
         with open("README.md", 'w') as fh:
             fh.write(readme)
-            fh.write("| Author | Title | Git Repo |\n")
-            fh.write("| ------ | ------| ---------|\n")
+            fh.write("| Author | Title | Type | Git Repo |\n")
+            fh.write("| ------ | ------| -----| ---------|\n")
             for project in self.projects:
                 if not project.fill:
                     fh.write(project.get_index_row())