v {xschem version=3.0.0 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
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L 4 130 -770 130 -650 {}
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L 7 130 -740 150 -740 {}
L 7 130 -720 150 -720 {}
L 7 130 -700 150 -700 {}
B 5 -152.5 -762.5 -147.5 -757.5 {name=row_sel dir=in }
B 5 -152.5 -742.5 -147.5 -737.5 {name=col_sel dir=in }
B 5 -152.5 -722.5 -147.5 -717.5 {name=Vgnr dir=in }
B 5 -152.5 -702.5 -147.5 -697.5 {name=WR dir=in }
B 5 -152.5 -682.5 -147.5 -677.5 {name=Vgpr dir=in }
B 5 147.5 -462.5 152.5 -457.5 {name=B15r sig_type=std_logic dir=in }
B 5 -152.5 -462.5 -147.5 -457.5 {name=A15r sig_type=std_logic dir=in }
B 5 147.5 -442.5 152.5 -437.5 {name=B14r sig_type=std_logic dir=in }
B 5 -152.5 -442.5 -147.5 -437.5 {name=A14r sig_type=std_logic dir=in }
B 5 -152.5 -662.5 -147.5 -657.5 {name=SAMPLE dir=in }
B 5 147.5 -422.5 152.5 -417.5 {name=B13r sig_type=std_logic dir=in }
B 5 -152.5 -422.5 -147.5 -417.5 {name=A13r sig_type=std_logic dir=in }
B 5 147.5 -402.5 152.5 -397.5 {name=B12r sig_type=std_logic dir=in }
B 5 -152.5 -402.5 -147.5 -397.5 {name=A12r sig_type=std_logic dir=in }
B 5 147.5 -382.5 152.5 -377.5 {name=B11r sig_type=std_logic dir=in }
B 5 -152.5 -382.5 -147.5 -377.5 {name=A11r sig_type=std_logic dir=in }
B 5 147.5 -362.5 152.5 -357.5 {name=B10r sig_type=std_logic dir=in }
B 5 -152.5 -362.5 -147.5 -357.5 {name=A10r sig_type=std_logic dir=in }
B 5 -152.5 -642.5 -147.5 -637.5 {name=Vrminus dir=in }
B 5 147.5 -342.5 152.5 -337.5 {name=B9r sig_type=std_logic dir=in }
B 5 -152.5 -342.5 -147.5 -337.5 {name=A9r sig_type=std_logic dir=in }
B 5 -152.5 -622.5 -147.5 -617.5 {name=Vrplus dir=in }
B 5 147.5 -322.5 152.5 -317.5 {name=B8r sig_type=std_logic dir=in }
B 5 -152.5 -322.5 -147.5 -317.5 {name=A8r sig_type=std_logic dir=in }
B 5 147.5 -302.5 152.5 -297.5 {name=B7r sig_type=std_logic dir=in }
B 5 -152.5 -302.5 -147.5 -297.5 {name=A7r sig_type=std_logic dir=in }
B 5 147.5 -282.5 152.5 -277.5 {name=B6r sig_type=std_logic dir=in }
B 5 -152.5 -282.5 -147.5 -277.5 {name=A6r sig_type=std_logic dir=in }
B 5 147.5 -262.5 152.5 -257.5 {name=B5r sig_type=std_logic dir=in }
B 5 -152.5 -262.5 -147.5 -257.5 {name=A5r sig_type=std_logic dir=in }
B 5 147.5 -242.5 152.5 -237.5 {name=B4r sig_type=std_logic dir=in }
B 5 -152.5 -242.5 -147.5 -237.5 {name=A4r sig_type=std_logic dir=in }
B 5 147.5 -222.5 152.5 -217.5 {name=B3r sig_type=std_logic dir=in }
B 5 -152.5 -222.5 -147.5 -217.5 {name=A3r sig_type=std_logic dir=in }
B 5 147.5 -202.5 152.5 -197.5 {name=B2r sig_type=std_logic dir=in }
B 5 -152.5 -202.5 -147.5 -197.5 {name=A2r sig_type=std_logic dir=in }
B 5 147.5 -182.5 152.5 -177.5 {name=B1r sig_type=std_logic dir=in }
B 5 -152.5 -182.5 -147.5 -177.5 {name=A1r sig_type=std_logic dir=in }
B 5 147.5 -162.5 152.5 -157.5 {name=B0r sig_type=std_logic dir=in }
B 5 -152.5 -162.5 -147.5 -157.5 {name=A0r sig_type=std_logic dir=in }
B 5 -152.5 -122.5 -147.5 -117.5 {name=WL15 sig_type=std_logic dir=in }
B 5 -152.5 -102.5 -147.5 -97.5 {name=WL14 sig_type=std_logic dir=in }
B 5 -152.5 -82.5 -147.5 -77.5 {name=WL13 sig_type=std_logic dir=in }
B 5 -152.5 -62.5 -147.5 -57.5 {name=WL12 sig_type=std_logic dir=in }
B 5 -152.5 -42.5 -147.5 -37.5 {name=WL11 sig_type=std_logic dir=in }
B 5 -152.5 -22.5 -147.5 -17.5 {name=WL10 sig_type=std_logic dir=in }
B 5 -152.5 -2.5 -147.5 2.5 {name=WL9 sig_type=std_logic dir=in }
B 5 -152.5 17.5 -147.5 22.5 {name=WL8 sig_type=std_logic dir=in }
B 5 -152.5 37.5 -147.5 42.5 {name=WL7 sig_type=std_logic dir=in }
B 5 -152.5 57.5 -147.5 62.5 {name=WL6 sig_type=std_logic dir=in }
B 5 -152.5 77.5 -147.5 82.5 {name=WL5 sig_type=std_logic dir=in }
B 5 -152.5 97.5 -147.5 102.5 {name=WL4 sig_type=std_logic dir=in }
B 5 -152.5 117.5 -147.5 122.5 {name=WL3 sig_type=std_logic dir=in }
B 5 -152.5 137.5 -147.5 142.5 {name=WL2 sig_type=std_logic dir=in }
B 5 -152.5 157.5 -147.5 162.5 {name=WL1 sig_type=std_logic dir=in }
B 5 -152.5 177.5 -147.5 182.5 {name=WL0 sig_type=std_logic dir=in }
B 5 -152.5 -602.5 -147.5 -597.5 {name=RISC_CLK dir=in }
B 5 147.5 -762.5 152.5 -757.5 {name=latch_high dir=out }
B 5 -152.5 -582.5 -147.5 -577.5 {name=Vref_comp dir=in }
B 5 -152.5 -562.5 -147.5 -557.5 {name=Vref dir=in }
B 5 147.5 -742.5 152.5 -737.5 {name=vccd1 dir=inout }
B 5 147.5 -722.5 152.5 -717.5 {name=vdda1 dir=inout }
B 5 147.5 -702.5 152.5 -697.5 {name=vssd1 dir=inout }
B 5 -152.5 -542.5 -147.5 -537.5 {name=Vcminus dir=in }
B 5 -152.5 -522.5 -147.5 -517.5 {name=Vcplus dir=in }
B 5 147.5 437.5 152.5 442.5 {name=B4c sig_type=std_logic dir=in }
B 5 147.5 457.5 152.5 462.5 {name=B3c sig_type=std_logic dir=in }
B 5 147.5 477.5 152.5 482.5 {name=B2c sig_type=std_logic dir=in }
B 5 147.5 497.5 152.5 502.5 {name=B1c sig_type=std_logic dir=in }
B 5 147.5 517.5 152.5 522.5 {name=B0c sig_type=std_logic dir=in }
B 5 -152.5 217.5 -147.5 222.5 {name=A15c sig_type=std_logic dir=in }
B 5 -152.5 237.5 -147.5 242.5 {name=A14c sig_type=std_logic dir=in }
B 5 -152.5 257.5 -147.5 262.5 {name=A13c sig_type=std_logic dir=in }
B 5 -152.5 277.5 -147.5 282.5 {name=A12c sig_type=std_logic dir=in }
B 5 -152.5 297.5 -147.5 302.5 {name=A11c sig_type=std_logic dir=in }
B 5 -152.5 317.5 -147.5 322.5 {name=A10c sig_type=std_logic dir=in }
B 5 -152.5 337.5 -147.5 342.5 {name=A9c sig_type=std_logic dir=in }
B 5 -152.5 357.5 -147.5 362.5 {name=A8c sig_type=std_logic dir=in }
B 5 -152.5 377.5 -147.5 382.5 {name=A7c sig_type=std_logic dir=in }
B 5 -152.5 397.5 -147.5 402.5 {name=A6c sig_type=std_logic dir=in }
B 5 -152.5 417.5 -147.5 422.5 {name=A5c sig_type=std_logic dir=in }
B 5 -152.5 437.5 -147.5 442.5 {name=A4c sig_type=std_logic dir=in }
B 5 -152.5 457.5 -147.5 462.5 {name=A3c sig_type=std_logic dir=in }
B 5 -152.5 477.5 -147.5 482.5 {name=A2c sig_type=std_logic dir=in }
B 5 147.5 337.5 152.5 342.5 {name=B9c sig_type=std_logic dir=in }
B 5 147.5 217.5 152.5 222.5 {name=B15c sig_type=std_logic dir=in }
B 5 147.5 237.5 152.5 242.5 {name=B14c sig_type=std_logic dir=in }
B 5 147.5 257.5 152.5 262.5 {name=B13c sig_type=std_logic dir=in }
B 5 147.5 277.5 152.5 282.5 {name=B12c sig_type=std_logic dir=in }
B 5 147.5 297.5 152.5 302.5 {name=B11c sig_type=std_logic dir=in }
B 5 147.5 317.5 152.5 322.5 {name=B10c sig_type=std_logic dir=in }
B 5 147.5 357.5 152.5 362.5 {name=B8c sig_type=std_logic dir=in }
B 5 147.5 377.5 152.5 382.5 {name=B7c sig_type=std_logic dir=in }
B 5 147.5 397.5 152.5 402.5 {name=B6c sig_type=std_logic dir=in }
B 5 147.5 417.5 152.5 422.5 {name=B5c sig_type=std_logic dir=in }
B 5 -152.5 497.5 -147.5 502.5 {name=A1c sig_type=std_logic dir=in }
B 5 -152.5 517.5 -147.5 522.5 {name=A0c sig_type=std_logic dir=in }
T {@symname} -36 -6 0 0 0.3 0.3 {}
T {@name} 85 -792 0 0 0.2 0.2 {}
T {row_sel} -125 -764 0 0 0.2 0.2 {}
T {col_sel} -125 -744 0 0 0.2 0.2 {}
T {Vgnr} -125 -724 0 0 0.2 0.2 {}
T {WR} -125 -704 0 0 0.2 0.2 {}
T {Vgpr} -125 -684 0 0 0.2 0.2 {}
T {B15r} 125 -464 0 1 0.2 0.2 {}
T {A15r} -125 -464 0 0 0.2 0.2 {}
T {B14r} 125 -444 0 1 0.2 0.2 {}
T {A14r} -125 -444 0 0 0.2 0.2 {}
T {SAMPLE} -125 -664 0 0 0.2 0.2 {}
T {B13r} 125 -424 0 1 0.2 0.2 {}
T {A13r} -125 -424 0 0 0.2 0.2 {}
T {B12r} 125 -404 0 1 0.2 0.2 {}
T {A12r} -125 -404 0 0 0.2 0.2 {}
T {B11r} 125 -384 0 1 0.2 0.2 {}
T {A11r} -125 -384 0 0 0.2 0.2 {}
T {B10r} 125 -364 0 1 0.2 0.2 {}
T {A10r} -125 -364 0 0 0.2 0.2 {}
T {Vrminus} -125 -644 0 0 0.2 0.2 {}
T {B9r} 125 -344 0 1 0.2 0.2 {}
T {A9r} -125 -344 0 0 0.2 0.2 {}
T {Vrplus} -125 -624 0 0 0.2 0.2 {}
T {B8r} 125 -324 0 1 0.2 0.2 {}
T {A8r} -125 -324 0 0 0.2 0.2 {}
T {B7r} 125 -304 0 1 0.2 0.2 {}
T {A7r} -125 -304 0 0 0.2 0.2 {}
T {B6r} 125 -284 0 1 0.2 0.2 {}
T {A6r} -125 -284 0 0 0.2 0.2 {}
T {B5r} 125 -264 0 1 0.2 0.2 {}
T {A5r} -125 -264 0 0 0.2 0.2 {}
T {B4r} 125 -244 0 1 0.2 0.2 {}
T {A4r} -125 -244 0 0 0.2 0.2 {}
T {B3r} 125 -224 0 1 0.2 0.2 {}
T {A3r} -125 -224 0 0 0.2 0.2 {}
T {B2r} 125 -204 0 1 0.2 0.2 {}
T {A2r} -125 -204 0 0 0.2 0.2 {}
T {B1r} 125 -184 0 1 0.2 0.2 {}
T {A1r} -125 -184 0 0 0.2 0.2 {}
T {B0r} 125 -164 0 1 0.2 0.2 {}
T {A0r} -125 -164 0 0 0.2 0.2 {}
T {WL15} -125 -124 0 0 0.2 0.2 {}
T {WL14} -125 -104 0 0 0.2 0.2 {}
T {WL13} -125 -84 0 0 0.2 0.2 {}
T {WL12} -125 -64 0 0 0.2 0.2 {}
T {WL11} -125 -44 0 0 0.2 0.2 {}
T {WL10} -125 -24 0 0 0.2 0.2 {}
T {WL9} -125 -4 0 0 0.2 0.2 {}
T {WL8} -125 16 0 0 0.2 0.2 {}
T {WL7} -125 36 0 0 0.2 0.2 {}
T {WL6} -125 56 0 0 0.2 0.2 {}
T {WL5} -125 76 0 0 0.2 0.2 {}
T {WL4} -125 96 0 0 0.2 0.2 {}
T {WL3} -125 116 0 0 0.2 0.2 {}
T {WL2} -125 136 0 0 0.2 0.2 {}
T {WL1} -125 156 0 0 0.2 0.2 {}
T {WL0} -125 176 0 0 0.2 0.2 {}
T {RISC_CLK} -125 -604 0 0 0.2 0.2 {}
T {latch_high} 125 -764 0 1 0.2 0.2 {}
T {Vref_comp} -125 -584 0 0 0.2 0.2 {}
T {Vref} -125 -564 0 0 0.2 0.2 {}
T {vccd1} 125 -744 0 1 0.2 0.2 {}
T {vdda1} 125 -724 0 1 0.2 0.2 {}
T {vssd1} 125 -704 0 1 0.2 0.2 {}
T {Vcminus} -125 -544 0 0 0.2 0.2 {}
T {Vcplus} -125 -524 0 0 0.2 0.2 {}
T {B4c} 125 436 0 1 0.2 0.2 {}
T {B3c} 125 456 0 1 0.2 0.2 {}
T {B2c} 125 476 0 1 0.2 0.2 {}
T {B1c} 125 496 0 1 0.2 0.2 {}
T {B0c} 125 516 0 1 0.2 0.2 {}
T {A15c} -125 216 0 0 0.2 0.2 {}
T {A14c} -125 236 0 0 0.2 0.2 {}
T {A13c} -125 256 0 0 0.2 0.2 {}
T {A12c} -125 276 0 0 0.2 0.2 {}
T {A11c} -125 296 0 0 0.2 0.2 {}
T {A10c} -125 316 0 0 0.2 0.2 {}
T {A9c} -125 336 0 0 0.2 0.2 {}
T {A8c} -125 356 0 0 0.2 0.2 {}
T {A7c} -125 376 0 0 0.2 0.2 {}
T {A6c} -125 396 0 0 0.2 0.2 {}
T {A5c} -125 416 0 0 0.2 0.2 {}
T {A4c} -125 436 0 0 0.2 0.2 {}
T {A3c} -125 456 0 0 0.2 0.2 {}
T {A2c} -125 476 0 0 0.2 0.2 {}
T {B9c} 125 336 0 1 0.2 0.2 {}
T {B15c} 125 216 0 1 0.2 0.2 {}
T {B14c} 125 236 0 1 0.2 0.2 {}
T {B13c} 125 256 0 1 0.2 0.2 {}
T {B12c} 125 276 0 1 0.2 0.2 {}
T {B11c} 125 296 0 1 0.2 0.2 {}
T {B10c} 125 316 0 1 0.2 0.2 {}
T {B8c} 125 356 0 1 0.2 0.2 {}
T {B7c} 125 376 0 1 0.2 0.2 {}
T {B6c} 125 396 0 1 0.2 0.2 {}
T {B5c} 125 416 0 1 0.2 0.2 {}
T {A1c} -125 496 0 0 0.2 0.2 {}
T {A0c} -125 516 0 0 0.2 0.2 {}