diff --git a/.gitignore b/.gitignore
index f770f0d..d1f0d9e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,7 @@
 /.idea/
 /precheck_results/
 */tmp
-*/*/tmp
\ No newline at end of file
+*/*/tmp
+
+*.pyc
+/.doit.db*
diff --git a/LICENSE b/LICENSE
index 261eeb9..4362b49 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,201 +1,502 @@
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+  13. The Free Software Foundation may publish revised and/or new
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+                     END OF TERMS AND CONDITIONS
+
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+  If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
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+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
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+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the
+  library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+  <signature of Ty Coon>, 1 April 1990
+  Ty Coon, President of Vice
+
+That's all there is to it!
diff --git a/README.md b/README.md
index d7d53a3..e68ae3d 100644
--- a/README.md
+++ b/README.md
@@ -1,18 +1,85 @@
-# Caravel Analog User
+# PDKMaster based memory compiler test chip
 
-[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![CI](https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml) [![Caravan Build](https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml/badge.svg)](https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml)
+## Description
 
----
+This test chip contains a first version of an SRAM block with the in development single
+port SRAM compiler. At the time the compiler can only generate a block with 512 words and
+a column demultiplexer of 4 and there has to be exactly one we bit per 8 bits in each word.
+For this tape-out a 512x8 block with one we pin has been used.
 
-| :exclamation: Important Note            |
-|-----------------------------------------|
+Current version of the SRAM cell is DRC compliant and not minimal area yet.
 
-## Please fill in your project documentation in this README.md file 
+The top design consists of connecting in and out each of the SRAM signals using the caravan
+analog frame. It has the following pin mapping:
 
+| caravan pin   | signal    |
+|---------------|-----------|
+| io_analog[4]  | SRAM vdd  |
+| io_analog[5]  | SRAM vss  |
+| vssd1         | logic vss |
+| vccd1         | logic vdd |
+| io_in[0]      | SRAM we   |
+| io_out[1]     | SRAM q[1] |
+| io_out[2]     | SRAM q[2] |
+| io_in[3]      | SRAM d[2] |
+| io_in[4]      | SRAM d[3] |
+| io_out[5]     | SRAM q[3] |
+| io_out[6]     | SRAM q[4] |
+| io_in[7]      | SRAM d[4] |
+| io_in[8]      | SRAM d[5] |
+| io_out[9]     | SRAM q[5] |
+| io_out[10]    | SRAM q[6] |
+| io_in[11]     | SRAM d[6] |
+| io_in[12]     | SRAM d[7] |
+| io_out[13]    | SRAM q[7] |
+| io_in[14]     | SRAM a[0] |
+| io_in[15]     | SRAM a[1] |
+| io_in[16]     | SRAM a[2] |
+| io_in[17]     | SRAM a[3] |
+| io_in[18]     | SRAM a[4] |
+| io_in[19]     | SRAM a[5] |
+| io_in[20]     | SRAM a[6] |
+| io_in[21]     | SRAM a[7] |
+| io_in[22]     | SRAM a[8] |
+| io_in[23]     | SRAM clk  |
+| io_out[24]    | SRAM q[0] |
+| io_in[25]     | SRAM d[0] |
+| io_in[26]     | SRAM d[1] |
 
-:warning: | Use this sample project for analog user projects. 
-:---: | :---
+When `io_in[n]` is present in the table corresponding `io_out[n]` is connected to logic
+zero and corresponding io_oeb[n] to logic one. When `io_out[n]` is present corresponding
+`io_oeb[n]` is connected to logic zero.
 
----
+One can also see that the SRAM block vss/vdd are connected to other pins than for the
+logic vss/vdd. The logic consists of buffers and logic one and zero cells. As the SRAM is
+not put in a deep nwell the SRAM vss and the logic vss will be connected to each other
+through the (higher resistive) bulk of the die. Separate vdd pins though will allow to
+measure the SRAM power consumption independently.
 
-Refer to [README](docs/source/index.rst) for this sample project documentation. 
+## Layout
+
+Layout of the unconnected SRAM block:
+
+![block](block.png)
+
+Layout of the caravan top:
+
+![top](top.png)
+
+## Source
+
+The top level is fully generated from python code in the `doitcode` subdirectory. pydoit is used to generate the design with the provided `dodo.py` file in the top directory. The code depends on some external modules that are assumed to be installed:
+
+* [PDKMaster](https://gitlab.com/Chips4Makers/PDKMaster): python framework (under heavy development) to ease generation of circuits and corresponding DRC compliant layout. This based on a description of a technology with python souce code to allow easy porting to different technologies.
+* [c4m-flexcell](https://gitlab.com/Chips4Makers/c4m-flexcell): a (currently minimal) standard cell library based on PDKMaster
+* [c4m-flexmem](https://gitlab.com/Chips4Makers/c4m-flexmem): the source for the memory compiler
+* [c4m-pdk-sky130](https://gitlab.com/Chips4Makers/c4m-pdk-sky130): the source for the PDKMaster based PDK for the Sky130 technology.  
+  The workbook of the design of the DRC compliant 6T SRAM cell is available [in the repo](
+      https://gitlab.com/Chips4Makers/c4m-pdk-sky130/-/blob/a73f6fae/notebooks/SRAMCellSP6T.ipynb
+  )
+
+As these code bases have still unstable APIs a mpw5 branch has been made in each of the repos with the state as for the tape-out.
+
+## License
+
+The resulting GDS files is released under [the LGPL 2.1 or later](https://spdx.org/licenses/LGPL-2.1-or-later.html) license. Some of the source code to generate the GDS is under [the GPL 2.0 or later](https://spdx.org/licenses/GPL-2.0-or-later.html) license.
diff --git a/block.png b/block.png
new file mode 100644
index 0000000..58efea9
--- /dev/null
+++ b/block.png
Binary files differ
diff --git a/dodo.py b/dodo.py
new file mode 100644
index 0000000..a809bde
--- /dev/null
+++ b/dodo.py
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: LGPL-2.1-or-later
+from os.path import dirname
+from pathlib import Path
+
+DOIT_CONFIG = {
+    "default_tasks": ["gds"],
+}
+
+
+top_dir = Path(dirname(__file__))
+
+code_dir = top_dir.joinpath("code")
+code_py_files = tuple(code_dir.rglob("*.py"))
+
+gds_dir = top_dir.joinpath("gds")
+gds_empty_file = gds_dir.joinpath("user_analog_project_wrapper_empty.gds")
+gds_out_file = gds_dir.joinpath("user_analog_project_wrapper.gds.gz")
+
+def task_gds():
+    """Generating GDS file with"""
+    def run():
+        from doitcode.generate import gen_gds
+
+        gen_gds(name="_empty_", gds_out=gds_out_file, gds_empty=gds_empty_file)
+
+    return {
+        "file_dep": code_py_files,
+        "targets": (gds_out_file,),
+        "actions": (run,),
+    }
\ No newline at end of file
diff --git a/doitcode/__init__.py b/doitcode/__init__.py
new file mode 100644
index 0000000..bd4fba4
--- /dev/null
+++ b/doitcode/__init__.py
@@ -0,0 +1 @@
+# SPDX-License-Identifier: LGPL-2.1-or-later
diff --git a/doitcode/bandgap.py b/doitcode/bandgap.py
new file mode 100644
index 0000000..4c38897
--- /dev/null
+++ b/doitcode/bandgap.py
@@ -0,0 +1,335 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+import sys
+from termios import TIOCPKT_FLUSHREAD
+from typing import List, Tuple, cast
+
+from pdkmaster.technology import geometry as _geo, primitive as _prm
+from pdkmaster.design import circuit as _ckt, layout as _lay, library as _lbry
+
+from c4m.pdk import sky130
+_prims = sky130.tech.primitives
+
+from . import frame as _frm
+
+
+__all__ = ["ConnectedBandGap"]
+
+
+class ConnectedBandGap(_lbry._Cell[_lbry.Library]):
+    def __init__(self, *, lib: _lbry.Library):
+        super().__init__(lib=lib, name="ConnectedBandGap")
+
+        ckt = self.new_circuit()
+        layouter = self.new_circuitlayouter()
+        layout = layouter.layout
+
+        li = cast(_prm.MetalWire, _prims.li)
+        assert li.pin is not None
+        lipin = li.pin[0]
+        mcon = cast(_prm.Via, _prims.mcon)
+        m1 = cast(_prm.MetalWire, _prims.m1)
+        assert m1.pin is not None
+        m1pin = m1.pin[0]
+        via = cast(_prm.Via, _prims.via)
+        m2 = cast(_prm.MetalWire, _prims.m2)
+        via2 = cast(_prm.Via, _prims.via2)
+        m3 = cast(_prm.MetalWire, _prims.m3)
+        assert m3.pin is not None
+        m3pin = m3.pin[0]
+        bnd = cast(_prm.Auxiliary, _prims.prBoundary)
+
+        nmos3v3 = cast(_prm.MOSFET, _prims.nfet_g5v0d10v5)
+        nmos1v8lvt = cast(_prm.MOSFET, _prims.nfet_01v8_lvt)
+        nmos1v8 = cast(_prm.MOSFET, _prims.nfet_01v8)
+        pmos3v3 = cast(_prm.MOSFET, _prims.pfet_g5v0d10v5)
+        pmos1v8lvt = cast(_prm.MOSFET, _prims.pfet_01v8_lvt)
+        pmos1v8 = cast(_prm.MOSFET, _prims.pfet_01v8)
+        pnp = sky130.macrolib.cells.PNP_05v5_W3u40L3u40
+        res = cast(_prm.Resistor, _prims.poly_res)
+
+        # Create the bandgap subcells
+        bg3v3_cell = sky130.BandgapCell(
+            lib=lib, name="Bandgap3V3",
+            nmos=nmos3v3, nmos_l=25.0, nmos_w=40.0,
+            pmos=pmos3v3, pmos_l=7.75, pmos_w=40.0,
+            pnp=pnp, pnp_ratio=2,
+            resistor=res, r1_height=13.055, r2_height=329.85,
+        )
+        lib.cells += bg3v3_cell
+        _bg3v3_bb = bg3v3_cell.layout.bounds()
+        assert _bg3v3_bb is not None
+        _bg3v3vref = bg3v3_cell.circuit.nets.vref
+        _bg3v3vref_m1pinbb = bg3v3_cell.layout.bounds(mask=m1pin.mask, net=_bg3v3vref)
+
+        bg1v8lvt_cell = sky130.BandgapCell(
+            lib=lib, name="Bandgap1V8lvt",
+            nmos=nmos1v8lvt, nmos_l=1.0, nmos_w=40.0,
+            pmos=pmos1v8lvt, pmos_l=25.0, pmos_w=40.0,
+            pnp=pnp, pnp_ratio=2,
+            resistor=res, r1_height=62.85, r2_height=1091.20,
+        )
+        lib.cells += bg1v8lvt_cell
+        _bg1v8lvt_bb = bg1v8lvt_cell.layout.bounds()
+        assert _bg1v8lvt_bb is not None
+        _bg1v8lvtvref = bg1v8lvt_cell.circuit.nets.vref
+        _bg1v8lvtvref_m1pinbb = bg1v8lvt_cell.layout.bounds(mask=m1pin.mask, net=_bg1v8lvtvref)
+
+        bg1v8_cell = sky130.BandgapCell(
+            lib=lib, name="Bandgap1V8",
+            nmos=nmos1v8, nmos_l=25.0, nmos_w=40.0,
+            pmos=pmos1v8, pmos_l=0.5, pmos_w=40.0,
+            pnp=pnp, pnp_ratio=2,
+            resistor=res, r1_height=32.14, r2_height=458.46,
+        )
+        lib.cells += bg1v8_cell
+        _bg1v8_bb = bg1v8_cell.layout.bounds()
+        assert _bg1v8_bb is not None
+        _bg1v8vref = bg1v8_cell.circuit.nets.vref
+        _bg1v8vref_m1pinbb = bg1v8_cell.layout.bounds(mask=m1pin.mask, net=_bg1v8vref)
+
+        # Instantiate the bandgap cells
+        bg3v3 = ckt.instantiate(bg3v3_cell, name="bg3v3")
+        bg1v8lvt = ckt.instantiate(bg1v8lvt_cell, name="bg1v8lvt")
+        bg1v8 = ckt.instantiate(bg1v8_cell, name="bg1v8")
+
+        # Add pins + nets for the io signals of the bandgap
+        vss3v3_pinname = "io_analog[7]"
+        vss3v3_m3pinbb = _frm.toppins[vss3v3_pinname]
+        vss3v3 = ckt.new_net(name=vss3v3_pinname, external=True, childports=bg3v3.ports.vss)
+        layouter.add_wire(net=vss3v3, wire=m3, pin=m3pin, shape=vss3v3_m3pinbb)
+
+        vdd3v3_pinname = "io_analog[9]"
+        vdd3v3_m3pinbb = _frm.toppins[vdd3v3_pinname]
+        vdd3v3 = ckt.new_net(name=vdd3v3_pinname, external=True, childports=bg3v3.ports.vdd)
+        layouter.add_wire(net=vdd3v3, wire=m3, pin=m3pin, shape=vdd3v3_m3pinbb)
+
+        vref3v3_pinname = "io_analog[8]"
+        vref3v3_m3pinbb = _frm.toppins[vref3v3_pinname]
+        vref3v3 = ckt.new_net(name=vref3v3_pinname, external=True, childports=bg3v3.ports.vref)
+        layouter.add_wire(net=vref3v3, wire=m3, pin=m3pin, shape=vref3v3_m3pinbb)
+
+        # vss and vdd are shared between bg1v8lvt and bg1v8
+        vss1v8_pinname = "io_analog[0]"
+        vss1v8_m3pinbb = _frm.toppins[vss1v8_pinname]
+        vss1v8 = ckt.new_net(name=vss1v8_pinname, external=True, childports=(
+            bg1v8.ports.vss, bg1v8lvt.ports.vss,
+        ))
+        layouter.add_wire(net=vss1v8, wire=m3, pin=m3pin, shape=vss1v8_m3pinbb)
+
+        vdd1v8_pinname = "io_analog[3]"
+        vdd1v8_m3pinbb = _frm.toppins[vdd1v8_pinname]
+        vdd1v8 = ckt.new_net(name=vdd1v8_pinname, external=True, childports=(
+            bg1v8.ports.vdd, bg1v8lvt.ports.vdd,
+        ))
+        layouter.add_wire(net=vdd1v8, wire=m3, pin=m3pin, shape=vdd1v8_m3pinbb)
+
+        vref1v8lvt_pinname = "io_analog[2]"
+        vref1v8lvt_m3pinbb = _frm.toppins[vref1v8lvt_pinname]
+        vref1v8lvt = ckt.new_net(
+            name=vref1v8lvt_pinname, external=True, childports=bg1v8lvt.ports.vref,
+        )
+        layouter.add_wire(net=vref1v8lvt, wire=m3, pin=m3pin, shape=vref1v8lvt_m3pinbb)
+
+        vref1v8_pinname = "io_analog[1]"
+        vref1v8_m3pinbb = _frm.toppins[vref1v8_pinname]
+        vref1v8 = ckt.new_net(
+            name=vref1v8_pinname, external=True, childports=bg1v8.ports.vref,
+        )
+        layouter.add_wire(net=vref1v8, wire=m3, pin=m3pin, shape=vref1v8_m3pinbb)
+
+        # Boundary
+        layout.boundary = _frm.boundary
+        layouter.add_portless(prim=bnd, shape=_frm.boundary)
+
+        # Place bg3v3, align vref pin with top pin
+        x = vref3v3_m3pinbb.center.x - _bg3v3vref_m1pinbb.center.x
+        y = vref3v3_m3pinbb.bottom - 5.0 - _bg3v3_bb.top
+        bg3v3_lay = layouter.place(bg3v3, x=x, y=y)
+        bg3v3vss_m1pinbb = bg3v3_lay.bounds(mask=m1pin.mask, net=vss3v3, depth=1)
+        bg3v3vss_m1pinbb = _geo.Rect.from_rect(
+            rect=bg3v3vss_m1pinbb, top=(bg3v3vss_m1pinbb.top + 5.0),
+        )
+        bg3v3vdd_m1pinbb = bg3v3_lay.bounds(mask=m1pin.mask, net=vdd3v3, depth=1)
+        bg3v3vdd_m1pinbb = _geo.Rect.from_rect(
+            rect=bg3v3vdd_m1pinbb, bottom=(bg3v3vdd_m1pinbb.bottom - 5.0),
+        )
+        bg3v3vref_m1pinbb = bg3v3_lay.bounds(mask=m1pin.mask, net=vref3v3, depth=1)
+        bg3v3vref_m1pinbb = _geo.Rect.from_rect(
+            rect=bg3v3vref_m1pinbb, right=(bg3v3vref_m1pinbb.right + 5.0),
+        )
+
+        # Place bg1v8lvt, align vref pin with top pin
+        x = vref1v8lvt_m3pinbb.center.x - _bg1v8lvtvref_m1pinbb.center.x
+        y = vref1v8lvt_m3pinbb.bottom - 10.0 - _bg1v8lvt_bb.top
+        bg1v8lvt_lay = layouter.place(bg1v8lvt, x=x, y=y)
+        bg1v8lvtvss_m1pinbb = bg1v8lvt_lay.bounds(mask=m1pin.mask, net=vss1v8, depth=1)
+        bg1v8lvtvss_m1pinbb = _geo.Rect.from_rect(
+            rect=bg1v8lvtvss_m1pinbb, top=(bg1v8lvtvss_m1pinbb.top + 5.0),
+        )
+        bg1v8lvtvss_m2pinbb = _geo.Rect.from_rect(
+            rect=bg1v8lvtvss_m1pinbb, bottom=vss1v8_m3pinbb.bottom,
+        )
+        bg1v8lvtvss_m3pinbb = _geo.Rect.from_rect(
+            rect=bg1v8lvtvss_m2pinbb, top=vss1v8_m3pinbb.top,
+        )
+        bg1v8lvtvdd_m1pinbb = bg1v8lvt_lay.bounds(mask=m1pin.mask, net=vdd1v8, depth=1)
+        bg1v8lvtvdd_m1pinbb = _geo.Rect.from_rect(
+            rect=bg1v8lvtvdd_m1pinbb, top=(bg1v8lvtvdd_m1pinbb.top + 6.0),
+        )
+        bg1v8lvtvdd_m2pinbb = _geo.Rect.from_rect(
+            rect=bg1v8lvtvdd_m1pinbb, bottom=(bg1v8lvtvdd_m1pinbb.top - 5.0),
+        )
+        bg1v8lvtvref_m1pinbb = bg1v8lvt_lay.bounds(mask=m1pin.mask, net=vref1v8lvt, depth=1)
+        bg1v8lvtvref_m1pinbb = _geo.Rect.from_rect(
+            rect=bg1v8lvtvref_m1pinbb, right=(bg1v8lvtvref_m1pinbb.right + 5.0),
+        )
+
+        # Place bg1v8 below bg1v8lvt
+        x = vref1v8_m3pinbb.center.x - _bg1v8vref_m1pinbb.center.x
+        y = vref1v8_m3pinbb.bottom - 10.0 - _bg1v8_bb.top
+        bg1v8_lay = layouter.place(bg1v8, x=x, y=y)
+        bg1v8vss_m1pinbb = bg1v8_lay.bounds(mask=m1pin.mask, net=vss1v8, depth=1)
+        bg1v8vss_m1pinbb = _geo.Rect.from_rect(
+            rect=bg1v8vss_m1pinbb, top=(bg1v8vss_m1pinbb.top + 5.0),
+        )
+        bg1v8vss_m2pinbb = _geo.Rect.from_rect(
+            rect=bg1v8vss_m1pinbb, bottom=vss1v8_m3pinbb.bottom,
+        )
+        bg1v8vss_m3pinbb = _geo.Rect.from_rect(
+            rect=bg1v8vss_m2pinbb, top=vss1v8_m3pinbb.top,
+        )
+        bg1v8vdd_m1pinbb = bg1v8_lay.bounds(mask=m1pin.mask, net=vdd1v8, depth=1)
+        bg1v8vdd_m1pinbb = _geo.Rect.from_rect(
+            rect=bg1v8vdd_m1pinbb, top=(bg1v8vdd_m1pinbb.top + 6.0),
+        )
+        bg1v8vdd_m2pinbb = _geo.Rect.from_rect(
+            rect=bg1v8vdd_m1pinbb, bottom=(bg1v8vdd_m1pinbb.top - 5.0),
+        )
+        bg1v8vref_m1pinbb = bg1v8_lay.bounds(mask=m1pin.mask, net=vref1v8, depth=1)
+        bg1v8vref_m1pinbb = _geo.Rect.from_rect(
+            rect=bg1v8vref_m1pinbb, right=(bg1v8vref_m1pinbb.right + 5.0),
+        )
+
+        # vss3v3
+        net = vss3v3
+
+        layouter.add_wire(
+            net=net, wire=via, bottom_shape=bg3v3vss_m1pinbb, top_shape=bg3v3vss_m1pinbb,
+        )
+        lay = layouter.add_wire(
+            net=net, wire=via2, bottom_shape=bg3v3vss_m1pinbb, top_shape=bg3v3vss_m1pinbb,
+        )
+        m3bb = lay.bounds(mask=m3.mask)
+
+        shape = _geo.Rect.from_rect(rect=m3bb, right=vss3v3_m3pinbb.right)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        shape = _geo.Rect.from_rect(rect=vss3v3_m3pinbb, bottom=m3bb.bottom)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        # vdd3v3
+        net = vdd3v3
+
+        layouter.add_wire(
+            net=net, wire=via, bottom_shape=bg3v3vdd_m1pinbb, top_shape=bg3v3vdd_m1pinbb,
+        )
+        lay = layouter.add_wire(
+            net=net, wire=via2, bottom_shape=bg3v3vdd_m1pinbb, top_shape=bg3v3vdd_m1pinbb,
+        )
+        m3bb = lay.bounds(mask=m3.mask)
+
+        shape = _geo.Rect.from_rect(rect=m3bb, left=vdd3v3_m3pinbb.left)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        shape = _geo.Rect.from_rect(rect=vdd3v3_m3pinbb, bottom=m3bb.bottom)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        # vref3v3
+        net = vref3v3
+
+        layouter.add_wire(
+            net=net, wire=via, bottom_shape=bg3v3vref_m1pinbb, top_shape=bg3v3vref_m1pinbb,
+        )
+        lay = layouter.add_wire(
+            net=net, wire=via2, bottom_shape=bg3v3vref_m1pinbb, top_shape=bg3v3vref_m1pinbb,
+        )
+        m3bb = lay.bounds(mask=m3.mask)
+
+        shape = _geo.Rect.from_rect(rect=m3bb, top=vref3v3_m3pinbb.bottom)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        # vss1v8
+        net = vss1v8
+
+        layouter.add_wire(
+            net=net, wire=via,
+            bottom_shape=bg1v8lvtvss_m1pinbb, top_shape=bg1v8lvtvss_m2pinbb,
+        )
+        layouter.add_wire(
+            net=net, wire=via,
+            bottom_shape=bg1v8vss_m1pinbb, top_shape=bg1v8vss_m2pinbb,
+        )
+
+        layouter.add_wire(
+            net=net, wire=via2,
+            bottom_shape=bg1v8lvtvss_m3pinbb, top_shape=bg1v8lvtvss_m3pinbb,
+        )
+        layouter.add_wire(
+            net=net, wire=via2,
+            bottom_shape=bg1v8vss_m3pinbb, top_shape=bg1v8vss_m3pinbb,
+        )
+
+        shape = _geo.Rect.from_rect(rect=bg1v8lvtvss_m3pinbb, right=vss1v8_m3pinbb.right)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        # vdd1v8
+        net = vdd1v8
+
+        layouter.add_wire(
+            net=net, wire=via,
+            bottom_shape=bg1v8lvtvdd_m1pinbb, top_shape=bg1v8lvtvdd_m2pinbb,
+        )
+        layouter.add_wire(
+            net=net, wire=via,
+            bottom_shape=bg1v8vdd_m1pinbb, top_shape=bg1v8vdd_m2pinbb,
+        )
+        via2bb = _geo.Rect.from_rect(
+            rect=bg1v8vdd_m2pinbb, left=vdd1v8_m3pinbb.left, right=vdd1v8_m3pinbb.right,
+        )
+        layouter.add_wire(
+            net=net, wire=via2, bottom_shape=via2bb, top_shape=via2bb,
+        )
+        shape = _geo.Rect.from_rect(rect=via2bb, right=bg1v8vdd_m2pinbb.right)
+        layouter.add_wire(net=net, wire=m2, shape=shape)
+        shape = _geo.Rect.from_rect(rect=via2bb, top=vdd1v8_m3pinbb.top)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        # vref1v8lvt
+        net = vref1v8lvt
+
+        layouter.add_wire(
+            net=net, wire=via,
+            bottom_shape=bg1v8lvtvref_m1pinbb, top_shape=bg1v8lvtvref_m1pinbb,
+        )
+        lay = layouter.add_wire(
+            net=net, wire=via2,
+            bottom_shape=bg1v8lvtvref_m1pinbb, top_shape=bg1v8lvtvref_m1pinbb,
+        )
+        m3bb = lay.bounds(mask=m3.mask)
+
+        shape = _geo.Rect.from_rect(rect=m3bb, top=vref1v8lvt_m3pinbb.bottom)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        # vref1v8
+        net = vref1v8
+
+        layouter.add_wire(
+            net=net, wire=via,
+            bottom_shape=bg1v8vref_m1pinbb, top_shape=bg1v8vref_m1pinbb,
+        )
+        lay = layouter.add_wire(
+            net=net, wire=via2,
+            bottom_shape=bg1v8vref_m1pinbb, top_shape=bg1v8vref_m1pinbb,
+        )
+        m3bb = lay.bounds(mask=m3.mask)
+
+        shape = _geo.Rect.from_rect(rect=m3bb, top=vref1v8_m3pinbb.bottom)
+        layouter.add_wire(net=net, wire=m3, shape=shape)
diff --git a/doitcode/frame.py b/doitcode/frame.py
new file mode 100644
index 0000000..9bf5d39
--- /dev/null
+++ b/doitcode/frame.py
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: LGPL-2.1-or-later
+from pdkmaster.technology import geometry as _geo
+
+
+__all__ = ["boundary", "toppins"]
+
+
+# The metal3 pins for the IOs
+boundary = _geo.Rect(left=0.0, bottom=0.0, right=2920.0, top=3520.0)
+toppins = {
+    "io_in_3v3[0]": _geo.Rect(left=2917.60, bottom=7.72, right=2924.00, top=8.28),
+    "io_in[0]": _geo.Rect(left=2917.60, bottom=13.63, right=2924.00, top=14.19),
+    "io_out[0]": _geo.Rect(left=2917.60, bottom=19.54, right=2924.00, top=20.10),
+    "io_oeb[0]": _geo.Rect(left=2917.60, bottom=25.45, right=2924.00, top=26.01),
+    "io_in_3v3[1]": _geo.Rect(left=2917.60, bottom=31.36, right=2924.00, top=31.92),
+    "io_in[1]": _geo.Rect(left=2917.60, bottom=37.27, right=2924.00, top=37.83),
+    "io_out[1]": _geo.Rect(left=2917.60, bottom=43.18, right=2924.00, top=43.74),
+    "io_oeb[1]": _geo.Rect(left=2917.60, bottom=49.09, right=2924.00, top=49.65),
+    "io_in_3v3[2]": _geo.Rect(left=2917.60, bottom=55.00, right=2924.00, top=55.56),
+    "io_in[2]": _geo.Rect(left=2917.60, bottom=60.91, right=2924.00, top=61.47),
+    "io_out[2]": _geo.Rect(left=2917.60, bottom=66.82, right=2924.00, top=67.38),
+    "io_oeb[2]": _geo.Rect(left=2917.60, bottom=72.73, right=2924.00, top=73.29),
+    "io_in_3v3[3]": _geo.Rect(left=2917.60, bottom=78.64, right=2924.00, top=79.20),
+    "io_in[3]": _geo.Rect(left=2917.60, bottom=84.55, right=2924.00, top=85.11),
+    "io_out[3]": _geo.Rect(left=2917.60, bottom=90.46, right=2924.00, top=91.02),
+    "io_oeb[3]": _geo.Rect(left=2917.60, bottom=96.37, right=2924.00, top=96.93),
+    "io_in_3v3[4]": _geo.Rect(left=2917.60, bottom=102.28, right=2924.00, top=102.84),
+    "io_in[4]": _geo.Rect(left=2917.60, bottom=108.19, right=2924.00, top=108.75),
+    "io_out[4]": _geo.Rect(left=2917.60, bottom=114.10, right=2924.00, top=114.66),
+    "io_oeb[4]": _geo.Rect(left=2917.60, bottom=120.01, right=2924.00, top=120.57),
+    "io_in_3v3[5]": _geo.Rect(left=2917.60, bottom=234.57, right=2924.00, top=235.13),
+    "io_in[5]": _geo.Rect(left=2917.60, bottom=240.48, right=2924.00, top=241.04),
+    "io_out[5]": _geo.Rect(left=2917.60, bottom=246.39, right=2924.00, top=246.95),
+    "io_oeb[5]": _geo.Rect(left=2917.60, bottom=252.30, right=2924.00, top=252.86),
+    "io_in_3v3[6]": _geo.Rect(left=2917.60, bottom=457.86, right=2924.00, top=458.42),
+    "io_in[6]": _geo.Rect(left=2917.60, bottom=463.77, right=2924.00, top=464.33),
+    "io_out[6]": _geo.Rect(left=2917.60, bottom=469.68, right=2924.00, top=470.24),
+    "io_oeb[6]": _geo.Rect(left=2917.60, bottom=475.59, right=2924.00, top=476.15),
+    "gpio_analog[0]": _geo.Rect(left=2917.60, bottom=1346.15, right=2924.00, top=1346.71),
+    "gpio_noesd[0]": _geo.Rect(left=2917.60, bottom=1352.06, right=2924.00, top=1352.62),
+    "io_in_3v3[7]": _geo.Rect(left=2917.60, bottom=1357.97, right=2924.00, top=1358.53),
+    "io_in[7]": _geo.Rect(left=2917.60, bottom=1363.88, right=2924.00, top=1364.44),
+    "io_out[7]": _geo.Rect(left=2917.60, bottom=1369.79, right=2924.00, top=1370.35),
+    "io_oeb[7]": _geo.Rect(left=2917.60, bottom=1375.70, right=2924.00, top=1376.26),
+    "gpio_analog[1]": _geo.Rect(left=2917.60, bottom=1568.26, right=2924.00, top=1568.82),
+    "gpio_noesd[1]": _geo.Rect(left=2917.60, bottom=1574.17, right=2924.00, top=1574.73),
+    "io_in_3v3[8]": _geo.Rect(left=2917.60, bottom=1580.08, right=2924.00, top=1580.64),
+    "io_in[8]": _geo.Rect(left=2917.60, bottom=1585.99, right=2924.00, top=1586.55),
+    "io_out[8]": _geo.Rect(left=2917.60, bottom=1591.90, right=2924.00, top=1592.46),
+    "io_oeb[8]": _geo.Rect(left=2917.60, bottom=1597.81, right=2924.00, top=1598.37),
+    "gpio_analog[2]": _geo.Rect(left=2917.60, bottom=1794.37, right=2924.00, top=1794.93),
+    "gpio_noesd[2]": _geo.Rect(left=2917.60, bottom=1800.28, right=2924.00, top=1800.84),
+    "io_in_3v3[9]": _geo.Rect(left=2917.60, bottom=1806.19, right=2924.00, top=1806.75),
+    "io_in[9]": _geo.Rect(left=2917.60, bottom=1812.10, right=2924.00, top=1812.66),
+    "io_out[9]": _geo.Rect(left=2917.60, bottom=1818.01, right=2924.00, top=1818.57),
+    "io_oeb[9]": _geo.Rect(left=2917.60, bottom=1823.92, right=2924.00, top=1824.48),
+    "gpio_analog[3]": _geo.Rect(left=2917.60, bottom=2026.48, right=2924.00, top=2027.04),
+    "gpio_noesd[3]": _geo.Rect(left=2917.60, bottom=2032.39, right=2924.00, top=2032.95),
+    "io_in_3v3[10]": _geo.Rect(left=2917.60, bottom=2038.30, right=2924.00, top=2039.86),
+    "io_in[10]": _geo.Rect(left=2917.60, bottom=2044.21, right=2924.00, top=2044.77),
+    "io_out[10]": _geo.Rect(left=2917.60, bottom=2050.12, right=2924.00, top=2050.68),
+    "io_oeb[10]": _geo.Rect(left=2917.60, bottom=2056.03, right=2924.00, top=2056.59),
+    "gpio_analog[4]": _geo.Rect(left=2917.60, bottom=2248.59, right=2924.00, top=2249.15),
+    "gpio_noesd[4]": _geo.Rect(left=2917.60, bottom=2254.50, right=2924.00, top=2255.06),
+    "io_in_3v3[11]": _geo.Rect(left=2917.60, bottom=2260.41, right=2924.00, top=2260.97),
+    "io_in[11]": _geo.Rect(left=2917.60, bottom=2266.32, right=2924.00, top=2266.88),
+    "io_out[11]": _geo.Rect(left=2917.60, bottom=2272.23, right=2924.00, top=2272.79),
+    "io_oeb[11]": _geo.Rect(left=2917.60, bottom=2278.14, right=2924.00, top=2278.70),
+    "gpio_analog[5]": _geo.Rect(left=2917.60, bottom=2470.70, right=2924.00, top=2471.26),
+    "gpio_noesd[5]": _geo.Rect(left=2917.60, bottom=2476.61, right=2924.00, top=2477.17),
+    "io_in_3v3[12]": _geo.Rect(left=2917.60, bottom=2482.52, right=2924.00, top=2483.08),
+    "io_in[12]": _geo.Rect(left=2917.60, bottom=2488.43, right=2924.00, top=2488.99),
+    "io_out[12]": _geo.Rect(left=2917.60, bottom=2494.34, right=2924.00, top=2494.90),
+    "io_oeb[12]": _geo.Rect(left=2917.60, bottom=2500.25, right=2924.00, top=2500.81),
+    "gpio_analog[6]": _geo.Rect(left=2917.60, bottom=2917.81, right=2924.00, top=2918.37),
+    "gpio_noesd[6]": _geo.Rect(left=2917.60, bottom=2923.72, right=2924.00, top=2924.28),
+    "io_in_3v3[13]": _geo.Rect(left=2917.60, bottom=2929.63, right=2924.00, top=2930.19),
+    "io_in[13]": _geo.Rect(left=2917.60, bottom=2935.54, right=2924.00, top=2936.10),
+    "io_out[13]": _geo.Rect(left=2917.60, bottom=2941.45, right=2924.00, top=2942.01),
+    "io_oeb[13]": _geo.Rect(left=2917.60, bottom=2947.36, right=2924.00, top=2947.92),
+    "io_analog[0]": _geo.Rect(left=2911.50, bottom=3389.92, right=2924.00, top=3414.92),
+    "io_analog[1]": _geo.Rect(left=2832.97, bottom=3511.50, right=2857.97, top=3524.00),
+    "io_analog[2]": _geo.Rect(left=2326.97, bottom=3511.50, right=2351.97, top=3524.00),
+    "io_analog[3]": _geo.Rect(left=2066.97, bottom=3511.50, right=2091.97, top=3524.00),
+    "io_analog[4]": _geo.Rect(left=1594.97, bottom=3511.50, right=1619.97, top=3524.00),
+    "io_clamp_low[0]": _geo.Rect(left=1621.47, bottom=3511.50, right=1632.47, top=3524.00),
+    "io_clamp_high[0]": _geo.Rect(left=1633.97, bottom=3511.50, right=1644.97, top=3524.00),
+    "io_analog[5]": _geo.Rect(left=1086.47, bottom=3511.50, right=1111.47, top=3524.00),
+    "io_clamp_low[1]": _geo.Rect(left=1112.97, bottom=3511.50, right=1123.97, top=3524.00),
+    "io_clamp_high[1]": _geo.Rect(left=1125.47, bottom=3511.50, right=1136.47, top=3524.00),
+    "io_analog[6]": _geo.Rect(left=827.97, bottom=3511.50, right=852.97, top=3524.00),
+    "io_clamp_low[2]": _geo.Rect(left=854.47, bottom=3511.50, right=865.47, top=3524.00),
+    "io_clamp_high[2]": _geo.Rect(left=866.97, bottom=3511.50, right=877.97, top=3524.00),
+    "io_analog[7]": _geo.Rect(left=600.97, bottom=3511.50, right=625.97, top=3524.00),
+    "io_analog[8]": _geo.Rect(left=340.97, bottom=3511.50, right=365.97, top=3524.00),
+    "io_analog[9]": _geo.Rect(left=80.97, bottom=3511.50, right=105.97, top=3524.00),
+    "io_analog[10]": _geo.Rect(left=-4.00, bottom=3401.21, right=8.50, top=3426.21),
+    "io_oeb[14]": _geo.Rect(left=-4.00, bottom=2528.10, right=2.40, top=2528.66),
+    "io_out[14]": _geo.Rect(left=-4.00, bottom=2534.01, right=2.40, top=2534.57),
+    "io_in[14]": _geo.Rect(left=-4.00, bottom=2539.92, right=2.40, top=2540.48),
+    "io_in_3v3[14]": _geo.Rect(left=-4.00, bottom=2545.83, right=2.40, top=2546.39),
+    "gpio_noesd[7]": _geo.Rect(left=-4.00, bottom=2551.74, right=2.40, top=2552.30),
+    "gpio_analog[7]": _geo.Rect(left=-4.00, bottom=2557.65, right=2.40, top=2558.21),
+    "io_oeb[15]": _geo.Rect(left=-4.00, bottom=2311.99, right=2.40, top=2312.55),
+    "io_out[15]": _geo.Rect(left=-4.00, bottom=2317.90, right=2.40, top=2318.46),
+    "io_in[15]": _geo.Rect(left=-4.00, bottom=2323.81, right=2.40, top=2324.37),
+    "io_in_3v3[15]": _geo.Rect(left=-4.00, bottom=2329.72, right=2.40, top=2330.28),
+    "gpio_noesd[8]": _geo.Rect(left=-4.00, bottom=2335.63, right=2.40, top=2336.19),
+    "gpio_analog[8]": _geo.Rect(left=-4.00, bottom=2341.54, right=2.40, top=2342.10),
+    "io_oeb[16]": _geo.Rect(left=-4.00, bottom=2095.88, right=2.40, top=2096.44),
+    "io_out[16]": _geo.Rect(left=-4.00, bottom=2101.79, right=2.40, top=2102.35),
+    "io_in[16]": _geo.Rect(left=-4.00, bottom=2107.70, right=2.40, top=2108.26),
+    "io_in_3v3[16]": _geo.Rect(left=-4.00, bottom=2113.61, right=2.40, top=2114.17),
+    "gpio_noesd[9]": _geo.Rect(left=-4.00, bottom=2119.52, right=2.40, top=2120.08),
+    "gpio_analog[9]": _geo.Rect(left=-4.00, bottom=2125.43, right=2.40, top=2125.99),
+    "io_oeb[17]": _geo.Rect(left=-4.00, bottom=1879.77, right=2.40, top=1880.33),
+    "io_out[17]": _geo.Rect(left=-4.00, bottom=1885.68, right=2.40, top=1886.24),
+    "io_in[17]": _geo.Rect(left=-4.00, bottom=1891.59, right=2.40, top=1892.15),
+    "io_in_3v3[17]": _geo.Rect(left=-4.00, bottom=1897.50, right=2.40, top=1898.06),
+    "gpio_noesd[10]": _geo.Rect(left=-4.00, bottom=1903.41, right=2.40, top=1903.97),
+    "gpio_analog[10]": _geo.Rect(left=-4.00, bottom=1909.32, right=2.40, top=1909.88),
+    "io_oeb[18]": _geo.Rect(left=-4.00, bottom=1663.66, right=2.40, top=1664.22),
+    "io_out[18]": _geo.Rect(left=-4.00, bottom=1669.57, right=2.40, top=1670.13),
+    "io_in[18]": _geo.Rect(left=-4.00, bottom=1675.48, right=2.40, top=1676.04),
+    "io_in_3v3[18]": _geo.Rect(left=-4.00, bottom=1681.39, right=2.40, top=1681.95),
+    "gpio_noesd[11]": _geo.Rect(left=-4.00, bottom=1687.30, right=2.40, top=1687.86),
+    "gpio_analog[11]": _geo.Rect(left=-4.00, bottom=1693.21, right=2.40, top=1693.77),
+    "io_oeb[19]": _geo.Rect(left=-4.00, bottom=1447.55, right=2.40, top=1448.11),
+    "io_out[19]": _geo.Rect(left=-4.00, bottom=1453.46, right=2.40, top=1454.02),
+    "io_in[19]": _geo.Rect(left=-4.00, bottom=1459.37, right=2.40, top=1459.93),
+    "io_in_3v3[19]": _geo.Rect(left=-4.00, bottom=1465.28, right=2.40, top=1465.84),
+    "gpio_noesd[12]": _geo.Rect(left=-4.00, bottom=1471.19, right=2.40, top=1471.75),
+    "gpio_analog[12]": _geo.Rect(left=-4.00, bottom=1477.10, right=2.40, top=1477.66),
+    "io_oeb[20]": _geo.Rect(left=-4.00, bottom=1232.44, right=2.40, top=1233.00),
+    "io_out[20]": _geo.Rect(left=-4.00, bottom=1238.35, right=2.40, top=1238.91),
+    "io_in[20]": _geo.Rect(left=-4.00, bottom=1244.26, right=2.40, top=1244.82),
+    "io_in_3v3[20]": _geo.Rect(left=-4.00, bottom=1250.17, right=2.40, top=1250.73),
+    "gpio_noesd[13]": _geo.Rect(left=-4.00, bottom=1256.08, right=2.40, top=1256.64),
+    "gpio_analog[13]": _geo.Rect(left=-4.00, bottom=1261.99, right=2.40, top=1262.55),
+    "io_oeb[21]": _geo.Rect(left=-4.00, bottom=594.33, right=2.40, top=594.89),
+    "io_out[21]": _geo.Rect(left=-4.00, bottom=600.24, right=2.40, top=600.80),
+    "io_in[21]": _geo.Rect(left=-4.00, bottom=606.15, right=2.40, top=606.71),
+    "io_in_3v3[21]": _geo.Rect(left=-4.00, bottom=612.06, right=2.40, top=612.62),
+    "gpio_noesd[14]": _geo.Rect(left=-4.00, bottom=617.97, right=2.40, top=618.53),
+    "gpio_analog[14]": _geo.Rect(left=-4.00, bottom=623.88, right=2.40, top=624.44),
+    "io_oeb[22]": _geo.Rect(left=-4.00, bottom=378.22, right=2.40, top=378.78),
+    "io_out[22]": _geo.Rect(left=-4.00, bottom=384.13, right=2.40, top=384.69),
+    "io_in[22]": _geo.Rect(left=-4.00, bottom=390.04, right=2.40, top=390.60),
+    "io_in_3v3[22]": _geo.Rect(left=-4.00, bottom=395.95, right=2.40, top=396.51),
+    "gpio_noesd[15]": _geo.Rect(left=-4.00, bottom=401.86, right=2.40, top=402.42),
+    "gpio_analog[15]": _geo.Rect(left=-4.00, bottom=407.77, right=2.40, top=408.33),
+    "io_oeb[23]": _geo.Rect(left=-4.00, bottom=162.11, right=2.40, top=162.67),
+    "io_out[23]": _geo.Rect(left=-4.00, bottom=168.02, right=2.40, top=168.58),
+    "io_in[23]": _geo.Rect(left=-4.00, bottom=173.93, right=2.40, top=174.49),
+    "io_in_3v3[23]": _geo.Rect(left=-4.00, bottom=179.84, right=2.40, top=180.40),
+    "gpio_noesd[16]": _geo.Rect(left=-4.00, bottom=185.75, right=2.40, top=186.31),
+    "gpio_analog[16]": _geo.Rect(left=-4.00, bottom=191.66, right=2.40, top=192.22),
+    "io_oeb[24]": _geo.Rect(left=-4.00, bottom=55.00, right=2.40, top=55.56),
+    "io_out[24]": _geo.Rect(left=-4.00, bottom=60.91, right=2.40, top=61.47),
+    "io_in[24]": _geo.Rect(left=-4.00, bottom=66.82, right=2.40, top=67.38),
+    "io_in_3v3[24]": _geo.Rect(left=-4.00, bottom=72.73, right=2.40, top=73.29),
+    "gpio_noesd[17]": _geo.Rect(left=-4.00, bottom=78.64, right=2.40, top=79.20),
+    "gpio_analog[17]": _geo.Rect(left=-4.00, bottom=84.55, right=2.40, top=85.11),
+    "io_oeb[25]": _geo.Rect(left=-4.00, bottom=31.36, right=2.40, top=31.92),
+    "io_out[25]": _geo.Rect(left=-4.00, bottom=37.27, right=2.40, top=37.83),
+    "io_in[25]": _geo.Rect(left=-4.00, bottom=43.18, right=2.40, top=43.74),
+    "io_in_3v3[25]": _geo.Rect(left=-4.00, bottom=49.09, right=2.40, top=49.65),
+    "io_oeb[26]": _geo.Rect(left=-4.00, bottom=7.72, right=2.40, top=8.28),
+    "io_out[26]": _geo.Rect(left=-4.00, bottom=13.63, right=2.40, top=14.19),
+    "io_in[26]": _geo.Rect(left=-4.00, bottom=19.54, right=2.40, top=20.10),
+    "io_in_3v3[26]": _geo.Rect(left=-4.00, bottom=25.45, right=2.40, top=26.01),
+    # TODO: vss*, vdd*, ioclamp*, wb(s)_*, la_data*, user_clock2, user_irq
+    "vccd1": _geo.Rect(left=2911.70, bottom=3148.92, right=2924.00, top=3172.92),
+    "vssd1": _geo.Rect(left=2911.70, bottom=957.15, right=2924.00, top=981.15),
+    # "vdda2": _geo.Rect(left=-4.00, bottom=1074.44, right=8.30, top=1098.44),
+    # "vdda2": _geo.Rect(left=-4.00, bottom=1024.44, right=8.30, top=1048.44),
+    # "vssd2": _geo.Rect(left=-4.00, bottom=864.44, right=8.30, top=888.44),
+    # "vssd2": _geo.Rect(left=-4.00, bottom=814.44, right=8.30, top=838.44),
+}
diff --git a/doitcode/generate.py b/doitcode/generate.py
new file mode 100644
index 0000000..8297498
--- /dev/null
+++ b/doitcode/generate.py
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# PDKMaster & co. don't put a license requirement on the generated files.
+# The generated gds files in this project are released under the LGPL 2.0 or later license.
+from pathlib import Path
+from typing import Any, cast
+
+import pya as _pya
+# Disable type checking
+pya = cast(Any, _pya)
+
+from pdkmaster.technology import geometry as _geo
+from pdkmaster.design import library as _lib
+from pdkmaster.io.klayout import export as _klexp
+
+from c4m.pdk import sky130
+
+from . import frame as _frm, sram as _ram, bandgap as _bg
+
+
+__all__ = ["gen_gds"]
+
+
+def _postprocess(*, klay: "pya.Layout"):
+    # Post process
+    # - split tapdiff into tap and diff layers
+    # - remove pad drawing layer to avoid interacting with RDL
+    nwell_idx = klay.layer(64, 20)
+    diff_idx = klay.layer(65, 20)
+    tap_idx = klay.layer(65, 44)
+    nsdm_idx = klay.layer(93, 44)
+    psdm_idx = klay.layer(94, 20)
+    pad_idx = klay.layer(76, 20)
+
+    for cell in klay.each_cell():
+        nwell = pya.Region(cell.shapes(nwell_idx))
+        nsdm = pya.Region(cell.shapes(nsdm_idx))
+        psdm = pya.Region(cell.shapes(psdm_idx))
+
+        tap_cover = (nsdm & nwell) + (psdm - nwell)
+
+        diff_shapes = cell.shapes(diff_idx)
+        tap_shapes = cell.shapes(tap_idx)
+
+        difftap = pya.Region(cell.shapes(diff_idx)) # Original difftap layer to be split
+
+        tap = difftap & tap_cover
+        diff = difftap - tap
+
+        diff_shapes.clear()
+        diff_shapes.insert(diff)
+        tap_shapes.insert(tap)
+
+        cell.shapes(pad_idx).clear()
+
+
+def gen_gds(*, name: str, gds_out: Path, gds_empty: Path):
+    top_name = "user_analog_project_wrapper"
+
+    lib = _lib.Library(
+        name=name, tech=sky130.tech, cktfab=sky130.cktfab, layoutfab=sky130.layoutfab,
+    )
+
+    # Create user_analog_project_wrapper top cell
+    top = lib.new_cell(name=top_name)
+    ckt = top.new_circuit()
+    layouter = top.new_circuitlayouter()
+
+    # Add the BandGap
+    bandgap_cell = _bg.ConnectedBandGap(lib=lib)
+    bandgap_inst = ckt.instantiate(bandgap_cell, name="bandgaptop")
+    layouter.place(bandgap_inst, x=0.0, y=0.0)
+
+    # Add the SRAM
+    sram_cell = _ram.ConnectedSRAM(lib=lib)
+    sram_inst = ckt.instantiate(sram_cell, name="sramtop")
+    layouter.place(sram_inst, origin=_geo.origin)
+
+    lib.cells += (bandgap_cell, sram_cell)
+
+    # Add circuit and
+    layouter.layout.boundary = _frm.boundary
+
+    # Convert to klayout
+    klay = _klexp.export2db(
+        obj=lib, add_pin_label=True, gds_layers=sky130.gds_layers, cell_name=None, merge=True,
+    )
+
+    _postprocess(klay=klay)
+
+    # Instantiate the empty cell in top cell
+    emptylib = pya.Library()
+    emptylib.register("empty")
+    emptylayout = emptylib.layout()
+    emptylayout.read(str(gds_empty))
+    emptylibcell_idx = emptylayout.cell("user_analog_project_wrapper_empty").cell_index()
+    emptycell_idx = klay.add_lib_cell(emptylib, emptylibcell_idx)
+
+    ktop = klay.cell(top_name)
+    ktop.insert(pya.CellInstArray(emptycell_idx, pya.Trans.R0))
+
+    ktech = pya.Technology.technology_by_name("Skywater_S8")
+    ksaveopts = ktech.save_layout_options.dup()
+    ksaveopts.write_context_info = False
+    klay.write(str(gds_out), ksaveopts)
diff --git a/doitcode/sram.py b/doitcode/sram.py
new file mode 100644
index 0000000..71438b1
--- /dev/null
+++ b/doitcode/sram.py
@@ -0,0 +1,2636 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+from typing import Optional, List, Tuple, Union, cast
+from pandas import notna
+
+from pdkmaster.technology import geometry as _geo, primitive as _prm
+from pdkmaster.design import circuit as _ckt, library as _lbry
+
+from c4m import flexmem as _mem
+from c4m.pdk import sky130
+
+from . import frame as _frm
+
+
+__all__ = ["ConnectedSRAM"]
+
+
+class _io_spec:
+    def __init__(self, *,
+        sram_signal: Union[str, Tuple[str, str, str]],
+        io_type: str, io_number: int,
+    ):
+        assert io_type in ("io_in", "io_out", "io_analog")
+        assert (io_type != "io_inout") or isinstance(sram_signal, tuple)
+        self.sram_signal = sram_signal
+        self.io_type = io_type
+        self.io_number = io_number
+
+    @property
+    def prefix(self) -> str:
+        if self.io_type in ("io_in", "io_out", "io_inout"):
+            return f"io{self.io_number}"
+        elif self.io_type == "io_analog":
+            return f"ioa{self.io_number}"
+        elif self.io_type == "gpio":
+            return f"gpio{self.io_number}"
+        else:
+            raise NotImplementedError(f"io_type == '{self.io_type}'")
+
+    @property
+    def toppin_name(self) -> str:
+        num = self.io_number
+        if self.io_type == "io_in":
+            return f"io_in[{num}]"
+        elif self.io_type == "io_out":
+            return f"io_out[{num}]"
+        elif self.io_type == "io_analog":
+            return f"io_analog[{num}]"
+        else:
+            raise NotImplementedError(f"io_type == {self.io_type}")
+
+    @property
+    def oeb(self) -> Optional[bool]:
+        if self.io_type == "io_in":
+            return True
+        elif self.io_type == "io_out":
+            return False
+        else:
+            return None
+
+
+io_spspecs = (
+    _io_spec(sram_signal="in_shiftclk", io_type="io_in", io_number=14),
+    _io_spec(sram_signal="shift_in", io_type="io_in", io_number=15),
+    _io_spec(sram_signal="in_captureclk_l", io_type="io_out", io_number=16),
+    _io_spec(sram_signal="in_captureclk", io_type="io_in", io_number=17),
+    _io_spec(sram_signal="sramclk", io_type="io_in", io_number=18),
+    _io_spec(sram_signal="out_captureclk_l", io_type="io_out", io_number=13),
+    _io_spec(sram_signal="out_captureclk", io_type="io_in", io_number=12),
+    _io_spec(sram_signal="out_docapture", io_type="io_in", io_number=11),
+    _io_spec(sram_signal="out_shiftclk", io_type="io_in", io_number=10),
+    _io_spec(sram_signal="shift_out", io_type="io_out", io_number=9),
+)
+io_spsig2spec = {
+    spec.sram_signal: spec
+    for spec in io_spspecs
+}
+io_sppin2spec = {
+    spec.toppin_name: spec
+    for spec in io_spspecs
+}
+
+
+io_specs = (
+    _io_spec(sram_signal="svdd", io_type="io_analog", io_number=4),
+    _io_spec(sram_signal="svss", io_type="io_analog", io_number=5),
+)
+io_sig2spec = {
+    spec.sram_signal: spec
+    for spec in io_specs
+}
+io_pin2spec = {
+    spec.toppin_name: spec
+    for spec in io_specs
+}
+
+
+class SPCharacterizationWrapper(_lbry._OnDemandCell[_lbry.Library]):
+    def __init__(self, *,
+        lib: _lbry.Library, spcell: _mem.sp6t.factory._SP6TBlock,
+    ):
+        name = f"Char{spcell.name}"
+        super().__init__(lib=lib, name=name)
+        self.spcell = spcell
+
+    def _create_circuit(self):
+        stdcells = sky130.stdcelllib.cells
+        ff_cell = stdcells.sff1_x4
+        mux_cell = stdcells.mx2_x2
+
+        spcell = self.spcell
+        self.a_bits = a_bits = spcell.a_bits
+        self.word_size = word_size = spcell.word_size
+        self.we_size = we_size = spcell.we_size
+        assert word_size%we_size == 0
+        self.byte_size = byte_size = word_size//we_size
+
+        ckt = self.new_circuit()
+
+        # Registers for shifting and capturing the inputs for the sram
+        # Order is aligned with the layout
+        _in_shiftreg: List[_ckt._CellInstance] = []
+        _in_capturereg: List[_ckt._CellInstance] = []
+        for n_a in range(a_bits):
+            _in_shiftreg.append(ckt.instantiate(ff_cell, name=f"aff_s[{n_a}]"))
+            _in_capturereg.append(ckt.instantiate(ff_cell, name=f"aff_c[{n_a}]"))
+        for n_we in range(we_size):
+            _in_shiftreg.append(ckt.instantiate(ff_cell, name=f"weff_s[{n_we}]"))
+            _in_capturereg.append(ckt.instantiate(ff_cell, name=f"weff_c[{n_we}]"))
+            for n_byte in range(byte_size):
+                n_bit = n_we*byte_size + n_byte
+
+                _in_shiftreg.append(ckt.instantiate(ff_cell, name=f"dff_s[{n_bit}]"))
+                _in_capturereg.append(ckt.instantiate(ff_cell, name=f"dff_c[{n_bit}]"))
+        in_shiftreg = tuple(_in_shiftreg)
+        in_capturereg = tuple(_in_capturereg)
+        in_all = (*in_shiftreg, *in_capturereg)
+
+        # Register for capturing the outputs
+        _out_shiftreg: List[_ckt._CellInstance] = []
+        _out_capturereg: List[_ckt._CellInstance] = []
+        _out_muxes: List[_ckt._CellInstance] = []
+        for n_bit in range(word_size):
+            _out_shiftreg.append(ckt.instantiate(ff_cell, name=f"qff_s[{n_bit}]"))
+            _out_capturereg.append(ckt.instantiate(ff_cell, name=f"qff_c[{n_bit}]"))
+            _out_muxes.append(ckt.instantiate(mux_cell, name=f"qmux[{n_bit}]"))
+        out_shiftreg = tuple(_out_shiftreg)
+        out_capturereg = tuple(_out_capturereg)
+        out_muxes = tuple(_out_muxes)
+        out_all = (*out_shiftreg, *out_capturereg, *out_muxes)
+
+        in_captclkff = ckt.instantiate(ff_cell, name="incaptclkff")
+        out_captclkff = ckt.instantiate(ff_cell, name="outcaptclkff")
+
+        sram = ckt.instantiate(spcell, name="sram")
+
+        ckt.new_net(name="dvss", external=True, childports=(
+            inst.ports.vss for inst in (*in_all, *out_all, in_captclkff, out_captclkff)
+        ))
+        ckt.new_net(name="dvdd", external=True, childports=(
+            inst.ports.vdd for inst in (*in_all, *out_all, in_captclkff, out_captclkff)
+        ))
+        ckt.new_net(name="svss", external=True, childports=sram.ports.vss)
+        ckt.new_net(name="svdd", external=True, childports=sram.ports.vdd)
+
+        ckt.new_net(name="shift_in", external=True, childports=in_all[0].ports.i)
+        ckt.new_net(name="shift_out", external=True, childports=out_shiftreg[-1].ports.q)
+
+        ckt.new_net(name="sramclk", external=True, childports=(
+            sram.ports.clk, in_captclkff.ports.ck, out_captclkff.ports.ck,
+        ))
+
+        ckt.new_net(name="in_shiftclk", external=True, childports=(
+            ff.ports.ck for ff in in_shiftreg
+        ))
+        ckt.new_net(name="in_captureclk", external=True, childports=(
+            *(ff.ports.ck for ff in in_capturereg), in_captclkff.ports.i,
+        ))
+        ckt.new_net(name="in_captureclk_l", external=True, childports=(
+            in_captclkff.ports.q
+        ))
+
+        ckt.new_net(name="out_shiftclk", external=True, childports=(
+            ff.ports.ck for ff in out_shiftreg
+        ))
+        ckt.new_net(name="out_captureclk", external=True, childports=(
+            *(ff.ports.ck for ff in out_capturereg), out_captclkff.ports.i,
+        ))
+        ckt.new_net(name="out_captureclk_l", external=True, childports=(
+            out_captclkff.ports.q
+        ))
+        ckt.new_net(name="out_docapture", external=True, childports=(
+            mux.ports.cmd for mux in out_muxes
+        ))
+
+        # Connect the input shift registers
+        # Output of flop in shift reg is connected to input of corresponding flop in
+        # the capture reg and to the input of next flop in shift reg. Last flop
+        # connected to the input
+        # Output of flop in capture reg is connected to corresponding sram input pin
+        n = 0
+        for n_a in range(a_bits):
+            ckt.new_net(name=f"a_s[{n_a}]", external=False, childports=(
+                in_shiftreg[n].ports.q, in_capturereg[n].ports.i,
+                in_shiftreg[n + 1].ports.i
+            ))
+            ckt.new_net(name=f"a_c[{n_a}]", external=False, childports=(
+                in_capturereg[n].ports.q, sram.ports[f"a[{n_a}]"],
+            ))
+            n += 1
+        for n_we in range(we_size):
+            ckt.new_net(name=f"we_s[{n_we}]", external=False, childports=(
+                in_shiftreg[n].ports.q, in_capturereg[n].ports.i,
+                in_shiftreg[n + 1].ports.i
+            ))
+            ckt.new_net(name=f"we_c[{n_we}]", external=False, childports=(
+                in_capturereg[n].ports.q, sram.ports[f"we[{n_we}]"],
+            ))
+            n += 1
+
+            for n_byte in range(byte_size):
+                n_bit = n_we*byte_size + n_byte
+                nextgatepin = (
+                    in_shiftreg[n + 1].ports.i
+                    if n < (len(in_shiftreg) - 1)
+                    else out_muxes[0].ports.i1
+                )
+                ckt.new_net(name=f"d_s[{n_bit}]", external=False, childports=(
+                    in_shiftreg[n].ports.q, in_capturereg[n].ports.i,
+                    nextgatepin,
+                ))
+                ckt.new_net(name=f"d_c[{n_bit}]", external=False, childports=(
+                    in_capturereg[n].ports.q, sram.ports[f"d[{n_bit}]"],
+                ))
+                n += 1
+
+        # Connect the output shift registers
+        # The output of the sram is connected to the input of the corresponding flop
+        # in the capture reg. The output of the flop in the capture reg is connect
+        # to input i0 of the corresponding mux and the output of the previous flop in
+        # shift reg is connect to i1 of the mux.
+        for n_bit in range(word_size):
+            ckt.new_net(name=f"q_c[{n_bit}]", external=False, childports=(
+                sram.ports[f"q[{n_bit}]"], out_capturereg[n_bit].ports.i,
+            ))
+            ckt.new_net(name=f"q_cl[{n_bit}]", external=False, childports=(
+                out_capturereg[n_bit].ports.q, out_muxes[n_bit].ports.i0,
+            ))
+            if n_bit < (word_size - 1):
+                ckt.new_net(name=f"q_s[{n_bit}]", external=False, childports=(
+                    out_shiftreg[n_bit].ports.q, out_muxes[n_bit + 1].ports.i1,
+                ))
+            ckt.new_net(name=f"q_mux[{n_bit}]", external=False, childports=(
+                out_muxes[n_bit].ports.q, out_shiftreg[n_bit].ports.i,
+            ))
+
+    def _create_layout(self):
+        tech = self.tech
+        prims = tech.primitives
+
+        ckt = self.circuit
+        nets = ckt.nets
+        insts = ckt.instances
+
+        nwm = cast(_prm.Well, prims.nwm)
+        li = cast(_prm.MetalWire, prims.li)
+        assert li.pin is not None
+        lipin = li.pin[0]
+        mcon = cast(_prm.Via, prims.mcon)
+        m1 = cast(_prm.MetalWire, prims.m1)
+        assert m1.pin is not None
+        m1pin = m1.pin[0]
+        via = cast(_prm.Via, prims.via)
+        m2 = cast(_prm.MetalWire, prims.m2)
+        assert m2.pin is not None
+        m2pin = m2.pin[0]
+        via2 = cast(_prm.Via, prims.via2)
+        m3 = cast(_prm.MetalWire, prims.m3)
+        assert m3.pin is not None
+        m3pin = m3.pin[0]
+
+        # Place the SRAM block
+        layouter = self.new_circuitlayouter()
+
+        sram_lay = layouter.place(insts.sram, origin=_geo.origin)
+        sram_bb = sram_lay.boundary
+        assert sram_bb is not None
+
+        sramclk_m2pinbb = sram_lay.bounds(mask=m2pin.mask, net=nets.sramclk, depth=1)
+
+        # Place and connect a flipflops
+        x_s = y_s0 = None
+        x_c = y_c0 = None
+        dy = None
+        net_s_prev = None
+        mconnets_m1bb1_prev = None
+        mconacclk_m1bb_last = None
+        mconasclk_m1bb_last = None
+        affcvss_lipinbb_last = None
+        affcvdd_lipinbb_last = None
+        affsvss_lipinbb_last = None
+        affsvdd_lipinbb_last = None
+        for n_a in range(self.a_bits):
+            net_s = nets[f"a_s[{n_a}]"]
+            net_c = nets[f"a_c[{n_a}]"]
+            _affs_lay = layouter.inst_layout(
+                inst=insts[f"aff_s[{n_a}]"], rotation=_geo.Rotation.MX90,
+            )
+            _affc_lay = layouter.inst_layout(
+                inst=insts[f"aff_c[{n_a}]"], rotation=_geo.Rotation.R90,
+            )
+            sramnetc_m1pinbb = sram_lay.bounds(mask=m1pin.mask, net=net_c, depth=1)
+            if n_a == 0:
+                _affs_bb = _affs_lay.boundary
+                assert _affs_bb is not None
+                _affc_bb = _affc_lay.boundary
+                assert _affc_bb is not None
+
+                # Compute placement based on first flops
+                x_c = -3.0 - _affc_bb.right
+                y_c0 = sramnetc_m1pinbb.bottom - _affc_bb.top
+                x_s = x_c + _affc_bb.left - _affs_bb.right
+                y_s0 = sramnetc_m1pinbb.bottom - _affs_bb.top
+
+                dy = _affs_bb.height
+            assert x_s is not None
+            assert y_s0 is not None
+            assert x_c is not None
+            assert y_c0 is not None
+            assert dy is not None
+
+            # Place flops for a part of registers
+            y_s = y_s0 + n_a*dy
+            y_c = y_c0 + n_a*dy
+            affs_lay = layouter.place(_affs_lay, x=x_s, y=y_s)
+            affsnets_lipinbb = affs_lay.bounds(mask=lipin.mask, net=net_s)
+            affssclk_lipinbb = affs_lay.bounds(mask=lipin.mask, net=nets.in_shiftclk)
+            affsvss_lipinbb_last = affs_lay.bounds(mask=lipin.mask, net=nets.dvss)
+            affsvdd_lipinbb_last = affs_lay.bounds(mask=lipin.mask, net=nets.dvdd)
+            affc_lay = layouter.place(_affc_lay, x=x_c, y=y_c)
+            affcnets_lipinbb = affc_lay.bounds(mask=lipin.mask, net=net_s)
+            affcnetc_lipinbb = affc_lay.bounds(mask=lipin.mask, net=net_c)
+            affccclk_lipinbb = affc_lay.bounds(mask=lipin.mask, net=nets.in_captureclk)
+            affcvss_lipinbb_last = affc_lay.bounds(mask=lipin.mask, net=nets.dvss)
+            affcvdd_lipinbb_last = affc_lay.bounds(mask=lipin.mask, net=nets.dvdd)
+
+            # in_shiftclk
+            mconsclk_lay = layouter.add_wire(
+                net=nets.in_shiftclk, wire=mcon, columns=2,
+                origin=affssclk_lipinbb.center,
+            )
+            mconasclk_m1bb_last = mconsclk_lay.bounds(mask=m1.mask)
+
+            # in_captureclk
+            mconcclk_lay = layouter.add_wire(
+                net=nets.in_captureclk, wire=mcon, columns=2,
+                origin=affccclk_lipinbb.center,
+            )
+            mconacclk_m1bb_last = mconcclk_lay.bounds(mask=m1.mask)
+
+            # net_s
+            _mconnets_lay = layouter.wire_layout(
+                net=net_s, wire=mcon, columns=2,
+                bottom_enclosure="wide", top_enclosure="tall",
+            )
+            _mconnets_libb = _mconnets_lay.bounds(mask=li.mask)
+
+            x = affsnets_lipinbb.right - _mconnets_libb.right
+            y = affsnets_lipinbb.center.y
+            mconnets_lay1 = layouter.place(_mconnets_lay, x=x, y=y)
+            mconnets_m1bb1 = mconnets_lay1.bounds(mask=m1.mask)
+            x = affcnets_lipinbb.left - _mconnets_libb.left
+            y = affcnets_lipinbb.center.y
+            mconnets_lay2 = layouter.place(_mconnets_lay, x=x, y=y)
+            mconnets_m1bb2 = mconnets_lay2.bounds(mask=m1.mask)
+
+            shape = _geo.Rect.from_rect(rect=mconnets_m1bb2, top=mconnets_m1bb1.top)
+            layouter.add_wire(net=net_s, wire=m1, shape=shape)
+            shape = _geo.Rect.from_rect(rect=mconnets_m1bb1, right=mconnets_m1bb2.right)
+            layouter.add_wire(net=net_s, wire=m1, shape=shape)
+
+            _mconnetc_lay = layouter.wire_layout(
+                net=net_c, wire=mcon, columns=2,
+                bottom_enclosure="wide", top_enclosure="tall",
+            )
+            _mconnetc_libb = _mconnetc_lay.bounds(mask=li.mask)
+
+            x = affcnetc_lipinbb.right - _mconnetc_libb.right
+            y = affcnetc_lipinbb.center.y
+            mconnetc_lay = layouter.place(_mconnetc_lay, x=x, y=y)
+            mconnetc_m1bb = mconnetc_lay.bounds(mask=m1.mask)
+
+            shape = _geo.Rect.from_rect(rect=sramnetc_m1pinbb, left = mconnetc_m1bb.left)
+            layouter.add_wire(net=net_c, wire=m1, shape=shape)
+            if sramnetc_m1pinbb.top > mconnetc_m1bb.top:
+                shape = _geo.Rect.from_rect(rect=mconnetc_m1bb, top=sramnetc_m1pinbb.top)
+            else:
+                assert sramnetc_m1pinbb.bottom < mconnetc_m1bb.bottom
+                shape = _geo.Rect.from_rect(
+                    rect=mconnetc_m1bb, bottom=sramnetc_m1pinbb.bottom,
+                )
+            layouter.add_wire(net=net_c, wire=m1, shape=shape)
+
+            # net_s_prev
+            if net_s_prev is not None:
+                affsnetsp_lipinbb = affs_lay.bounds(mask=lipin.mask, net=net_s_prev)
+
+                assert mconnets_m1bb1_prev is not None
+                _mconnetsp_lay = layouter.wire_layout(
+                    net=net_s_prev, wire=mcon, columns=2,
+                    bottom_enclosure="wide", top_enclosure="tall",
+                )
+                _mconnetsp_libb = _mconnets_lay.bounds(mask=li.mask)
+
+                x = affsnetsp_lipinbb.right - _mconnetsp_libb.right
+                y = affsnetsp_lipinbb.center.y
+                mconnetsp_lay = layouter.place(_mconnetsp_lay, x=x, y=y)
+                mconnetsp_m1bb = mconnetsp_lay.bounds(mask=m1.mask)
+
+                shape = _geo.Rect.from_rect(
+                    rect=mconnets_m1bb1_prev, top=mconnetsp_m1bb.top,
+                )
+                layouter.add_wire(net=net_s_prev, wire=m1, shape=shape)
+            else:
+                assert n_a == 0
+                net = nets.shift_in
+                affssin_lipinbb = affs_lay.bounds(mask=lipin.mask, net=net)
+                _mconsin_lay = layouter.wire_layout(
+                    net=net, wire=mcon, columns=2,
+                    bottom_enclosure="wide", top_enclosure="tall",
+                )
+                _mconsin_libb = _mconsin_lay.bounds(mask=li.mask)
+
+                x = affssin_lipinbb.left - _mconsin_libb.left
+                y = affssin_lipinbb.center.y
+                mconsin_lay = layouter.place(_mconsin_lay, x=x, y=y)
+                mconsin_m1bb = mconsin_lay.bounds(mask=m1.mask)
+
+                layouter.add_wire(net=net, wire=m1, pin=m1pin, shape=mconsin_m1bb)
+
+            net_s_prev = net_s
+            mconnets_m1bb1_prev = mconnets_m1bb1
+        assert x_s is not None
+        assert y_s0 is not None
+        assert x_c is not None
+        assert y_c0 is not None
+        assert dy is not None
+        assert mconacclk_m1bb_last is not None
+        assert mconasclk_m1bb_last is not None
+        assert affcvss_lipinbb_last is not None
+        assert affcvdd_lipinbb_last is not None
+        assert affsvss_lipinbb_last is not None
+        assert affsvdd_lipinbb_last is not None
+
+        # Place in_captureclk capture flop + connect
+        x = x_c
+        y = y_c0 - dy
+        cclkff_lay = layouter.place(
+            insts.incaptclkff, x=x, y=y, rotation=_geo.Rotation.R90,
+        )
+        cclkffclk_lipinbb = cclkff_lay.bounds(mask=lipin.mask, net=nets.sramclk)
+        cclkffcclk_lipinbb = cclkff_lay.bounds(mask=lipin.mask, net=nets.in_captureclk)
+        cclkffcclkl_lipinbb = cclkff_lay.bounds(mask=lipin.mask, net=nets.in_captureclk_l)
+
+        x = mconacclk_m1bb_last.center.x
+        y = cclkffcclk_lipinbb.center.y
+        layouter.add_wire(
+            net=nets.in_captureclk, wire=mcon, x=x, y=y, columns=2,
+            bottom_enclosure="wide", top_enclosure="tall",
+        )
+
+        # Connect svss
+        net = nets.svss
+
+        bbs = tuple(ms.shape.bounds for ms in sram_lay.filter_polygons(
+            net=net, mask=m2pin.mask, depth=1, split=True,
+        ))
+        left = max(bb.left for bb in bbs)
+        top = max(bb.top for bb in bbs)
+        bottom = min(bb.bottom for bb in bbs)
+        w = 10.0
+        x_via2 = left + w/2.0
+        right = left + w
+
+        for bb in bbs:
+            y_via2 = bb.center.y
+            layouter.add_wire(
+                net=net, wire=via2, x=x_via2, y=y_via2,
+                bottom_width=w, bottom_enclosure="wide",
+                top_width=w, top_enclosure="wide",
+            )
+
+        shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=shape)
+
+        # Connect svdd
+        net = nets.svdd
+
+        bbs = tuple(ms.shape.bounds for ms in sram_lay.filter_polygons(
+            net=net, mask=m2pin.mask, depth=1, split=True,
+        ))
+        right = min(bb.right for bb in bbs)
+        top = max(bb.top for bb in bbs)
+        bottom = min(bb.bottom for bb in bbs)
+        w = 10.0
+        x_via2 = right - w/2.0
+        left = right - w
+
+        for bb in bbs:
+            y_via2 = bb.center.y
+            layouter.add_wire(
+                net=net, wire=via2, x=x_via2, y=y_via2,
+                bottom_width=w, bottom_enclosure="wide",
+                top_width=w, top_enclosure="wide",
+            )
+
+        shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=shape)
+
+        # Connect sramclk
+        net = nets.sramclk
+
+        _mconclkcclkff_lay = layouter.wire_layout(
+            net=net, wire=mcon, columns=2,
+            bottom_enclosure="wide", top_enclosure="tall",
+        )
+        _mconclkcclkff_libb = _mconclkcclkff_lay.bounds(mask=li.mask)
+
+        x = cclkffclk_lipinbb.right - _mconclkcclkff_libb.right
+        y = cclkffclk_lipinbb.center.y
+        layouter.place(_mconclkcclkff_lay, x=x, y=y)
+        viaclkcclkff_lay = layouter.add_wire(
+            net=net, wire=via, columns=2, x=x, y=y,
+            bottom_enclosure="tall", top_enclosure="tall",
+        )
+        viaclkcclkff_m2bb = viaclkcclkff_lay.bounds(mask=m2.mask)
+
+        shape = _geo.Rect.from_rect(
+            rect=viaclkcclkff_m2bb, right=sramclk_m2pinbb.right,
+        )
+        layouter.add_wire(net=net, wire=m2, shape=shape)
+        shape = _geo.Rect.from_rect(
+            rect=sramclk_m2pinbb, top=viaclkcclkff_m2bb.top,
+        )
+        layouter.add_wire(net=net, wire=m2, pin=m2pin, shape=shape)
+
+        # Connect in_captureclk_l        
+        _mconcclklcclkff_lay = layouter.wire_layout(
+            net=nets.in_captureclk_l, wire=mcon, columns=2,
+            bottom_enclosure="wide", top_enclosure="tall",
+        )
+        _mconcclklcclkff_libb = _mconcclklcclkff_lay.bounds(mask=li.mask)
+
+        x = cclkffcclkl_lipinbb.left - _mconcclklcclkff_libb.left
+        y = cclkffcclkl_lipinbb.center.y
+        mconcclklcclkff_lay = layouter.place(_mconcclklcclkff_lay, x=x, y=y)
+        mconcclklcclkff_m1bb = mconcclklcclkff_lay.bounds(mask=m1.mask)
+        
+        layouter.add_wire(
+            net=nets.in_captureclk_l, wire=m1, pin=m1pin, shape=mconcclklcclkff_m1bb,
+        )
+
+        # Compute horizontal displacement of the standard cells
+        assert self.byte_size > 2
+        m2pinbb1 = sram_lay.bounds(mask=m2pin.mask, net=nets["d_c[0]"], depth=1)
+        m2pinbb2 = sram_lay.bounds(mask=m2pin.mask, net=nets["d_c[2]"], depth=1)
+        dx_stdcell = m2pinbb2.center.x - m2pinbb1.center.x
+
+        # Place and connect we, d, q flipflops
+        insreg_m1bb_prev = None
+        insreg_net_prev = None
+        outsreg_m1bb_prev = None
+        outsreg_net_prev = None
+        outsreg_m1bb_first = None
+        outsreg_net_first = None
+        mconwecclk_m1bb_last = None
+        mconwesclk_m1bb_last = None
+        mcondcclk_m1bb1_last = None
+        mcondcclk_m1bb2_last = None
+        mcondsclk_m1bb1_last = None
+        mcondsclk_m1bb2_last = None
+        mconqcclk_m1bb1_last = None
+        mconqcclk_m1bb2_last = None
+        mconqsclk_m1bb1_last = None
+        mconqsclk_m1bb2_last = None
+        mcondoc_m1bb_first = None
+        mcondoc_m1bb_last = None
+        for n_we in range(self.we_size):
+            # Place we flops
+            we_s = nets[f"we_s[{n_we}]"]
+            we_c = nets[f"we_c[{n_we}]"]
+            sramwe_m2pinbb = sram_lay.bounds(mask=m2pin.mask, net=we_c, depth=1)
+
+            _weffc_lay = layouter.inst_layout(inst=insts[f"weff_c[{n_we}]"])
+            _weffc_bb = _weffc_lay.boundary
+            assert _weffc_bb is not None
+            _weffs_lay = layouter.inst_layout(
+                inst=insts[f"weff_s[{n_we}]"], rotation=_geo.Rotation.MX,
+            )
+            _weffs_bb = _weffs_lay.boundary
+            assert _weffs_bb is not None
+
+            stdcell_left = sramwe_m2pinbb.left - 5.0
+            x = stdcell_left - _weffc_bb.left
+            y = -5.0 - _weffc_bb.top
+            weffc_lay = layouter.place(_weffc_lay, x=x, y=y)
+            weffc_bb = weffc_lay.boundary
+            assert weffc_bb is not None
+            weffcclk_lipinbb = weffc_lay.bounds(mask=lipin.mask, net=nets.in_captureclk)
+            weffcwes_lipinbb = weffc_lay.bounds(mask=lipin.mask, net=we_s)
+            weffcwec_lipinbb = weffc_lay.bounds(mask=lipin.mask, net=we_c)
+
+            x = stdcell_left - _weffs_bb.left
+            y = weffc_bb.bottom - _weffs_bb.top
+            weffs_lay = layouter.place(_weffs_lay, x=x, y=y)
+            weffs_bb = weffs_lay.boundary
+            assert weffs_bb is not None
+            weffsclk_lipinbb = weffs_lay.bounds(mask=lipin.mask, net=nets.in_shiftclk)
+            weffswes_lipinbb = weffs_lay.bounds(mask=lipin.mask, net=we_s)
+
+            # Connect we captureclk
+            net = nets.in_captureclk
+
+            o = weffcclk_lipinbb.center
+            mconwecclk_lay = layouter.add_wire(
+                net=net, wire=mcon, rows=2, origin=o,
+                bottom_enclosure="tall", top_enclosure="wide",
+            )
+            mconwecclk_m1bb = mconwecclk_lay.bounds(mask=m1.mask)
+            mconwecclk_m1bb_last = mconwecclk_m1bb
+
+            # Connect we shifteclk
+            net = nets.in_shiftclk
+
+            o = weffsclk_lipinbb.center
+            mconwesclk_lay = layouter.add_wire(
+                net=net, wire=mcon, rows=2, origin=o,
+                bottom_enclosure="tall", top_enclosure="wide",
+            )
+            mconwesclk_m1bb = mconwesclk_lay.bounds(mask=m1.mask)
+            mconwesclk_m1bb_last = mconwesclk_m1bb
+
+            # Connect we_c
+            _mconwec_lay = layouter.wire_layout(
+                net=we_c, wire=mcon, rows=2,
+                bottom_enclosure="tall", top_enclosure="wide",
+            )
+            _mconwec_libb = _mconwec_lay.bounds(mask=li.mask)
+
+            x = weffcwec_lipinbb.center.x
+            y = weffcwec_lipinbb.top - _mconwec_libb.top
+            mconwec_lay = layouter.place(_mconwec_lay, x=x, y=y)
+            mconwec_m1bb = mconwec_lay.bounds(mask=m1.mask)
+            x = sramwe_m2pinbb.center.x
+            viawec_lay = layouter.add_wire(net=we_c, wire=via, rows=2, x=x, y=y)
+            viawec_m1bb = viawec_lay.bounds(mask=m1.mask)
+            viawec_m2bb = viawec_lay.bounds(mask=m2.mask)
+
+            shape = _geo.Rect.from_rect(rect=sramwe_m2pinbb, bottom=viawec_m2bb.bottom)
+            layouter.add_wire(net=we_c, wire=m2, shape=shape)
+            shape = _geo.Rect.from_rect(rect=mconwec_m1bb, left=viawec_m1bb.left)
+            layouter.add_wire(net=we_c, wire=m1, shape=shape)
+
+            # Connect we_s
+            _mconwes_lay = layouter.wire_layout(
+                net=we_s, wire=mcon, rows=2,
+                bottom_enclosure="tall", top_enclosure="wide",
+            )
+            _mconwes_libb = _mconwes_lay.bounds(mask=li.mask)
+
+            x = weffswes_lipinbb.center.x
+            y = weffswes_lipinbb.top - _mconwes_libb.top
+            mconwes_lay1 = layouter.place(_mconwes_lay, x=x, y=y)
+            mconwes_m1bb1 = mconwes_lay1.bounds(mask=m1.mask)
+
+            x = weffcwes_lipinbb.center.x
+            y = weffcwes_lipinbb.bottom - _mconwes_libb.bottom
+            mconwes_lay2 = layouter.place(_mconwes_lay, x=x, y=y)
+            mconwes_m1bb2 = mconwes_lay2.bounds(mask=m1.mask)
+            insreg_m1bb_prev = mconwes_m1bb2
+            insreg_net_prev = we_s
+
+            shape = _geo.Rect.from_rect(rect=mconwes_m1bb2, bottom=mconwes_m1bb1.bottom)
+            layouter.add_wire(net=we_s, wire=m1, shape=shape)
+            shape = _geo.Rect.from_rect(rect=mconwes_m1bb1, left=mconwes_m1bb2.left)
+            layouter.add_wire(net=we_s, wire=m1, shape=shape)
+            
+            # Place d flops, q flops and muxes
+            y_d = None
+            for n_byte in range(self.byte_size):
+                n_bit = n_we*self.byte_size + n_byte
+                d_s = nets[f"d_s[{n_bit}]"]
+                d_c = nets[f"d_c[{n_bit}]"]
+                sramd_m2pinbb = sram_lay.bounds(mask=m2pin.mask, net=d_c, depth=1)
+                q_c = nets[f"q_c[{n_bit}]"]
+                q_cl = nets[f"q_cl[{n_bit}]"]
+                q_mux = nets[f"q_mux[{n_bit}]"]
+                if n_bit < (self.word_size - 1):
+                    q_s = nets[f"q_s[{n_bit}]"]
+                else:
+                    q_s = nets.shift_out
+                sramq_m2pinbb = sram_lay.bounds(mask=m2pin.mask, net=q_c, depth=1)
+
+                mux_below = (n_byte%2) == 0
+
+                # Place the d flops, put two underneath each other
+                _dffc_lay = layouter.inst_layout(inst=insts[f"dff_c[{n_bit}]"])
+                _dffc_bb = _dffc_lay.boundary
+                assert _dffc_bb is not None
+                _dffs_lay = layouter.inst_layout(
+                    inst=insts[f"dff_s[{n_bit}]"], rotation=_geo.Rotation.MX,
+                )
+                _dffs_bb = _dffs_lay.boundary
+                assert _dffs_bb is not None
+
+                # Increase stdcell_left if n_byte is even but not 0;
+                # for zero we use the stdcell_left determined by the we flops
+                if mux_below and (n_byte != 0):
+                    stdcell_left += dx_stdcell
+
+                if mux_below:
+                    y_d = weffs_bb.bottom - _dffc_bb.top
+                else:
+                    assert y_d is not None
+                    y_d -= _dffc_bb.height + _dffs_bb.height
+
+                x = stdcell_left - _dffc_bb.left
+                y = y_d
+                dffc_lay = layouter.place(_dffc_lay, x=x, y=y)
+                dffc_bb = dffc_lay.boundary
+                assert dffc_bb is not None
+                dffcclk_lipinbb = dffc_lay.bounds(mask=lipin.mask, net=nets.in_captureclk)
+                dffcdc_lipinbb = dffc_lay.bounds(mask=lipin.mask, net=d_c)
+                dffcds_lipinbb = dffc_lay.bounds(mask=lipin.mask, net=d_s)
+                y = dffc_bb.bottom - _dffs_bb.top
+                dffs_lay = layouter.place(_dffs_lay, x=x, y=y)
+                dffsclk_lipinbb = dffs_lay.bounds(mask=lipin.mask, net=nets.in_shiftclk)
+                dffsds_lipinbb = dffs_lay.bounds(mask=lipin.mask, net=d_s)
+
+                # Connect d captureclk
+                net = nets.in_captureclk
+
+                o = dffcclk_lipinbb.center
+                mcondcclk_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=2, origin=o,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                mcondcclk_m1bb = mcondcclk_lay.bounds(mask=m1.mask)
+                if mux_below:
+                    mcondcclk_m1bb1_last = mcondcclk_m1bb
+                else:
+                    mcondcclk_m1bb2_last = mcondcclk_m1bb
+
+                # Connect d shifteclk
+                net = nets.in_shiftclk
+
+                o = dffsclk_lipinbb.center
+                mcondsclk_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=2, origin=o,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                mcondsclk_m1bb = mcondsclk_lay.bounds(mask=m1.mask)
+                if mux_below:
+                    mcondsclk_m1bb1_last = mcondsclk_m1bb
+                else:
+                    mcondsclk_m1bb2_last = mcondsclk_m1bb
+
+                # Connect d_c
+                _mcondc_lay = layouter.wire_layout(
+                    net=d_c, wire=mcon, rows=2,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                _mcondc_libb = _mcondc_lay.bounds(mask=li.mask)
+
+                x = dffcdc_lipinbb.center.x
+                y = dffcdc_lipinbb.top - _mcondc_libb.top
+                mcondc_lay = layouter.place(_mcondc_lay, x=x, y=y)
+                mcondc_m1bb = mcondc_lay.bounds(mask=m1.mask)
+                x = sramd_m2pinbb.center.x
+                viadc_lay = layouter.add_wire(net=d_c, wire=via, rows=2, x=x, y=y)
+                viadc_m1bb = viadc_lay.bounds(mask=m1.mask)
+                viadc_m2bb = viadc_lay.bounds(mask=m2.mask)
+
+                shape = _geo.Rect.from_rect(rect=sramd_m2pinbb, bottom=viadc_m2bb.bottom)
+                layouter.add_wire(net=d_c, wire=m2, shape=shape)
+                shape = _geo.Rect.from_rect(rect=mcondc_m1bb, left=viadc_m1bb.left)
+                layouter.add_wire(net=d_c, wire=m1, shape=shape)
+
+                # Connect d_s
+                _mconds_lay = layouter.wire_layout(
+                    net=d_s, wire=mcon, rows=2,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                _mconds_libb = _mconds_lay.bounds(mask=li.mask)
+
+                x = dffsds_lipinbb.center.x
+                y = dffsds_lipinbb.top - _mconds_libb.top
+                mconds_lay1 = layouter.place(_mconds_lay, x=x, y=y)
+                mconds_m1bb1 = mconds_lay1.bounds(mask=m1.mask)
+
+                x = dffcds_lipinbb.center.x
+                y = dffcds_lipinbb.bottom - _mconds_libb.bottom
+                mconds_lay2 = layouter.place(_mconds_lay, x=x, y=y)
+                mconds_m1bb2 = mconds_lay2.bounds(mask=m1.mask)
+                if (not mux_below) and (n_bit < (self.word_size - 1)):
+                    y = (
+                        dffcds_lipinbb.top - _mconds_libb.top
+                        - mconds_m1bb2.height - 2*m1.min_space
+                    )
+                    mconds_lay3 = layouter.place(_mconds_lay, x=x, y=y)
+                    mconds_m1bb3 = mconds_lay3.bounds(mask=m1.mask)
+
+                shape = _geo.Rect.from_rect(rect=mconds_m1bb2, bottom=mconds_m1bb1.bottom)
+                layouter.add_wire(net=d_s, wire=m1, shape=shape)
+                shape = _geo.Rect.from_rect(rect=mconds_m1bb1, left=mconds_m1bb2.left)
+                layouter.add_wire(net=d_s, wire=m1, shape=shape)
+
+                # Connect previous output of input shiftregister
+                assert insreg_m1bb_prev is not None
+                assert insreg_net_prev is not None
+                dffssregp_lipinbb = dffs_lay.bounds(mask=lipin.mask, net=insreg_net_prev)
+
+                _mconsregp_lay = layouter.wire_layout(
+                    net=insreg_net_prev, wire=mcon, rows=2,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                _mconsregp_libb = _mconsregp_lay.bounds(mask=li.mask)
+
+                x = dffssregp_lipinbb.center.x
+                y = dffssregp_lipinbb.bottom - _mconsregp_libb.bottom
+                mconsregp_lay = layouter.place(_mconsregp_lay, x=x, y=y)
+                mconsregp_m1bb = mconsregp_lay.bounds(mask=m1.mask)
+                if n_byte == 0:
+                    # Straight line for we_s
+                    viasregp_lay1 = layouter.add_wire(
+                        net=insreg_net_prev, wire=via, rows=2,
+                        origin=insreg_m1bb_prev.center,
+                    )
+                    viasregp_m2bb1 = viasregp_lay1.bounds(mask=m2.mask)
+
+                    viasregp_lay2 = layouter.add_wire(
+                        net=insreg_net_prev, wire=via, rows=2,
+                        origin=mconsregp_m1bb.center,
+                    )
+                    viasregp_m2bb2 = viasregp_lay2.bounds(mask=m2.mask)
+
+                    shape = _geo.Rect.from_rect(
+                        rect=viasregp_m2bb1, bottom=viasregp_m2bb2.bottom,
+                    )
+                    layouter.add_wire(net=insreg_net_prev, wire=m2, shape=shape)
+                elif not mux_below:
+                    # Horizontal m1, vertical m2
+                    viasregp_lay1 = layouter.add_wire(
+                        net=insreg_net_prev, wire=via, rows=2,
+                        origin=insreg_m1bb_prev.center,
+                    )
+                    viasregp_m2bb1 = viasregp_lay1.bounds(mask=m2.mask)
+
+                    x = insreg_m1bb_prev.center.x
+                    y = mconsregp_m1bb.center.y
+                    viasregp_lay2 = layouter.add_wire(
+                        net=insreg_net_prev, wire=via, rows=2, x=x, y=y,
+                    )
+                    viasregp_m1bb2 = viasregp_lay2.bounds(mask=m1.mask)
+                    viasregp_m2bb2 = viasregp_lay2.bounds(mask=m2.mask)
+
+                    shape = _geo.Rect.from_rect(
+                        rect=mconsregp_m1bb, right=viasregp_m1bb2.right,
+                    )
+                    layouter.add_wire(net=insreg_net_prev, wire=m1, shape=shape)
+                    shape = _geo.Rect.from_rect(
+                        rect=viasregp_m2bb1, bottom=viasregp_m2bb2.bottom,
+                    )
+                    layouter.add_wire(net=insreg_net_prev, wire=m2, shape=shape)
+                else: # mux_below and n_byte > 0
+                    # Connect from previous column with a polygon on m1
+                    left = stdcell_left
+                    right = left + insreg_m1bb_prev.height
+                    shape = _geo.Polygon.from_floats(points=(
+                        (insreg_m1bb_prev.left, insreg_m1bb_prev.bottom),
+                        (insreg_m1bb_prev.left, insreg_m1bb_prev.top),
+                        (left, insreg_m1bb_prev.top),
+                        (left, mconsregp_m1bb.top),
+                        (mconsregp_m1bb.right, mconsregp_m1bb.top),
+                        (mconsregp_m1bb.right, mconsregp_m1bb.bottom),
+                        (right, mconsregp_m1bb.bottom),
+                        (right, insreg_m1bb_prev.bottom),
+                        (insreg_m1bb_prev.left, insreg_m1bb_prev.bottom),
+                    ))
+                    layouter.add_wire(net=insreg_net_prev, wire=m1, shape=shape)
+                if mux_below or (n_bit == (self.word_size - 1)):
+                    insreg_m1bb_prev = mconds_m1bb1
+                else:
+                    insreg_m1bb_prev = mconds_m1bb3
+                insreg_net_prev = d_s
+
+                # Place the q flops, put two underneath each other
+                if mux_below:
+                    _qffc_lay = layouter.inst_layout(
+                        inst=insts[f"qff_c[{n_bit}]"],
+                    )
+                    _qffc_bb = _qffc_lay.boundary
+                    assert _qffc_bb is not None
+                    _qffs_lay = layouter.inst_layout(
+                        inst=insts[f"qff_s[{n_bit}]"], rotation=_geo.Rotation.MX,
+                    )
+                    _qffs_bb = _qffs_lay.boundary
+                    assert _qffs_bb is not None
+                    _qmux_lay = layouter.inst_layout(
+                        inst=insts[f"qmux[{n_bit}]"],
+                    )
+                    _qmux_bb = _qmux_lay.boundary
+                    assert _qmux_bb is not None
+
+                    y_q = y_d - 4*_qffc_bb.height
+                    x_mux = stdcell_left - _qmux_bb.left
+                    y_mux = y_q - 2*_qffc_bb.height
+                else:
+                    _qffc_lay = layouter.inst_layout(
+                        inst=insts[f"qff_c[{n_bit}]"], rotation=_geo.Rotation.MX,
+                    )
+                    _qffc_bb = _qffc_lay.boundary
+                    assert _qffc_bb is not None
+                    _qffs_lay = layouter.inst_layout(
+                        inst=insts[f"qff_s[{n_bit}]"],
+                    )
+                    _qffs_bb = _qffs_lay.boundary
+                    assert _qffs_bb is not None
+                    _qmux_lay = layouter.inst_layout(
+                        inst=insts[f"qmux[{n_bit}]"],
+                    )
+                    _qmux_bb = _qmux_lay.boundary
+                    assert _qmux_bb is not None
+
+                    x_mux = stdcell_left - _qmux_bb.left + _qmux_bb.width
+                    y_mux = y_d - 4*_qffc_bb.height
+                    y_q = y_mux
+
+                x = stdcell_left - _qffc_bb.left
+                y = y_q
+                qffc_lay = layouter.place(_qffc_lay, x=x, y=y)
+                qffc_bb = qffc_lay.boundary
+                assert qffc_bb is not None
+                qffcclk_lipinbb = qffc_lay.bounds(mask=lipin.mask, net=nets.out_captureclk)
+                qffcqc_lipinbb = qffc_lay.bounds(mask=lipin.mask, net=q_c)
+                qffcqcl_lipinbb = qffc_lay.bounds(mask=lipin.mask, net=q_cl)
+                y = qffc_bb.bottom - _qffs_bb.top
+                qffs_lay = layouter.place(_qffs_lay, x=x, y=y)
+                qffsclk_lipinbb = qffs_lay.bounds(mask=lipin.mask, net=nets.out_shiftclk)
+                qffsqs_lipinbb = qffs_lay.bounds(mask=lipin.mask, net=q_s)
+                qffsqmux_lipinbb = qffs_lay.bounds(mask=lipin.mask, net=q_mux)
+                qmux_lay = layouter.place(_qmux_lay, x=x_mux, y=y_mux)
+                qmuxqmux_lipinbb = qmux_lay.bounds(mask=lipin.mask, net=q_mux)
+                qmuxqcl_lipinbb = qmux_lay.bounds(mask=lipin.mask, net=q_cl)
+                qmuxdoc_lipinbb = qmux_lay.bounds(mask=lipin.mask, net=nets.out_docapture)
+
+                # Connect q captureclk
+                net = nets.out_captureclk
+
+                o = qffcclk_lipinbb.center
+                mconqcclk_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=2, origin=o,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                mconqcclk_m1bb = mconqcclk_lay.bounds(mask=m1.mask)
+                if mux_below:
+                    mconqcclk_m1bb1_last = mconqcclk_m1bb
+                else:
+                    mconqcclk_m1bb2_last = mconqcclk_m1bb
+
+                # Connect q shifteclk
+                net = nets.out_shiftclk
+
+                o = qffsclk_lipinbb.center
+                mconqsclk_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=2, origin=o,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                mconqsclk_m1bb = mconqsclk_lay.bounds(mask=m1.mask)
+                if mux_below:
+                    mconqsclk_m1bb1_last = mconqsclk_m1bb
+                else:
+                    mconqsclk_m1bb2_last = mconqsclk_m1bb
+
+                # Connect q_c
+                net = q_c
+
+                _mconqc_lay = layouter.wire_layout(
+                    net=net, wire=mcon, rows=2,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                _mconqc_libb = _mconqc_lay.bounds(mask=li.mask)
+
+                x = qffcqc_lipinbb.center.x
+                y = qffcqc_lipinbb.top - _mconqc_libb.top
+                mconqc_lay = layouter.place(_mconqc_lay, x=x, y=y)
+                mconqc_m1bb = mconqc_lay.bounds(mask=m1.mask)
+                x = sramq_m2pinbb.center.x
+                viaqc_lay = layouter.add_wire(net=net, wire=via, rows=2, x=x, y=y)
+                viaqc_m1bb = viaqc_lay.bounds(mask=m1.mask)
+                viaqc_m2bb = viaqc_lay.bounds(mask=m2.mask)
+
+                shape = _geo.Rect.from_rect(rect=sramq_m2pinbb, bottom=viaqc_m2bb.bottom)
+                layouter.add_wire(net=net, wire=m2, shape=shape)
+                if (mconqc_m1bb.left > viaqc_m1bb.left):
+                    shape = _geo.Rect.from_rect(rect=mconqc_m1bb, left=viaqc_m1bb.left)
+                else:
+                    shape = _geo.Rect.from_rect(rect=mconqc_m1bb, right=viaqc_m1bb.right)
+                layouter.add_wire(net=net, wire=m1, shape=shape)
+
+                # Connect q_cl
+                net = q_cl
+
+                _mconqcl_lay = layouter.wire_layout(
+                    net=net, wire=mcon, rows=2,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                _mconqcl_libb = _mconqcl_lay.bounds(mask=li.mask)
+
+                x = qffcqcl_lipinbb.center.x
+                if mux_below:
+                    y = qffcqcl_lipinbb.bottom - _mconqcl_libb.bottom
+                else:
+                    y = qffcqcl_lipinbb.top - _mconqcl_libb.top
+                mconqcl_lay = layouter.place(_mconqcl_lay, x=x, y=y)
+                mconqcl_m1bb = mconqcl_lay.bounds(mask=m1.mask)
+
+                x = qmuxqcl_lipinbb.center.x
+                viaqcl_lay1 = layouter.add_wire(
+                    net=net, wire=via, rows=2, x=x, y=y,
+                    bottom_enclosure="wide", top_enclosure="tall",
+                )
+                viaqcl_m1bb1 = viaqcl_lay1.bounds(mask=m1.mask)
+                viaqcl_m2bb1 = viaqcl_lay1.bounds(mask=m2.mask)
+
+                shape = _geo.Rect.from_rect(
+                    rect=mconqcl_m1bb, left = viaqcl_m1bb1.left,
+                )
+                layouter.add_wire(net=net, wire=m1, shape=shape)
+
+                x = qmuxqcl_lipinbb.center.x
+                if mux_below:
+                    y = qmuxqcl_lipinbb.top - _mconqcl_libb.top
+                else:
+                    y = qmuxqcl_lipinbb.bottom - _mconqcl_libb.bottom
+                    # Use second row, i0 has already higher bottom
+                    y += 2*m1.min_space
+                layouter.place(_mconqcl_lay, x=x, y=y)
+                viaqcl_lay2 = layouter.add_wire(
+                    net=net, wire=via, rows=2, x=x, y=y,
+                    bottom_enclosure="wide", top_enclosure="tall",
+                )
+                viaqcl_m2bb2 = viaqcl_lay2.bounds(mask=m2.mask)
+
+                if mux_below:
+                    shape = _geo.Rect.from_rect(
+                        rect=viaqcl_m2bb1, bottom=viaqcl_m2bb2.bottom,
+                    )
+                else:
+                    shape = _geo.Rect.from_rect(
+                        rect=viaqcl_m2bb1, top=viaqcl_m2bb2.top,
+                    )
+                layouter.add_wire(net=net, wire=m2, shape=shape)
+
+                # Connect q_s
+                _mconqs_lay = layouter.wire_layout(
+                    net=q_s, wire=mcon, rows=2,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                _mconqs_libb = _mconqs_lay.bounds(mask=li.mask)
+
+                x = qffsqs_lipinbb.center.x
+                if mux_below:
+                    y = qffsqs_lipinbb.bottom - _mconqs_libb.bottom
+                else:
+                    y = qffsqs_lipinbb.top - _mconqs_libb.top
+                mconqs_lay1 = layouter.place(_mconqs_lay, x=x, y=y)
+                mconqs_m1bb1 = mconqs_lay1.bounds(mask=m1.mask)
+
+                # Connect out_docapture
+                net = nets.out_docapture
+                o = self.tech.on_grid(qmuxdoc_lipinbb.center, mult=2)
+                mcondoc_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=2, origin=o,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                mcondoc_m1bb = mcondoc_lay.bounds(mask=m1.mask)
+
+                if n_bit == 0:
+                    mcondoc_m1bb_first = mcondoc_m1bb
+                mcondoc_m1bb_last = mcondc_m1bb
+
+                # Connect q_mux
+                _mconqmux_lay = layouter.wire_layout(
+                    net=q_mux, wire=mcon, rows=2,
+                    bottom_enclosure="tall", top_enclosure="wide",
+                )
+                _mconqmux_libb = _mconqmux_lay.bounds(mask=li.mask)
+
+                x = qffsqmux_lipinbb.center.x
+                if mux_below:
+                    y = qffsqmux_lipinbb.bottom - _mconqmux_libb.bottom
+                else:
+                    y = qffsqmux_lipinbb.top - _mconqmux_libb.top
+                mconqmux_lay1 = layouter.place(_mconqmux_lay, x=x, y=y)
+                mconqmux_m1bb1 = mconqmux_lay1.bounds(mask=m1.mask)
+
+                x = qmuxqmux_lipinbb.center.x
+                if mux_below:
+                    y = qmuxqmux_lipinbb.top - _mconqmux_libb.top
+                else:
+                    y = qmuxqmux_lipinbb.bottom - _mconqmux_libb.bottom
+                mconqmux_lay2 = layouter.place(_mconqmux_lay, x=x, y=y)
+                mconqmux_m1bb2 = mconqmux_lay2.bounds(mask=m1.mask)
+
+                assert mconqmux_m1bb1.left < mconqmux_m1bb2.left
+                if mux_below:
+                    # Connect on m1 with polygon
+                    shape = _geo.Polygon.from_floats(points=(
+                        (mconqmux_m1bb1.left, mconqmux_m1bb2.bottom),
+                        (mconqmux_m1bb1.left, mconqmux_m1bb1.top),
+                        (mconqmux_m1bb1.right, mconqmux_m1bb1.top),
+                        (mconqmux_m1bb1.right, mconqmux_m1bb2.top),
+                        (mconqmux_m1bb2.right, mconqmux_m1bb2.top),
+                        (mconqmux_m1bb2.right, mconqmux_m1bb2.bottom),
+                        (mconqmux_m1bb1.left, mconqmux_m1bb2.bottom),
+                    ))
+                    layouter.add_wire(net=q_mux, wire=m1, shape=shape)
+                else:
+                    # Horizontal m1, vertical m2
+                    shape = _geo.Rect.from_rect(
+                        rect=mconqmux_m1bb2, left=mconqmux_m1bb1.left,
+                    )
+                    layouter.add_wire(net=q_mux, wire=m1, shape=shape)
+
+                    x = mconqmux_m1bb1.center.x
+                    y = mconqmux_m1bb2.center.y
+                    viaqmux_lay1 = layouter.add_wire(
+                        net=q_mux, wire=via, rows=2, x=x, y=y,
+                        bottom_enclosure="tall", top_enclosure="tall",
+                    )
+                    viaqmux_m2bb1 = viaqmux_lay1.bounds(mask=m2.mask)
+
+                    o = mconqmux_m1bb1.center
+                    viaqmux_lay2 = layouter.add_wire(
+                        net=q_mux, wire=via, rows=2, origin=o,
+                        bottom_enclosure="tall", top_enclosure="tall",
+                    )
+                    viaqmux_m2bb2 = viaqmux_lay2.bounds(mask=m2.mask)
+
+                    shape = _geo.Rect.from_rect(
+                        rect=viaqmux_m2bb1, bottom=viaqmux_m2bb2.bottom,
+                    )
+                    layouter.add_wire(net=q_mux, wire=m2, shape=shape)
+
+                # Connect previous output of out shiftregister
+                if outsreg_m1bb_prev is None:
+                    assert outsreg_net_prev is None
+                    assert n_byte == 0 # Can only happen for first bit in byte
+                    outsreg_net_first = net = nets[f"d_s[{self.word_size - 1}]"]
+                    qmuxds_lipinbb = qmux_lay.bounds(mask=lipin.mask, net=net)
+
+                    _mconds_lay = layouter.wire_layout(
+                        net=net, wire=mcon, rows=2,
+                        bottom_enclosure="tall", top_enclosure="wide",
+                    )
+                    _mconds_libb = _mconds_lay.bounds(mask=li.mask)
+
+                    x = qmuxds_lipinbb.center.x
+                    y = (
+                        qmuxds_lipinbb.top - _mconds_libb.top
+                        - _mconds_libb.height - 2*m1.min_space
+                    )
+                    mconds_lay = layouter.place(_mconds_lay, x=x, y=y)
+                    outsreg_m1bb_first = mconds_lay.bounds(mask=m1.mask)
+                else:
+                    assert outsreg_net_prev is not None
+                    qmuxsregp_lipinbb = qmux_lay.bounds(
+                        mask=lipin.mask, net=outsreg_net_prev,
+                    )
+
+                    _mconsregp_lay = layouter.wire_layout(
+                        net=insreg_net_prev, wire=mcon, rows=2,
+                        bottom_enclosure="tall", top_enclosure="wide",
+                    )
+                    _mconsregp_libb = _mconsregp_lay.bounds(mask=li.mask)
+
+                    if mux_below:
+                        x = qmuxsregp_lipinbb.center.x
+                        y = (
+                            qmuxsregp_lipinbb.bottom - _mconsregp_libb.bottom
+                            + _mconsregp_libb.height + 2*m1.min_space
+                        )
+                        mconsregp_lay = layouter.place(_mconsregp_lay, x=x, y=y)
+                        mconsregp_m1bb = mconsregp_lay.bounds(mask=m1.mask)
+
+                        x = outsreg_m1bb_prev.center.x
+                        viasregp_lay1 = layouter.add_wire(
+                            net=outsreg_net_prev, wire=via, rows=2, x=x, y=y,
+                            bottom_enclosure="wide", top_enclosure="tall",
+                        )
+                        viasregp_m1bb1 = viasregp_lay1.bounds(mask=m1.mask)
+                        viasregp_m2bb1 = viasregp_lay1.bounds(mask=m2.mask)
+
+                        shape = _geo.Rect.from_rect(
+                            rect=mconsregp_m1bb, left=viasregp_m1bb1.left,
+                        )
+                        layouter.add_wire(
+                            net=outsreg_net_prev, wire=m1, shape=shape,
+                        )
+                        y = outsreg_m1bb_prev.center.y
+                        viasregp_lay2 = layouter.add_wire(
+                            net=outsreg_net_prev, wire=via, rows=2, x=x, y=y,
+                            bottom_enclosure="wide", top_enclosure="tall",
+                        )
+                        viasregp_m2bb2 = viasregp_lay2.bounds(mask=m2.mask)
+
+                        shape = _geo.Rect.from_rect(
+                            rect=viasregp_m2bb1, bottom=viasregp_m2bb2.bottom,
+                        )
+                        layouter.add_wire(net=outsreg_net_prev, wire=m2, shape=shape)
+                    else:
+                        x = qmuxsregp_lipinbb.center.x
+                        y = qmuxsregp_lipinbb.top - _mconsregp_libb.top
+                        mconsregp_lay = layouter.place(_mconsregp_lay, x=x, y=y)
+                        mconsregp_m1bb = mconsregp_lay.bounds(mask=m1.mask)
+
+                        shape = _geo.Polygon.from_floats(points=(
+                            (mconsregp_m1bb.left, mconsregp_m1bb.bottom),
+                            (mconsregp_m1bb.left, outsreg_m1bb_prev.top),
+                            (outsreg_m1bb_prev.right, outsreg_m1bb_prev.top),
+                            (outsreg_m1bb_prev.right, outsreg_m1bb_prev.bottom),
+                            (mconsregp_m1bb.right, outsreg_m1bb_prev.bottom),
+                            (mconsregp_m1bb.right, mconsregp_m1bb.bottom),
+                            (mconsregp_m1bb.left, mconsregp_m1bb.bottom),
+                        ))
+                        layouter.add_wire(net=outsreg_net_prev, wire=m1, shape=shape)
+                outsreg_m1bb_prev = mconqs_m1bb1
+                outsreg_net_prev = q_s
+
+                # Place the out captureclk flop if the first bit
+                if n_bit == 0:
+                    _cclkff_lay = layouter.inst_layout(inst=insts.outcaptclkff)
+                    _cclkff_bb = _cclkff_lay.boundary
+                    assert _cclkff_bb is not None
+
+                    x = qffc_bb.left - _cclkff_bb.right
+                    y = qffc_bb.bottom - _cclkff_bb.bottom
+                    cclkff_lay = layouter.place(_cclkff_lay, x=x, y=y)
+                    cclkffclk_lipinbb = cclkff_lay.bounds(
+                        mask=lipin.mask, net=nets.sramclk,
+                    )
+                    cclkffcclk_lipinbb = cclkff_lay.bounds(
+                        mask=lipin.mask, net=nets.out_captureclk,
+                    )
+                    cclkffcclkl_lipinbb = cclkff_lay.bounds(
+                        mask=lipin.mask, net=nets.out_captureclk_l,
+                    )
+
+                    # Connedt sramclk
+                    net = nets.sramclk
+
+                    _mconclk_lay = layouter.wire_layout(
+                        net=net, wire=mcon, rows=2,
+                        bottom_enclosure="tall", top_enclosure="wide",
+                    )
+                    _mconclk_libb = _mconclk_lay.bounds(mask=li.mask)
+
+                    x = cclkffclk_lipinbb.center.x
+                    y = cclkffclk_lipinbb.bottom - _mconclk_libb.bottom
+                    mconclk_lay = layouter.place(_mconclk_lay, x=x, y=y)
+                    mconclk_m1bb = mconclk_lay.bounds(mask=m1.mask)
+
+                    shape = _geo.Rect.from_rect(
+                        rect=mconclk_m1bb, left=sramclk_m2pinbb.left,
+                    )
+                    layouter.add_wire(net=net, wire=m1, shape=shape)
+
+                    x = sramclk_m2pinbb.center.x
+                    y = mconclk_m1bb.center.y
+                    viaclk_lay = layouter.add_wire(
+                        net=net, wire=via, x=x, y=y,
+                        top_width=sramclk_m2pinbb.width,
+                    )
+                    viaclk_m2bb = viaclk_lay.bounds(mask=m2.mask)
+
+                    shape = _geo.Rect.from_rect(
+                        rect=viaclk_m2bb, top=sramclk_m2pinbb.top
+                    )
+                    layouter.add_wire(net=net, wire=m2, pin=m2pin, shape=shape)
+
+                    # Connect out_captureclk
+                    net = nets.out_captureclk
+
+                    o = cclkffcclk_lipinbb.center
+                    layouter.add_wire(
+                        net=net, wire=mcon, rows=2, origin=o,
+                        bottom_enclosure="tall", top_enclosure="wide",
+                    )
+
+                    # Connect out_captureclk_l
+                    net = nets.out_captureclk_l
+
+                    _mconcclkl_lay = layouter.wire_layout(
+                        net=net, wire=mcon, rows=2,
+                        bottom_enclosure="tall", top_enclosure="wide",
+                    )
+                    _mconcclkl_libb = _mconcclkl_lay.bounds(mask=li.mask)
+
+                    x = cclkffcclkl_lipinbb.center.x
+                    y = cclkffcclkl_lipinbb.bottom - _mconcclkl_libb.bottom
+                    mconcclkl_lay = layouter.place(_mconcclkl_lay, x=x, y=y)
+                    mconcclkl_m1bb = mconcclkl_lay.bounds(mask=m1.mask)
+
+                    layouter.add_wire(net=net, wire=m1, pin=m1pin, shape=mconcclkl_m1bb)
+
+            # Connect output of in shift register to first of output shift register
+            assert insreg_m1bb_prev is not None
+            assert insreg_net_prev is not None
+            assert outsreg_m1bb_first is not None
+            assert outsreg_net_first is not None
+            assert insreg_net_prev == outsreg_net_first
+
+            left = insreg_m1bb_prev.right + 2*m1.min_space
+            right = left + insreg_m1bb_prev.height
+            shape = _geo.Polygon.from_floats(points=(
+                (outsreg_m1bb_first.left, outsreg_m1bb_first.bottom),
+                (outsreg_m1bb_first.left, outsreg_m1bb_first.top),
+                (left, outsreg_m1bb_first.top),
+                (left, insreg_m1bb_prev.bottom),
+                (insreg_m1bb_prev.left, insreg_m1bb_prev.bottom),
+                (insreg_m1bb_prev.left, insreg_m1bb_prev.top),
+                (right, insreg_m1bb_prev.top),
+                (right, outsreg_m1bb_first.bottom),
+                (outsreg_m1bb_first.left, outsreg_m1bb_first.bottom),
+            ))
+            layouter.add_wire(net=insreg_net_prev, wire=m1, shape=shape)
+        assert mconwecclk_m1bb_last is not None
+        assert mconwesclk_m1bb_last is not None
+        assert mcondcclk_m1bb1_last is not None
+        assert mcondcclk_m1bb2_last is not None
+        assert mcondsclk_m1bb1_last is not None
+        assert mcondsclk_m1bb2_last is not None
+        assert mconqcclk_m1bb1_last is not None
+        assert mconqcclk_m1bb2_last is not None
+        assert mconqsclk_m1bb1_last is not None
+        assert mconqsclk_m1bb2_last is not None
+
+        # Connect shift_out
+        assert outsreg_m1bb_prev is not None
+        assert outsreg_net_prev is not None
+        assert outsreg_net_prev == nets.shift_out
+        layouter.add_wire(
+            net=outsreg_net_prev, wire=m1, pin=m1pin, shape=outsreg_m1bb_prev,
+        )
+
+        # Conect in_captureclk
+        net = nets.in_captureclk
+
+        bottom = mconwecclk_m1bb_last.bottom
+        left = mconacclk_m1bb_last.left
+        shape = _geo.Rect.from_rect(rect=mconacclk_m1bb_last, bottom=bottom)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mconwecclk_m1bb_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mcondcclk_m1bb1_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mcondcclk_m1bb2_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+
+        x = mconacclk_m1bb_last.center.x
+        y = mconwecclk_m1bb_last.center.y
+        via_lay = layouter.add_wire(
+            net=net, wire=via, rows=2, columns=2, x=x, y=y,
+        )
+        via_m2bb1 = via_lay.bounds(mask=m2.mask)
+        y = mcondcclk_m1bb1_last.center.y
+        layouter.add_wire(
+            net=net, wire=via, rows=2, columns=2, x=x, y=y,
+        )
+        y = mcondcclk_m1bb2_last.center.y
+        via_lay = layouter.add_wire(
+            net=net, wire=via, rows=2, columns=2, x=x, y=y,
+        )
+        via_m2bb2 = via_lay.bounds(mask=m2.mask)
+
+        shape = _geo.Rect.from_rect(rect=via_m2bb1, bottom=via_m2bb2.bottom)
+        layouter.add_wire(net=net, wire=m2, pin=m2pin, shape=shape)
+
+        # Conect in_shiftclk
+        net = nets.in_shiftclk
+
+        bottom = mcondsclk_m1bb2_last.bottom
+        left = mconasclk_m1bb_last.left
+        shape = _geo.Rect.from_rect(rect=mconasclk_m1bb_last, bottom=bottom)
+        layouter.add_wire(net=net, wire=m1, pin=m1pin, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mconwesclk_m1bb_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mcondsclk_m1bb1_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mcondsclk_m1bb2_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+
+        # Conect out_captureclk
+        net = nets.out_captureclk
+
+        left = 5.0
+        shape = _geo.Rect.from_rect(rect=mconqcclk_m1bb1_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mconqcclk_m1bb2_last, left=left)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+
+        right = 6.0
+        shape = _geo.Rect(
+            left=left, bottom=mconqcclk_m1bb2_last.bottom,
+            right=right, top=mconqcclk_m1bb1_last.top,
+        )
+        layouter.add_wire(net=net, wire=m1, pin=m1pin, shape=shape)
+
+        # Conect out_shiftclk
+        net = nets.out_shiftclk
+
+        x = 27.0
+        shape = _geo.Rect.from_rect(rect=mconqsclk_m1bb1_last, left=x)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+        shape = _geo.Rect.from_rect(rect=mconqsclk_m1bb2_last, left=x)
+        layouter.add_wire(net=net, wire=m1, shape=shape)
+
+        y = mconqsclk_m1bb1_last.center.y
+        via_lay = layouter.add_wire(
+            net=net, wire=via, rows=2, columns=2, x=x, y=y,
+        )
+        via_m2bb1 = via_lay.bounds(mask=m2.mask)
+        y = mconqsclk_m1bb2_last.center.y
+        via_lay = layouter.add_wire(
+            net=net, wire=via, rows=2, columns=2, x=x, y=y,
+        )
+        via_m2bb2 = via_lay.bounds(mask=m2.mask)
+
+        shape = _geo.Rect.from_rect(rect=via_m2bb1, bottom=via_m2bb2.bottom)
+        layouter.add_wire(net=net, wire=m2, pin=m2pin, shape=shape)
+
+        # Connect out_docapture
+        net = nets.out_docapture
+
+        assert mcondoc_m1bb_first is not None
+        assert mcondoc_m1bb_last is not None
+        shape = _geo.Rect.from_rect(
+            rect=mcondoc_m1bb_first, right=mcondoc_m1bb_last.right,
+        )
+        layouter.add_wire(net=net, wire=m1, pin=m1pin, shape=shape)
+
+        # TODO: remove hard coded values
+        stdcell_height = 10.0
+        stdcellvss_height = 1.2
+        stdcellvdd_height = 1.2
+        stdcellnwelledge_height = 4.8
+
+        bottomblock_top = -5
+
+        # Connect dvss
+        net = nets.dvss
+
+        bottom = -115
+        shape = _geo.Rect.from_rect(rect=affsvss_lipinbb_last, bottom=bottom)
+        layouter.add_wire(net=net, wire=li, shape=shape)
+        shape = _geo.Rect.from_rect(rect=affcvss_lipinbb_last, bottom=bottom)
+        layouter.add_wire(net=net, wire=li, shape=shape)
+
+        left = affcvss_lipinbb_last.left
+        right = sram_bb.right
+        for i in range(6):
+            top = bottomblock_top - (2*i + 1)*stdcell_height + stdcellvss_height
+            if i < 5:
+                bottom = top - 2*stdcellvss_height
+            else:
+                bottom = top - stdcellvss_height
+            shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+            layouter.add_wire(net=net, wire=li, shape=shape)
+
+            # Connect with first column
+            if i == 4:
+                x = affcvss_lipinbb_last.left
+                y = 0.5*(bottom + top)
+                mcon_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=7, columns=7, x=x, y=y
+                )
+                mcon_m1bb1 = mcon_lay.bounds(mask=m1.mask)
+                x = affsvss_lipinbb_last.center.x
+                mcon_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=7, columns=7, x=x, y=y
+                )
+                mcon_m1bb2 = mcon_lay.bounds(mask=m1.mask)
+
+                shape = _geo.Rect.from_rect(rect=mcon_m1bb1, left=mcon_m1bb2.left)
+                layouter.add_wire(net=net, wire=m1, pin=m1pin, shape=shape)
+
+        # Connect dvdd
+        net = nets.dvdd
+
+        bottom = -115
+        shape = _geo.Rect.from_rect(rect=affsvdd_lipinbb_last, bottom=bottom)
+        layouter.add_wire(net=net, wire=li, shape=shape)
+        shape = _geo.Rect.from_rect(rect=affcvdd_lipinbb_last, bottom=bottom)
+        layouter.add_wire(net=net, wire=li, shape=shape)
+
+        left = sram_bb.left
+        right = sram_bb.right
+        for i in range(6):
+            # li
+            bottom = bottomblock_top - 2*i*stdcell_height - stdcellvdd_height
+            if i == 0:
+                top = bottom + stdcellvdd_height
+            else:
+                top = bottom + 2*stdcellvdd_height
+            shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+            layouter.add_wire(net=net, wire=li, shape=shape)
+
+            # nwell
+            bottom = bottomblock_top - (2*i + 1)*stdcell_height + stdcellnwelledge_height
+            if i == 0:
+                top = bottomblock_top + 1.0
+            else:
+                top = bottomblock_top - (2*i - 1)*stdcell_height - stdcellnwelledge_height
+            shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+            layouter.add_wire(net=net, wire=nwm, shape=shape)
+
+            x = left + 1.0
+            y = 0.5*(bottom + top)
+            mcon_lay = layouter.add_wire(
+                net=net, wire=mcon, rows=7, columns=7, x=x, y=y
+            )
+            mcon_m1bb1 = mcon_lay.bounds(mask=m1.mask)
+            via_lay = layouter.add_wire(
+                net=net, wire=via, rows=4, columns=4, x=x, y=y,
+            )
+            via_m2bb = via_lay.bounds(mask=m2.mask)
+            if i == 5:
+                # Connect with column
+                x = affsvdd_lipinbb_last.right
+                mcon_lay = layouter.add_wire(
+                    net=net, wire=mcon, rows=7, columns=7, x=x, y=y
+                )
+                mcon_m1bb2 = mcon_lay.bounds(mask=m1.mask)
+
+                shape = _geo.Rect.from_rect(rect=mcon_m1bb1, left=mcon_m1bb2.left)
+                layouter.add_wire(net=net, wire=m1, shape=shape)
+
+                shape = _geo.Rect.from_rect(rect=via_m2bb, top=bottomblock_top)
+                layouter.add_wire(net=net, wire=m2, pin=m2pin, shape=shape)
+
+        # Boundary
+        layouter.layout.boundary = _geo.Rect(
+            left=affsvss_lipinbb_last.left,
+            bottom=(bottomblock_top - 11*stdcell_height),
+            right = sram_bb.right,
+            top = sram_bb.top,
+        )
+
+class ConnectedSRAM(_lbry._Cell[_lbry.Library]):
+    def __init__(self, *, lib: _lbry.Library):
+        super().__init__(lib=lib, name="ConnectedSRAM")
+        tech = lib.tech
+        prims = tech.primitives
+
+        stdcells = sky130.stdcelllib.cells
+
+        spmem_fab = sky130.Sky130SP6TFactory(lib=self.lib)
+        dpmem_fab = sky130.Sky130DP8TFactory(lib=self.lib)
+
+        nwm = cast(_prm.Well, prims.nwm)
+        li = cast(_prm.MetalWire, prims.li)
+        lipin = cast(_prm.Marker, prims["li.pin"])
+        mcon = cast(_prm.Via, prims.mcon)
+        m1 = cast(_prm.MetalWire, prims.m1)
+        m1pin = cast(_prm.Marker, prims["m1.pin"])
+        via = cast(_prm.Via, prims.via)
+        m2 = cast(_prm.MetalWire, prims.m2)
+        m2pin = cast(_prm.Marker, prims["m2.pin"])
+        via2 = cast(_prm.Via, prims.via2)
+        m3 = cast(_prm.MetalWire, prims.m3)
+        m3pin = cast(_prm.Marker, prims["m3.pin"])
+        via3 = cast(_prm.Via, prims.via3)
+        m4 = cast(_prm.MetalWire, prims.m4)
+
+        zero_cell = stdcells.zero_x1
+        zero_nets = zero_cell.circuit.nets
+        _zero_zerolipinbb = zero_cell.layout.bounds(
+            mask=lipin.mask, net=zero_nets.zero, depth=1,
+        )
+        _zero_bb = zero_cell.layout.boundary
+        assert _zero_bb is not None
+
+        one_cell = stdcells.one_x1
+        _one_bb = one_cell.layout.boundary
+        assert _one_bb is not None
+
+        buf_cell = stdcells.buf_x2
+        buf_nets = buf_cell.circuit.nets
+        _buf_ilipinbb = buf_cell.layout.bounds(mask=lipin.mask, net=buf_nets.i, depth=1)
+        _buf_bb = buf_cell.layout.boundary
+        assert _buf_bb is not None
+
+        tie_cell = stdcells.tie_diff_w4
+        _tie_bb = tie_cell.layout.boundary
+        assert _tie_bb is not None
+
+        word_size = 8
+        we_size = 1
+        address_groups = (3, 4, 2)
+        a_bits = sum(address_groups)
+        spsram_cell = spmem_fab.block(
+            address_groups=(3, 4, 2), word_size=word_size, we_size=we_size,
+            cell_name="512x8",
+        )
+        spchar_cell = SPCharacterizationWrapper(lib=lib, spcell=spsram_cell)
+        dpsram_cell = dpmem_fab.block(
+            address_groups=(3, 4, 2), word_size=word_size, we_size=we_size,
+            cell_name="512x8",
+        )
+
+        ckt = self.new_circuit()
+        layouter = self.new_circuitlayouter()
+        layout = layouter.layout
+
+        # vss/vdd for the included standard cells
+        #
+        dvss_name = "vssd1"
+        dvss = ckt.new_net(name=dvss_name, external=True)
+        dvss_bb = _frm.toppins[dvss_name]
+
+        dvdd_name = "vccd1"
+        dvdd = ckt.new_net(name=dvdd_name, external=True)
+        dvdd_bb = _frm.toppins[dvdd_name]
+
+        # Place the SRAM
+        #
+        # instantiate
+        spsram = ckt.instantiate(spchar_cell, name="sram")
+        dpsram = ckt.instantiate(dpsram_cell, name="sram")
+
+        dvss.childports += spsram.ports.dvss
+        dvdd.childports += spsram.ports.dvdd
+
+        # place
+        _spsram_lay = layouter.inst_layout(inst=spsram)
+        _spsram_bb = _spsram_lay.boundary
+        assert _spsram_bb is not None
+        _dpsram_lay = layouter.inst_layout(inst=dpsram)
+        _dpsram_bb = _dpsram_lay.boundary
+        assert _dpsram_bb is not None
+
+        x = sky130.tech.on_grid(_frm.boundary.center.x - _spsram_bb.center.x)
+        y = _frm.boundary.top - 60.0 - _spsram_bb.top
+        spsram_lay = layouter.place(_spsram_lay, x=x, y=y)
+        spsram_bb = spsram_lay.boundary
+        assert spsram_bb is not None
+        x = sky130.tech.on_grid(_frm.boundary.center.x - _dpsram_bb.center.x)
+        y = 1600.0 - _dpsram_bb.bottom
+        dpsram_lay = layouter.place(_dpsram_lay, x=x, y=y)
+        dpsram_bb = dpsram_lay.boundary
+        assert dpsram_bb is not None
+
+        # Make three rows of to place standard cells in
+        #
+        dbound = 4.0
+        # left
+        rot_leftrow = _geo.Rotation.R90
+        _tie_rotbb = rot_leftrow*_tie_bb
+
+        x_leftrow = dbound - _tie_rotbb.left
+
+        inst = ckt.instantiate(tie_cell, name="lltie")
+        dvss.childports += inst.ports.vss
+        dvdd.childports += inst.ports.vdd
+
+        y_tie = dbound - _tie_rotbb.bottom
+        lay = layouter.place(inst, x=x_leftrow, y=y_tie, rotation=rot_leftrow)
+        nwmbb1 = lay.bounds(mask=nwm.mask)
+        lipindvssbb1 = lay.bounds(mask=lipin.mask, net=dvss, depth=1)
+        lipindvddbb1 = lay.bounds(mask=lipin.mask, net=dvdd, depth=1)
+
+        inst = ckt.instantiate(tie_cell, name="ultie")
+        dvss.childports += inst.ports.vss
+        dvdd.childports += inst.ports.vdd
+
+        y_tie = _frm.boundary.top - dbound - _tie_rotbb.top
+        lay = layouter.place(inst, x=x_leftrow, y=y_tie, rotation=rot_leftrow)
+        nwmbb2 = lay.bounds(mask=nwm.mask)
+        lipindvssbb2 = lay.bounds(mask=lipin.mask, net=dvss, depth=1)
+        lipindvddbb2 = lay.bounds(mask=lipin.mask, net=dvdd, depth=1)
+
+        shape = _geo.Rect.from_rect(rect=nwmbb1, top=nwmbb2.top)
+        layouter.add_wire(net=dvdd, wire=nwm, shape=shape)
+
+        shape = _geo.Rect.from_rect(rect=lipindvssbb1, top=lipindvssbb2.top)
+        layouter.add_wire(net=dvss, wire=li, shape=shape)
+        w = tech.on_grid(shape.width, mult=2, rounding="floor")
+        h = tech.on_grid(shape.height, mult=2, rounding="floor")
+        o = tech.on_grid(shape.center)
+        lay = layouter.add_wire(
+            net=dvss, wire=mcon, origin=o, bottom_width=w, bottom_height=h,
+        )
+        dvss_leftrowm1bb = lay.bounds(mask=m1.mask)
+
+        shape = _geo.Rect.from_rect(rect=lipindvddbb1, top=lipindvddbb2.top)
+        layouter.add_wire(net=dvdd, wire=li, shape=shape)
+        w = tech.on_grid(shape.width, mult=2, rounding="floor")
+        h = tech.on_grid(shape.height, mult=2, rounding="floor")
+        o = tech.on_grid(shape.center)
+        lay = layouter.add_wire(
+            net=dvdd, wire=mcon, origin=o, bottom_width=w, bottom_height=h,
+        )
+        dvdd_leftrowm1bb = lay.bounds(mask=m1.mask)
+
+        # right
+        rot_rightrow = _geo.Rotation.R90
+        _tie_rotbb = rot_rightrow*_tie_bb
+
+        x_rightrow = _frm.boundary.right - dbound - _tie_rotbb.right
+
+        inst = ckt.instantiate(tie_cell, name="lrtie")
+        dvss.childports += inst.ports.vss
+        dvdd.childports += inst.ports.vdd
+
+        y_tie = dbound - _tie_rotbb.bottom
+        lay = layouter.place(inst, x=x_rightrow, y=y_tie, rotation=rot_rightrow)
+        nwmbb1 = lay.bounds(mask=nwm.mask)
+        lipindvssbb1 = lay.bounds(mask=lipin.mask, net=dvss, depth=1)
+        lipindvddbb1 = lay.bounds(mask=lipin.mask, net=dvdd, depth=1)
+
+        inst = ckt.instantiate(tie_cell, name="urtie")
+        dvss.childports += inst.ports.vss
+        dvdd.childports += inst.ports.vdd
+
+        y_tie = _frm.boundary.top - dbound - _tie_rotbb.top
+        lay = layouter.place(inst, x=x_rightrow, y=y_tie, rotation=rot_rightrow)
+        nwmbb2 = lay.bounds(mask=nwm.mask)
+        lipindvssbb2 = lay.bounds(mask=lipin.mask, net=dvss, depth=1)
+        lipindvddbb2 = lay.bounds(mask=lipin.mask, net=dvdd, depth=1)
+
+        shape = _geo.Rect.from_rect(rect=nwmbb1, top=nwmbb2.top)
+        layouter.add_wire(net=dvdd, wire=nwm, shape=shape)
+
+        shape = _geo.Rect.from_rect(rect=lipindvssbb1, top=lipindvssbb2.top)
+        layouter.add_wire(net=dvss, wire=li, shape=shape)
+        w = tech.on_grid(shape.width, mult=2, rounding="floor")
+        h = tech.on_grid(shape.height, mult=2, rounding="floor")
+        o = tech.on_grid(shape.center)
+        lay = layouter.add_wire(
+            net=dvss, wire=mcon, origin=o, bottom_width=w, bottom_height=h,
+        )
+        dvss_rightrowm1bb = lay.bounds(mask=m1.mask)
+
+        assert dvss_rightrowm1bb.center.x < dvss_bb.center.x, "Internal error"
+        w = tech.on_grid(dvss_rightrowm1bb.width, mult=2, rounding="floor")
+        h = tech.on_grid(dvss_bb.height, mult=2, rounding="floor")
+        x_via = tech.on_grid(dvss_rightrowm1bb.center.x)
+        y_via = tech.on_grid(dvss_bb.center.y)
+        layouter.add_wire(
+            net=dvss, wire=via, x=x_via, y=y_via,
+            bottom_width=w, bottom_height=h, top_width=w, top_height=h,
+        )
+        via2_lay = layouter.add_wire(
+            net=dvss, wire=via2, x=x_via, y=y_via,
+            bottom_width=w, bottom_height=h, top_width=w, top_height=h,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        shape = _geo.Rect.from_rect(rect=dvss_bb, left=via2_m3bb.left)
+        layouter.add_wire(net=dvss, wire=m3, shape=shape)
+
+        layouter.add_wire(net=dvss, wire=m3, pin=m3pin, shape=dvss_bb)
+
+        shape = _geo.Rect.from_rect(rect=lipindvddbb1, top=lipindvddbb2.top)
+        layouter.add_wire(net=dvdd, wire=li, shape=shape)
+        w = tech.on_grid(shape.width, mult=2, rounding="floor")
+        h = tech.on_grid(shape.height, mult=2, rounding="floor")
+        o = tech.on_grid(shape.center)
+        lay = layouter.add_wire(
+            net=dvdd, wire=mcon, origin=o, bottom_width=w, bottom_height=h,
+        )
+        dvdd_rightrowm1bb = lay.bounds(mask=m1.mask)
+
+        assert dvdd_rightrowm1bb.center.x < dvdd_bb.center.x, "Internal error"
+        w = tech.on_grid(dvdd_rightrowm1bb.width, mult=2, rounding="floor")
+        h = tech.on_grid(dvdd_bb.height, mult=2, rounding="floor")
+        x_via = tech.on_grid(dvdd_rightrowm1bb.center.x)
+        y_via = tech.on_grid(dvdd_bb.center.y)
+        layouter.add_wire(
+            net=dvdd, wire=via, x=x_via, y=y_via,
+            bottom_width=w, bottom_height=h, top_width=w, top_height=h,
+        )
+        via2_lay = layouter.add_wire(
+            net=dvdd, wire=via2, x=x_via, y=y_via,
+            bottom_width=w, bottom_height=h, top_width=w, top_height=h,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        shape = _geo.Rect.from_rect(rect=dvdd_bb, left=via2_m3bb.left)
+        lay = layouter.add_wire(net=dvdd, wire=m3, shape=shape)
+
+        layouter.add_wire(net=dvdd, wire=m3, pin=m3pin, shape=dvdd_bb)
+
+        # Connect the SRAM signals
+        #
+        # svss
+        spec = io_sig2spec["svss"]
+        sram_port = spsram.ports[spec.sram_signal]
+        net = ckt.new_net(name=spec.toppin_name, external=True, childports=sram_port)
+        toppin_bb = _frm.toppins[spec.toppin_name]
+        sram_m3pinbb = spsram_lay.bounds(mask=m3pin.mask, net=net, depth=1)
+        left = sram_m3pinbb.left
+        right = sram_m3pinbb.right
+        top = sram_m3pinbb.top
+
+        shape = _geo.Rect.from_rect(rect=sram_m3pinbb, top=(sram_m3pinbb.top + 20.0))
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        shape = _geo.Rect(
+            left=toppin_bb.left, bottom=(top + 10.0), right=right, top=(top+20.0),
+        )
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+
+        # io_clamp_low
+        clamp_bb = _frm.toppins["io_clamp_low[1]"]
+        shape = _geo.Rect.from_rect(rect=clamp_bb, bottom=(top + 10))
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        # svdd
+        spec = io_sig2spec["svdd"]
+        sram_port = spsram.ports[spec.sram_signal]
+        net = ckt.new_net(name=spec.toppin_name, external=True, childports=sram_port)
+        toppin_bb = _frm.toppins[spec.toppin_name]
+        sram_m3pinbb = spsram_lay.bounds(mask=m3pin.mask, net=net, depth=1)
+        left = sram_m3pinbb.left
+        right = sram_m3pinbb.right
+        top = sram_m3pinbb.top
+
+        shape = _geo.Rect.from_rect(rect=sram_m3pinbb, top=(sram_m3pinbb.top + 20.0))
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        shape = _geo.Rect(
+            left=left, bottom=(top + 10.0), right=toppin_bb.right, top=(top + 20.0),
+        )
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+
+        # io_clamp_high
+        clamp_bb = _frm.toppins["io_clamp_high[1]"]
+        w = clamp_bb.width
+        shape = _geo.Rect.from_rect(rect=clamp_bb, bottom=(clamp_bb.bottom - 2*w))
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+        shape = _geo.Rect(
+            left=clamp_bb.left, bottom=(clamp_bb.bottom - 2*w),
+            right=toppin_bb.right, top=(clamp_bb.bottom - w)
+        )
+        layouter.add_wire(net=net, wire=m3, shape=shape)
+
+        #
+        # Support functions
+        #
+        def place_ioperiph(*, spec: _io_spec, sram: _ckt._CellInstance):
+            sig_name = spec.sram_signal
+            prefix = spec.prefix
+            num = spec.io_number
+
+            pin_name = spec.toppin_name
+            oeb_name = f"io_oeb[{num}]"
+            out_name = f"io_out[{num}]"
+            sram_port = sram.ports[sig_name]
+
+            if spec.io_type == "io_in":
+                assert spec.oeb, "Internal error"
+
+                # instantiate cells
+                buf = ckt.instantiate(buf_cell, name="{prefix}buf")
+                one = ckt.instantiate(one_cell, name=f"{prefix}one")
+                zero = ckt.instantiate(zero_cell, name=f"{prefix}zero")
+                tie = ckt.instantiate(tie_cell, name=f"{prefix}tie")
+
+                # create nets
+                pin_net = ckt.new_net(name=pin_name, external=True, childports=buf.ports.i)
+                sig_net = ckt.new_net(name=sig_name, external=False, childports=(
+                    buf.ports.q, sram_port,
+                ))
+                oeb_net = ckt.new_net(
+                    name=oeb_name, external=True, childports=one.ports.one,
+                )
+                out_net = ckt.new_net(
+                    name=out_name, external=True, childports=zero.ports.zero,
+                )
+
+                # get bbs
+                toppin_bb = _frm.toppins[pin_name]
+                oeb_bb = _frm.toppins[oeb_name]
+                out_bb = _frm.toppins[out_name]
+                is_leftrow = toppin_bb.center.x < _frm.boundary.center.x
+
+                rot = rot_leftrow if is_leftrow else rot_rightrow
+                x_row = x_leftrow if is_leftrow else x_rightrow
+
+                # place buf
+                _buf_rotilipinbb = rot*_buf_ilipinbb
+                y_buf = tech.on_grid(
+                    toppin_bb.top - _buf_rotilipinbb.bottom,
+                    mult=2,
+                )
+                buf_lay = layouter.place(buf, x=x_row, y=y_buf, rotation=rot)
+                pinbuf_lipinbb = buf_lay.bounds(mask=lipin.mask, net=pin_net, depth=1)
+                sigbuf_lipinbb = buf_lay.bounds(mask=lipin.mask, net=sig_net, depth=1)
+                buf_bb = buf_lay.boundary
+                assert buf_bb is not None
+
+                # place tie cell
+                _tie_rotbb = rot*_tie_bb
+                if is_leftrow:
+                    y_tie = buf_bb.top - _tie_rotbb.bottom
+                else:
+                    y_tie = buf_bb.bottom - _tie_rotbb.top
+                layouter.place(tie, x=x_row, y=y_tie, rotation=rot)
+
+                # place zero cell
+                _zero_rotbb = rot*_zero_bb
+                if is_leftrow:
+                    y_zero = buf_bb.bottom - _zero_rotbb.top
+                else:
+                    y_zero = buf_bb.top - _zero_rotbb.bottom
+                zero_lay = layouter.place(zero, x=x_row, y=y_zero, rotation=rot)
+                zero_bb = zero_lay.boundary
+                assert zero_bb is not None
+                zeroout_lipinbb = zero_lay.bounds(mask=lipin.mask, net=out_net, depth=1)
+
+                # place one cell
+                _one_rotbb = rot*_one_bb
+                if is_leftrow:
+                    y_one = zero_bb.bottom - _one_rotbb.top
+                else:
+                    y_one = zero_bb.top - _one_rotbb.bottom
+                one_lay = layouter.place(one, x=x_row, y=y_one, rotation=rot)
+                oneoeb_lipinbb = one_lay.bounds(mask=lipin.mask, net=oeb_net, depth=1)
+
+                # connect pin_net
+                w = tech.on_grid(pinbuf_lipinbb.width, mult=2, rounding="floor")
+                o_via = tech.on_grid(pinbuf_lipinbb.center)
+                layouter.add_wire(
+                    net=pin_net, wire=mcon, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                layouter.add_wire(
+                    net=pin_net, wire=via, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_lay = layouter.add_wire(
+                    net=pin_net, wire=via2, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+                if is_leftrow:
+                    shape = _geo.Rect.from_rect(rect=toppin_bb, right=via2_m3bb.right)
+                else:
+                    shape = _geo.Rect.from_rect(rect=toppin_bb, left=via2_m3bb.left)
+                layouter.add_wire(net=pin_net, wire=m3, shape=shape)
+                layouter.add_wire(net=pin_net, wire=m3, pin=m3pin, shape=toppin_bb)
+
+                # connect oeb_net
+                w = tech.on_grid(oneoeb_lipinbb.width, mult=2, rounding="floor")
+                o_via = tech.on_grid(oneoeb_lipinbb.center)
+                layouter.add_wire(
+                    net=oeb_net, wire=mcon, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via_lay = layouter.add_wire(
+                    net=oeb_net, wire=via, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via_m2bb = via_lay.bounds(mask=m2.mask)
+
+                o_via2 = _geo.Point.from_point(point=o_via, y=oeb_bb.center.y)
+                via2_lay = layouter.add_wire(
+                    net=oeb_net, wire=via2, origin=o_via2,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_m2bb = via2_lay.bounds(mask=m2.mask)
+                via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+                if is_leftrow:
+                    shape = _geo.Rect.from_rect(rect=via_m2bb, bottom=via2_m2bb.bottom)
+                else:
+                    shape = _geo.Rect.from_rect(rect=via_m2bb, top=via2_m2bb.top)
+                layouter.add_wire(net=oeb_net, wire=m2, shape=shape)
+                if is_leftrow:
+                    shape = _geo.Rect.from_rect(rect=oeb_bb, right=via2_m3bb.right)
+                else:
+                    shape = _geo.Rect.from_rect(rect=oeb_bb, left=via2_m3bb.left)
+                layouter.add_wire(net=oeb_net, wire=m3, shape=shape)
+
+                layouter.add_wire(net=oeb_net, wire=m3, pin=m3pin, shape=oeb_bb)
+
+                # connect out_net
+                w = tech.on_grid(zeroout_lipinbb.width, mult=2, rounding="floor")
+                o_via = tech.on_grid(zeroout_lipinbb.center)
+                layouter.add_wire(
+                    net=out_net, wire=mcon, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                layouter.add_wire(
+                    net=out_net, wire=via, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_lay = layouter.add_wire(
+                    net=out_net, wire=via2, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+                if is_leftrow:
+                    shape = _geo.Rect.from_rect(rect=via2_m3bb, bottom=out_bb.bottom)
+                else:
+                    shape = _geo.Rect.from_rect(rect=via2_m3bb, top=out_bb.top)
+                layouter.add_wire(net=out_net, wire=m3, shape=shape)
+                if is_leftrow:
+                    shape = _geo.Rect.from_rect(rect=out_bb, right=via2_m3bb.right)
+                else:
+                    shape = _geo.Rect.from_rect(rect=out_bb, left=via2_m3bb.left)
+                layouter.add_wire(net=out_net, wire=m3, shape=shape)
+
+                layouter.add_wire(net=out_net, wire=m3, pin=m3pin, shape=out_bb)
+
+                # connect sig_net
+                w = tech.on_grid(sigbuf_lipinbb.width, mult=2, rounding="floor")
+                o_via = tech.on_grid(sigbuf_lipinbb.center)
+                layouter.add_wire(
+                    net=sig_net, wire=mcon, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                layouter.add_wire(
+                    net=sig_net, wire=via, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_lay = layouter.add_wire(
+                    net=sig_net, wire=via2, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2sig_m3bb = via2_lay.bounds(mask=m3.mask)
+            elif spec.io_type == "io_out":
+                assert not spec.oeb, "Internal error"
+
+                # instantiate cells
+                buf = ckt.instantiate(buf_cell, name="{prefix}buf")
+                zero = ckt.instantiate(zero_cell, name=f"{prefix}zero")
+                tie = ckt.instantiate(tie_cell, name=f"{prefix}tie")
+
+                # create nets
+                sig_net = pin_net = ckt.new_net(
+                    name=pin_name, external=True, childports=sram_port,
+                )
+                oeb_net = ckt.new_net(
+                    name=oeb_name, external=True, childports=zero.ports.zero,
+                )
+
+                # get bss
+                toppin_bb = _frm.toppins[pin_name]
+                oeb_bb = _frm.toppins[oeb_name]
+
+                is_leftrow = toppin_bb.center.x < _frm.boundary.center.x
+
+                # place zero
+                rot = rot_leftrow if is_leftrow else rot_rightrow
+                x_row = x_leftrow if is_leftrow else x_rightrow
+                _zero_rotzerolipinbb = rot*_zero_zerolipinbb
+                y_zero = oeb_bb.center.y - _zero_rotzerolipinbb.center.y
+                zero_lay = layouter.place(zero, x=x_row, y=y_zero, rotation=rot)
+                zero_zerolipinbb = zero_lay.bounds(mask=lipin.mask, net=oeb_net, depth=1)
+                zero_bb = zero_lay.boundary
+                assert zero_bb is not None
+
+                # place tie
+                _tie_rotbb = rot*_tie_bb
+                y_tie = zero_bb.top - _tie_rotbb.bottom
+                layouter.place(tie, x=x_row, y=y_tie, rotation=rot)
+
+                # connect sig_net
+                layouter.add_wire(net=sig_net, wire=m3, pin=m3pin, shape=toppin_bb)
+                if is_leftrow:
+                    via2sig_m3bb = _geo.Rect(
+                        left=toppin_bb.right, bottom=toppin_bb.bottom,
+                        right=(toppin_bb.right + 2.0), top=toppin_bb.top,
+                    )
+                else:
+                    via2sig_m3bb = _geo.Rect(
+                        left=(toppin_bb.left - 2.0), bottom=toppin_bb.bottom,
+                        right=toppin_bb.left, top=toppin_bb.top,
+                    )
+
+                # connect oeb_net
+                w = tech.on_grid(zero_zerolipinbb.width, mult=2, rounding="floor")
+                o_via = tech.on_grid(zero_zerolipinbb.center)
+                layouter.add_wire(
+                    net=oeb_net, wire=mcon, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                layouter.add_wire(
+                    net=oeb_net, wire=via, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_lay = layouter.add_wire(
+                    net=oeb_net, wire=via2, origin=o_via,
+                    bottom_width=w, bottom_enclosure="wide",
+                    top_width=w, top_enclosure="wide",
+                )
+                via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+                if is_leftrow:
+                    shape = _geo.Rect.from_rect(rect=oeb_bb, right=via2_m3bb.right)
+                else:
+                    shape = _geo.Rect.from_rect(rect=oeb_bb, left=via2_m3bb.left)
+                layouter.add_wire(net=oeb_net, wire=m3, shape=shape)
+                layouter.add_wire(net=oeb_net, wire=m3, pin=m3pin, shape=oeb_bb)
+            else:
+                assert False, "Internal error"
+
+            return sig_net, via2sig_m3bb
+
+        #
+        # SP connections
+        #
+
+        left_col = 1
+        right_col = 1
+        col_width = 10.0
+        col_pitch = 20.0
+        col_left0 = 20.0
+        col_right0 = 2890.0
+
+        # Connect in_shiftclk
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["in_shiftclk"], sram=spsram,
+        )
+
+        sramsig_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=sig_net, depth=1)
+
+        _viasig_lay = layouter.wire_layout(
+            net=sig_net, wire=via, rows=10, columns=10,
+        )
+        _viasig_m1bb = _viasig_lay.bounds(mask=m1.mask)
+
+        x = sramsig_m1pinbb.right - _viasig_m1bb.right
+        y = sramsig_m1pinbb.center.y
+        layouter.place(_viasig_lay, x=x, y=y)
+        via2_lay = layouter.add_wire(
+            net=sig_net, wire=via2, rows=10, columns=10, x=x, y=y,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_left = col_left0 + (left_col - 1)*col_pitch
+        col_right = col_left + col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (sig_m3bb.left, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.top + 1.0),
+            (col_left, sig_m3bb.top + 1.0),
+            (col_left, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.bottom),
+            (col_right, via2_m3bb.bottom),
+            (col_right, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        left_col += 1
+
+        # Connect shift_in
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["shift_in"], sram=spsram,
+        )
+
+        sramsig_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=sig_net, depth=1)
+
+        _viasig_lay = layouter.wire_layout(
+            net=sig_net, wire=via, rows=10, columns=10,
+        )
+        _viasig_m1bb = _viasig_lay.bounds(mask=m1.mask)
+
+        x = sramsig_m1pinbb.right - _viasig_m1bb.right
+        y = sramsig_m1pinbb.center.y
+        layouter.place(_viasig_lay, x=x, y=y)
+        via2_lay = layouter.add_wire(
+            net=sig_net, wire=via2, rows=10, columns=10, x=x, y=y,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_left = col_left0 + (left_col - 1)*col_pitch
+        col_right = col_left + col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (sig_m3bb.left, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.top + 1.0),
+            (col_left, sig_m3bb.top + 1.0),
+            (col_left, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.bottom),
+            (col_right, via2_m3bb.bottom),
+            (col_right, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        left_col += 1
+
+        # Connect in_captureclk_l
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["in_captureclk_l"], sram=spsram,
+        )
+
+        sramsig_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=sig_net, depth=1)
+
+        _viasig_lay = layouter.wire_layout(
+            net=sig_net, wire=via, rows=10, columns=10,
+        )
+        _viasig_m1bb = _viasig_lay.bounds(mask=m1.mask)
+
+        x = sramsig_m1pinbb.right - _viasig_m1bb.right
+        y = sramsig_m1pinbb.center.y
+        layouter.place(_viasig_lay, x=x, y=y)
+        via2_lay = layouter.add_wire(
+            net=sig_net, wire=via2, rows=10, columns=10, x=x, y=y,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_left = col_left0 + (left_col - 1)*col_pitch
+        col_right = col_left + col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (sig_m3bb.left, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.top + 1.0),
+            (col_left, sig_m3bb.top + 1.0),
+            (col_left, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.bottom),
+            (col_right, via2_m3bb.bottom),
+            (col_right, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        left_col += 1
+
+        # Connect in_captureclk
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["in_captureclk"], sram=spsram,
+        )
+
+        sramsig_m2pinbb = spsram_lay.bounds(mask=m2pin.mask, net=sig_net, depth=1)
+
+        _via2sig_lay = layouter.wire_layout(
+            net=sig_net, wire=via2, rows=10, columns=10,
+        )
+        _via2sig_m2bb = _via2sig_lay.bounds(mask=m2.mask)
+
+        x = sramsig_m2pinbb.right - _via2sig_m2bb.right
+        y = sramsig_m2pinbb.top - _via2sig_m2bb.top
+        via2_lay = layouter.place(_via2sig_lay, x=x, y=y)
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_left = col_left0 + (left_col - 1)*col_pitch
+        col_right = col_left + col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (sig_m3bb.left, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.top + 1.0),
+            (col_left, sig_m3bb.top + 1.0),
+            (col_left, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.bottom),
+            (col_right, via2_m3bb.bottom),
+            (col_right, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        left_col += 1
+
+        # Connect sramclk
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["sramclk"], sram=spsram,
+        )
+
+        sramsig_m2pinbb = spsram_lay.bounds(mask=m2pin.mask, net=sig_net, depth=1)
+
+        _via2sig_lay = layouter.wire_layout(
+            net=sig_net, wire=via2, rows=10, columns=10,
+        )
+        _via2sig_m2bb = _via2sig_lay.bounds(mask=m2.mask)
+
+        x = sramsig_m2pinbb.right - _via2sig_m2bb.right
+        y = sramsig_m2pinbb.bottom - _via2sig_m2bb.bottom
+        via2_lay = layouter.place(_via2sig_lay, x=x, y=y)
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_left = col_left0 + (left_col - 1)*col_pitch
+        col_right = col_left + col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (sig_m3bb.left, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.top + 1.0),
+            (col_left, sig_m3bb.top + 1.0),
+            (col_left, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.top),
+            (via2_m3bb.right, via2_m3bb.bottom),
+            (col_right, via2_m3bb.bottom),
+            (col_right, sig_m3bb.bottom),
+            (sig_m3bb.left, sig_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        left_col += 1
+
+        # Connect out_captureclk_l
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["out_captureclk_l"], sram=spsram,
+        )
+
+        sramsig_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=sig_net, depth=1)
+
+        _viasig_lay = layouter.wire_layout(
+            net=sig_net, wire=via, rows=10, columns=10,
+        )
+        _viasig_m1bb = _viasig_lay.bounds(mask=m1.mask)
+
+        x = sramsig_m1pinbb.right - _viasig_m1bb.right
+        y = sramsig_m1pinbb.center.y
+        layouter.place(_viasig_lay, x=x, y=y)
+        via2_lay = layouter.add_wire(
+            net=sig_net, wire=via2, rows=10, columns=10, x=x, y=y,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_right = col_right0 - (right_col - 1)*col_pitch
+        col_left = col_right - col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (via2_m3bb.left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.top),
+            (col_right, via2_m3bb.top),
+            (col_right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.bottom),
+            (col_left, sig_m3bb.bottom),
+            (col_left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        right_col += 1
+
+        # Connect out_captureclk
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["out_captureclk"], sram=spsram,
+        )
+
+        sramsig_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=sig_net, depth=1)
+
+        _viasig_lay = layouter.wire_layout(
+            net=sig_net, wire=via, rows=10, columns=10,
+        )
+        _viasig_m1bb = _viasig_lay.bounds(mask=m1.mask)
+
+        x = sramsig_m1pinbb.left - _viasig_m1bb.left
+        y = sramsig_m1pinbb.center.y
+        layouter.place(_viasig_lay, x=x, y=y)
+        via2_lay = layouter.add_wire(
+            net=sig_net, wire=via2, rows=10, columns=10, x=x, y=y,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_right = col_right0 - (right_col - 1)*col_pitch
+        col_left = col_right - col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (via2_m3bb.left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.top),
+            (col_right, via2_m3bb.top),
+            (col_right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.bottom),
+            (col_left, sig_m3bb.bottom),
+            (col_left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        right_col += 1
+
+        # Connect out_docapture
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["out_docapture"], sram=spsram,
+        )
+
+        sramsig_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=sig_net, depth=1)
+
+        _viasig_lay = layouter.wire_layout(
+            net=sig_net, wire=via, rows=10, columns=10,
+        )
+        _viasig_m1bb = _viasig_lay.bounds(mask=m1.mask)
+
+        x = sramsig_m1pinbb.right + 5.0 - _viasig_m1bb.left
+        y = sramsig_m1pinbb.center.y - 1.0
+        via_lay = layouter.place(_viasig_lay, x=x, y=y)
+        via_m1bb = via_lay.bounds(mask=m1.mask)
+        via2_lay = layouter.add_wire(
+            net=sig_net, wire=via2, rows=10, columns=10, x=x, y=y,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        shape =_geo.Rect.from_rect(rect=sramsig_m1pinbb, right=via_m1bb.right)
+        layouter.add_wire(net=sig_net, wire=m1, shape=shape)
+
+        col_right = col_right0 - (right_col - 1)*col_pitch
+        col_left = col_right - col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (via2_m3bb.left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.top),
+            (col_right, via2_m3bb.top),
+            (col_right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.bottom),
+            (col_left, sig_m3bb.bottom),
+            (col_left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        right_col += 1
+
+        # Connect out_shiftclk
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["out_shiftclk"], sram=spsram,
+        )
+
+        sramsig_m2pinbb = spsram_lay.bounds(mask=m2pin.mask, net=sig_net, depth=1)
+
+        _via2sig_lay = layouter.wire_layout(
+            net=sig_net, wire=via2, rows=10, columns=10,
+        )
+        _via2sig_m2bb = _via2sig_lay.bounds(mask=m2.mask)
+
+        x = sramsig_m2pinbb.left - _via2sig_m2bb.left
+        y = sramsig_m2pinbb.center.y - _via2sig_m2bb.top
+        via2_lay = layouter.place(_via2sig_lay, x=x, y=y)
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_right = col_right0 - (right_col - 1)*col_pitch
+        col_left = col_right - col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (via2_m3bb.left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.top),
+            (col_right, via2_m3bb.top),
+            (col_right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.bottom),
+            (col_left, sig_m3bb.bottom),
+            (col_left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        right_col += 1
+
+        # Connect shift_out
+        sig_net, sig_m3bb = place_ioperiph(
+            spec=io_spsig2spec["shift_out"], sram=spsram,
+        )
+
+        sramsig_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=sig_net, depth=1)
+
+        _viasig_lay = layouter.wire_layout(
+            net=sig_net, wire=via, rows=10, columns=10,
+        )
+        _viasig_m1bb = _viasig_lay.bounds(mask=m1.mask)
+
+        x = sramsig_m1pinbb.left - _viasig_m1bb.left
+        y = sramsig_m1pinbb.top - _viasig_m1bb.top
+        layouter.place(_viasig_lay, x=x, y=y)
+        via2_lay = layouter.add_wire(
+            net=sig_net, wire=via2, rows=10, columns=10, x=x, y=y,
+        )
+        via2_m3bb = via2_lay.bounds(mask=m3.mask)
+
+        col_right = col_right0 - (right_col - 1)*col_pitch
+        col_left = col_right - col_width
+        shape = _geo.Polygon.from_floats(points=(
+            (via2_m3bb.left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.top),
+            (col_right, via2_m3bb.top),
+            (col_right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.top + 1.0),
+            (sig_m3bb.right, sig_m3bb.bottom),
+            (col_left, sig_m3bb.bottom),
+            (col_left, via2_m3bb.bottom),
+            (via2_m3bb.left, via2_m3bb.bottom),
+        ))
+        layouter.add_wire(net=sig_net, wire=m3, shape=shape)
+
+        right_col += 1
+
+        # Connect dvss/dvdd
+        dc_width = 10.0
+
+        sramdvss_m1pinbb = spsram_lay.bounds(mask=m1pin.mask, net=dvss, depth=1)
+        sramdvdd_m2pinbb = spsram_lay.bounds(mask=m2pin.mask, net=dvdd, depth=1)
+
+        o = sramdvss_m1pinbb.center
+        layouter.add_wire(
+            net=dvss, wire=via, origin=o, rows=3,
+            bottom_width=sramdvss_m1pinbb.width
+        )
+        layouter.add_wire(
+            net=dvss, wire=via2, origin=o,
+            bottom_width=sramdvss_m1pinbb.width, bottom_height=dc_width,
+        )
+        via3dvss_lay = layouter.add_wire(
+            net=dvss, wire=via3, origin=o,
+            bottom_width=sramdvss_m1pinbb.width, bottom_height=dc_width,
+        )
+        via3dvss_m4bb = via3dvss_lay.bounds(mask=m4.mask)
+
+        shape = _geo.Rect.from_rect(
+            rect=via3dvss_m4bb, left=dvss_leftrowm1bb.left, right=dvss_rightrowm1bb.right,
+        )
+        layouter.add_wire(net=dvss, wire=m4, shape=shape)
+
+        shape = _geo.Rect(
+            left=dvss_leftrowm1bb.left, bottom=via3dvss_m4bb.bottom,
+            right=dvss_leftrowm1bb.right, top=via3dvss_m4bb.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via, bottom_shape=shape, top_shape=shape,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via2, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via3, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+
+        shape = _geo.Rect(
+            left=dvss_rightrowm1bb.left, bottom=via3dvss_m4bb.bottom,
+            right=dvss_rightrowm1bb.right, top=via3dvss_m4bb.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via, bottom_shape=shape, top_shape=shape,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via2, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via3, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+
+        bottom = via3dvss_m4bb.top + 1.0
+        top = bottom + dc_width
+        right = sramdvdd_m2pinbb.right
+        left = right - dc_width
+        shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+        layouter.add_wire(
+            net=dvss, wire=via2, bottom_shape=shape, top_shape=shape,
+        )
+        via3dvdd_lay = layouter.add_wire(
+            net=dvss, wire=via3, bottom_shape=shape, top_shape=shape,
+        )
+        via3dvdd_m4bb = via3dvdd_lay.bounds(mask=m4.mask)
+
+        shape = _geo.Rect.from_rect(
+            rect=via3dvdd_m4bb, left=dvdd_leftrowm1bb.left, right=dvdd_rightrowm1bb.right,
+        )
+        layouter.add_wire(net=dvss, wire=m4, shape=shape)
+
+        shape = _geo.Rect(
+            left=dvdd_leftrowm1bb.left, bottom=via3dvdd_m4bb.bottom,
+            right=dvdd_leftrowm1bb.right, top=via3dvdd_m4bb.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via, bottom_shape=shape, top_shape=shape,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via2, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via3, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+
+        shape = _geo.Rect(
+            left=dvdd_rightrowm1bb.left, bottom=via3dvdd_m4bb.bottom,
+            right=dvdd_rightrowm1bb.right, top=via3dvdd_m4bb.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via, bottom_shape=shape, top_shape=shape,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via2, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+        layouter.add_wire(
+            net=dvss, wire=via3, x=shape.center.x, columns=10,
+            bottom_bottom=shape.bottom, bottom_top=shape.top,
+            top_bottom=shape.bottom, top_top=shape.top,
+        )
+
+        # boundary
+        #
+        layout.boundary = _frm.boundary
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
deleted file mode 100644
index 764b362..0000000
--- a/gds/user_analog_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
new file mode 100644
index 0000000..45b162d
--- /dev/null
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ
diff --git a/gds/user_analog_project_wrapper_empty.gds b/gds/user_analog_project_wrapper_empty.gds
new file mode 100644
index 0000000..1951c76
--- /dev/null
+++ b/gds/user_analog_project_wrapper_empty.gds
Binary files differ
diff --git a/mag/example_por.mag b/mag/example_por.mag
deleted file mode 100644
index 1b8c9ba..0000000
--- a/mag/example_por.mag
+++ /dev/null
@@ -1,603 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1620310959
-<< nwell >>
-rect 70 7344 6652 7795
-rect 7401 6799 10893 7301
-<< pwell >>
-rect 463 6569 519 6579
-rect 2635 5816 2853 6026
-<< mvpsubdiff >>
-rect 7438 7387 10856 7455
-<< mvnsubdiff >>
-rect 7467 7201 10827 7235
-<< locali >>
-rect 41 8275 183 8288
-rect 41 8190 57 8275
-rect 169 8190 183 8275
-rect 41 7451 183 8190
-rect 6891 8273 7134 8286
-rect 6891 8112 6936 8273
-rect 7117 8112 7134 8273
-rect 6891 7455 7134 8112
-rect 3043 7451 7134 7455
-rect 41 7435 7134 7451
-rect 41 7305 6927 7435
-rect 35 6388 121 7179
-rect 3043 7022 6927 7305
-rect 7110 7322 7134 7435
-rect 7110 7201 10829 7322
-rect 7110 7022 7134 7201
-rect 3043 7005 7134 7022
-rect 2907 6693 7134 6838
-rect 2907 6388 3220 6693
-rect 35 6320 3220 6388
-rect 35 6318 505 6320
-rect 35 6192 48 6318
-rect 286 6192 505 6318
-rect 35 6191 505 6192
-rect 2951 6253 3220 6320
-rect 6116 6388 7134 6693
-rect 6116 6253 10860 6388
-rect 2951 6191 10860 6253
-rect 35 6143 10860 6191
-rect 35 5813 689 6143
-rect 1006 5813 1393 6029
-rect 1778 5813 2165 6029
-rect 2550 6015 2937 6029
-rect 2550 5829 2648 6015
-rect 2840 5829 2937 6015
-rect 2550 5813 2937 5829
-rect 3322 5813 3709 6029
-rect 4094 5813 4481 6029
-rect 4866 5813 5253 6029
-rect 5638 5813 6025 6029
-rect 6410 5813 6797 6029
-rect 7182 5813 7569 6029
-rect 7954 5813 8341 6029
-rect 8726 5813 9113 6029
-rect 9498 5813 9885 6029
-rect 10656 5813 10837 6029
-rect 51 165 234 381
-rect 619 165 1006 381
-rect 1391 165 1778 381
-rect 2163 165 2550 381
-rect 2935 165 3322 381
-rect 3707 165 4094 381
-rect 4479 165 4866 381
-rect 5251 165 5638 381
-rect 6023 165 6410 381
-rect 6795 165 7182 381
-rect 7567 165 7954 381
-rect 8339 165 8726 381
-rect 9111 165 9498 381
-rect 9883 165 10270 381
-rect 10655 165 10835 381
-<< viali >>
-rect 57 8190 169 8275
-rect 6936 8112 7117 8273
-rect 9224 7854 9270 8060
-rect 7604 7754 7807 7801
-rect 9459 7754 9796 7801
-rect 10785 7683 10819 7879
-rect 6927 7022 7110 7435
-rect 7870 6775 8128 6834
-rect 48 6192 286 6318
-rect 505 6191 2951 6320
-rect 3220 6253 6116 6693
-rect 8439 6684 8506 6878
-rect 8650 6720 8853 6767
-rect 10270 6735 10316 6896
-rect 2648 5829 2840 6015
-rect 10202 5598 10340 6030
-<< metal1 >>
-rect 40 8275 7133 8286
-rect 40 8190 57 8275
-rect 169 8273 7133 8275
-rect 169 8269 6936 8273
-rect 624 8260 6936 8269
-rect 624 8201 1026 8260
-rect 169 8193 1026 8201
-rect 7117 8209 7133 8273
-rect 7284 8252 10841 8278
-rect 169 8190 6936 8193
-rect 40 8179 6936 8190
-rect 218 8110 376 8127
-rect 218 8038 436 8110
-rect 709 8082 719 8144
-rect 801 8129 818 8144
-rect 801 8085 2498 8129
-rect 2829 8085 2990 8129
-rect 801 8082 818 8085
-rect 218 8024 282 8038
-rect 218 7641 313 8024
-rect 375 7641 436 8038
-rect 521 7788 567 8040
-rect 627 7892 2821 8028
-rect 502 7653 2537 7788
-rect 218 7568 436 7641
-rect 521 7597 567 7653
-rect 709 7597 719 7606
-rect 218 7554 375 7568
-rect 218 7501 282 7554
-rect 521 7553 719 7597
-rect 709 7544 719 7553
-rect 801 7597 818 7606
-rect 2866 7597 2944 8085
-rect 2993 7658 3300 7804
-rect 801 7556 2990 7597
-rect 801 7553 2922 7556
-rect 801 7544 818 7553
-rect 3360 7501 3433 8122
-rect 3699 8082 3959 8128
-rect 3486 7636 3556 8035
-rect 218 7453 3433 7501
-rect 218 7248 282 7453
-rect 3497 7344 3556 7636
-rect 185 7121 282 7248
-rect 2382 7274 3556 7344
-rect 3699 7642 3781 8082
-rect 4283 8081 5747 8125
-rect 6083 8081 6237 8125
-rect 6910 8112 6936 8179
-rect 7117 8112 7134 8209
-rect 7284 8153 7318 8252
-rect 10802 8153 10841 8252
-rect 7284 8125 10841 8153
-rect 3988 7805 4025 8041
-rect 4109 7872 6071 8033
-rect 3966 7645 5802 7805
-rect 3699 7600 3773 7642
-rect 3699 7554 3958 7600
-rect 3988 7597 4025 7645
-rect 6126 7597 6188 8081
-rect 6249 7884 6537 8029
-rect 6249 7690 6262 7884
-rect 3699 7501 3773 7554
-rect 3988 7553 6239 7597
-rect 6612 7501 6674 8112
-rect 3699 7453 6674 7501
-rect 185 6969 263 7121
-rect 2382 7074 2452 7274
-rect 3699 7165 3773 7453
-rect 2265 7047 2275 7074
-rect 185 6573 282 6969
-rect 25 6318 301 6326
-rect 25 6192 48 6318
-rect 286 6192 301 6318
-rect 25 6185 301 6192
-rect 25 5348 133 6185
-rect 345 5944 399 7033
-rect 781 7003 2275 7047
-rect 2351 7047 2452 7074
-rect 2767 7074 3773 7165
-rect 2351 7003 2738 7047
-rect 463 6745 634 6972
-rect 2382 6952 2452 7003
-rect 721 6815 2452 6952
-rect 463 6579 2560 6745
-rect 463 6569 634 6579
-rect 505 6326 634 6569
-rect 2629 6533 2693 7003
-rect 2767 6949 2842 7074
-rect 6752 7065 6823 8044
-rect 6910 7435 7134 8112
-rect 9218 8060 9276 8072
-rect 9218 7854 9224 8060
-rect 9270 8051 9276 8060
-rect 10128 8051 10138 8053
-rect 9270 8001 10138 8051
-rect 9270 7854 9276 8001
-rect 10128 7999 10138 8001
-rect 10290 7999 10300 8053
-rect 9218 7842 9276 7854
-rect 10779 7879 10825 7891
-rect 7592 7801 8339 7807
-rect 7592 7754 7604 7801
-rect 7807 7754 8339 7801
-rect 7592 7748 8339 7754
-rect 8519 7801 9808 7807
-rect 8519 7754 9459 7801
-rect 9796 7754 9808 7801
-rect 8519 7748 9808 7754
-rect 10779 7728 10785 7879
-rect 10819 7728 10825 7879
-rect 10743 7674 10753 7728
-rect 10905 7674 10915 7728
-rect 10779 7671 10825 7674
-rect 2756 6573 2842 6949
-rect 6407 7036 6825 7065
-rect 3167 6819 6174 6842
-rect 3167 6693 4331 6819
-rect 5278 6693 6174 6819
-rect 781 6489 2275 6533
-rect 2265 6460 2275 6489
-rect 2350 6460 2360 6533
-rect 2585 6489 2739 6533
-rect 3167 6326 3220 6693
-rect 493 6320 3220 6326
-rect 493 6191 505 6320
-rect 2951 6253 3220 6320
-rect 6116 6531 6174 6693
-rect 6407 6623 6432 7036
-rect 6803 6840 6825 7036
-rect 6910 7022 6927 7435
-rect 7110 7324 7134 7435
-rect 7279 7543 10836 7570
-rect 7279 7449 7306 7543
-rect 8343 7449 8618 7543
-rect 10649 7449 10836 7543
-rect 7279 7417 10836 7449
-rect 7110 7299 10832 7324
-rect 7110 7124 7171 7299
-rect 8320 7124 8602 7299
-rect 10750 7124 10832 7299
-rect 7110 7094 10832 7124
-rect 7110 7022 7134 7094
-rect 10516 7093 10832 7094
-rect 6910 6994 7134 7022
-rect 10264 6896 10322 6908
-rect 8433 6878 8512 6890
-rect 6803 6834 8140 6840
-rect 6803 6775 7870 6834
-rect 8128 6775 8140 6834
-rect 6803 6769 8140 6775
-rect 6803 6623 6825 6769
-rect 8429 6684 8439 6878
-rect 8506 6773 8516 6878
-rect 8506 6767 8865 6773
-rect 8506 6720 8650 6767
-rect 8853 6720 8865 6767
-rect 10264 6735 10270 6896
-rect 10316 6834 10322 6896
-rect 10316 6765 10507 6834
-rect 10672 6765 10682 6834
-rect 10316 6735 10322 6765
-rect 10264 6723 10322 6735
-rect 8506 6714 8865 6720
-rect 8506 6684 8516 6714
-rect 8433 6672 8512 6684
-rect 6407 6600 6825 6623
-rect 6116 6319 10827 6531
-rect 6116 6253 6174 6319
-rect 2951 6237 6174 6253
-rect 10221 6260 10716 6270
-rect 2951 6191 6175 6237
-rect 493 6185 6175 6191
-rect 10221 6187 10233 6260
-rect 10700 6187 10716 6260
-rect 10221 6176 10716 6187
-rect 10221 6045 10315 6176
-rect 10187 6030 10353 6045
-rect 2635 6015 2853 6026
-rect 2635 5944 2648 6015
-rect 345 5890 2648 5944
-rect 2635 5829 2648 5890
-rect 2840 5829 2853 6015
-rect 2635 5816 2853 5829
-rect 10187 5598 10202 6030
-rect 10340 5598 10353 6030
-rect 10187 5582 10353 5598
-rect 10805 5348 10867 6079
-rect 25 4748 10867 5348
-rect 25 4348 133 4748
-rect 10805 4348 10867 4748
-rect 25 3748 10867 4348
-rect 25 3348 133 3748
-rect 10805 3348 10867 3748
-rect 25 2748 10867 3348
-rect 25 2348 133 2748
-rect 10805 2348 10867 2748
-rect 25 1748 10867 2348
-rect 25 1348 133 1748
-rect 10805 1348 10867 1748
-rect 25 748 10867 1348
-rect 25 99 133 748
-rect 10805 99 10867 748
-rect 25 11 10867 99
-<< via1 >>
-rect 60 8201 169 8269
-rect 169 8201 624 8269
-rect 1026 8193 6936 8260
-rect 6936 8193 7093 8260
-rect 719 8082 801 8144
-rect 719 7544 801 7606
-rect 7318 8153 10802 8252
-rect 2275 7003 2351 7074
-rect 10138 7999 10290 8053
-rect 8339 7748 8519 7807
-rect 10753 7683 10785 7728
-rect 10785 7683 10819 7728
-rect 10819 7683 10905 7728
-rect 10753 7674 10905 7683
-rect 4331 6693 5278 6819
-rect 2275 6460 2350 6533
-rect 4331 6270 5278 6693
-rect 6432 6623 6803 7036
-rect 7306 7449 8343 7543
-rect 8618 7449 10649 7543
-rect 7171 7124 8320 7299
-rect 8602 7124 10750 7299
-rect 8439 6684 8506 6878
-rect 10507 6765 10672 6834
-rect 10233 6187 10700 6260
-<< metal2 >>
-rect 985 8286 7132 8287
-rect 38 8269 7132 8286
-rect 38 8201 60 8269
-rect 624 8261 7132 8269
-rect 38 8104 77 8201
-rect 634 8187 886 8261
-rect 7091 8260 7132 8261
-rect 7093 8193 7132 8260
-rect 634 8104 654 8187
-rect 38 8061 654 8104
-rect 719 8144 801 8154
-rect 719 8072 801 8082
-rect 866 8104 886 8187
-rect 7091 8104 7132 8193
-rect 7284 8252 10841 8278
-rect 7284 8153 7318 8252
-rect 10802 8153 10841 8252
-rect 7284 8125 10841 8153
-rect 729 7616 785 8072
-rect 866 8060 7132 8104
-rect 10138 8056 10290 8066
-rect 10138 7986 10290 7996
-rect 8339 7807 8519 7817
-rect 8339 7738 8519 7748
-rect 719 7606 801 7616
-rect 719 7534 801 7544
-rect 7279 7543 8374 7570
-rect 7279 7449 7306 7543
-rect 8343 7449 8374 7543
-rect 7279 7417 8374 7449
-rect 7141 7299 8355 7324
-rect 7141 7124 7171 7299
-rect 8320 7124 8355 7299
-rect 7141 7094 8355 7124
-rect 2275 7074 2351 7084
-rect 2275 6993 2351 7003
-rect 6407 7036 6825 7065
-rect 2288 6543 2340 6993
-rect 4308 6849 5298 6868
-rect 2275 6533 2350 6543
-rect 2275 6450 2350 6460
-rect 4308 6270 4331 6849
-rect 5278 6270 5298 6849
-rect 6407 6623 6432 7036
-rect 6803 6623 6825 7036
-rect 8443 6888 8500 7738
-rect 10753 7731 10905 7741
-rect 10753 7661 10905 7671
-rect 8588 7543 10667 7570
-rect 8587 7449 8618 7543
-rect 10649 7449 10667 7543
-rect 8588 7417 10667 7449
-rect 8567 7299 10798 7324
-rect 8567 7124 8602 7299
-rect 10750 7124 10798 7299
-rect 8567 7094 10798 7124
-rect 8439 6878 8506 6888
-rect 8439 6674 8506 6684
-rect 6407 6600 6825 6623
-rect 4308 6249 5298 6270
-rect 10221 6270 10431 7094
-rect 10498 6765 10507 6834
-rect 10672 6765 10757 6834
-rect 10909 6765 10918 6834
-rect 10221 6260 10716 6270
-rect 10221 6187 10233 6260
-rect 10700 6187 10716 6260
-rect 10221 6176 10716 6187
-<< via2 >>
-rect 77 8201 624 8261
-rect 624 8201 634 8261
-rect 77 8104 634 8201
-rect 886 8260 7091 8261
-rect 886 8193 1026 8260
-rect 1026 8193 7091 8260
-rect 886 8104 7091 8193
-rect 7318 8153 10802 8252
-rect 10138 8053 10290 8056
-rect 10138 7999 10290 8053
-rect 10138 7996 10290 7999
-rect 7306 7449 8343 7543
-rect 4331 6819 5278 6849
-rect 4331 6522 5278 6819
-rect 6432 6623 6803 7036
-rect 10753 7728 10905 7731
-rect 10753 7674 10905 7728
-rect 10753 7671 10905 7674
-rect 8618 7449 10649 7543
-rect 10757 6765 10909 6834
-<< metal3 >>
-rect 38 8261 7126 8283
-rect 38 8244 77 8261
-rect 634 8244 886 8261
-rect 38 8000 73 8244
-rect 7091 8104 7126 8261
-rect 7284 8252 10841 8278
-rect 7284 8153 7318 8252
-rect 10802 8153 10841 8252
-rect 7284 8125 10841 8153
-rect 7073 8000 7126 8104
-rect 38 7965 7126 8000
-rect 10128 8056 10295 8064
-rect 10128 7996 10138 8056
-rect 10290 7996 10431 8056
-rect 10128 7991 10295 7996
-rect 10371 7916 10431 7996
-rect 10371 7856 11343 7916
-rect 10743 7731 10910 7739
-rect 10743 7671 10753 7731
-rect 10905 7671 10910 7731
-rect 10743 7666 10910 7671
-rect 7279 7543 10667 7570
-rect 7279 7449 7306 7543
-rect 10649 7449 10667 7543
-rect 10792 7551 10852 7666
-rect 10792 7491 11344 7551
-rect 7279 7417 10667 7449
-rect 4111 7277 5299 7317
-rect 4111 6849 4350 7277
-rect 5268 6849 5299 7277
-rect 4111 6522 4331 6849
-rect 5278 6522 5299 6849
-rect 6408 7036 6825 7065
-rect 6408 6623 6432 7036
-rect 6803 6623 6825 7036
-rect 10747 6834 10918 6840
-rect 10747 6765 10757 6834
-rect 10909 6765 11342 6834
-rect 10747 6758 10918 6765
-rect 6408 6600 6825 6623
-rect 4111 6494 5299 6522
-rect 4111 6251 4307 6494
-<< via3 >>
-rect 73 8104 77 8244
-rect 77 8104 634 8244
-rect 634 8104 886 8244
-rect 886 8104 7073 8244
-rect 7318 8153 10802 8252
-rect 73 8000 7073 8104
-rect 7306 7449 8343 7543
-rect 8343 7449 8618 7543
-rect 8618 7449 10649 7543
-rect 4350 6849 5268 7277
-rect 4350 6558 5268 6849
-rect 6432 6623 6803 7036
-<< metal4 >>
-rect 38 8244 7126 8283
-rect 38 8000 73 8244
-rect 7073 8000 7126 8244
-rect 38 7965 7126 8000
-rect 7241 8252 11180 8291
-rect 7241 8153 7318 8252
-rect 10802 8153 11180 8252
-rect 7241 7962 11180 8153
-rect 10843 7755 11178 7774
-rect 38 7543 10667 7655
-rect 38 7449 7306 7543
-rect 10649 7449 10667 7543
-rect 38 7277 10667 7449
-rect 38 7255 4350 7277
-rect 3817 6558 4350 7255
-rect 5268 7255 10667 7277
-rect 5268 6558 5299 7255
-rect 10843 7074 10879 7755
-rect 6386 7036 10879 7074
-rect 6386 6623 6432 7036
-rect 6803 6623 10879 7036
-rect 6386 6615 10879 6623
-rect 11146 6615 11178 7755
-rect 6386 6591 11178 6615
-rect 3817 6522 5299 6558
-rect 3817 51 4011 6522
-rect 4101 51 4793 6251
-<< via4 >>
-rect 4350 6558 5268 7247
-rect 10879 6615 11146 7755
-<< metal5 >>
-rect 10851 7755 11171 7779
-rect 4313 7247 5299 7317
-rect 4313 6558 4350 7247
-rect 5268 6558 5299 7247
-rect 4313 6494 5299 6558
-rect 4507 6135 5299 6494
-rect 10851 6615 10879 7755
-rect 11146 6615 11171 7755
-rect 10851 6242 11171 6615
-use sky130_fd_pr__nfet_g5v0d10v5_TGFUGS  sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0
-timestamp 1606063140
-transform 1 0 1515 0 1 6769
-box -962 -458 962 458
-use sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC  sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1
-timestamp 1605994897
-transform -1 0 371 0 1 6769
-box -308 -458 308 458
-use sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ  sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0
-timestamp 1606063140
-transform 1 0 1657 0 1 7841
-box -1101 -497 1101 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3
-timestamp 1606063140
-transform 1 0 408 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__nfet_g5v0d10v5_PKVMTM  sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0
-timestamp 1606063140
-transform 1 0 2660 0 1 6770
-box -308 -458 308 458
-use sky130_fd_pr__pfet_g5v0d10v5_YUHPBG  sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0
-timestamp 1606063140
-transform 1 0 2906 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0
-timestamp 1606063140
-transform 1 0 3392 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1
-timestamp 1606063140
-transform 1 0 3878 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_YEUEBV  sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0
-timestamp 1606063140
-transform 1 0 5018 0 1 7841
-box -992 -497 992 497
-use sky130_fd_pr__pfet_g5v0d10v5_YUHPXE  sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0
-timestamp 1606063140
-transform 1 0 6158 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2
-timestamp 1606063140
-transform 1 0 6644 0 1 7841
-box -338 -497 338 497
-use sky130_fd_sc_hvl__schmittbuf_1  sky130_fd_sc_hvl__schmittbuf_1_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 7467 0 1 6404
-box -66 -43 1122 897
-use sky130_fd_sc_hvl__buf_8  sky130_fd_sc_hvl__buf_8_1 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 7477 0 1 7438
-box -66 -43 1986 897
-use sky130_fd_sc_hvl__buf_8  sky130_fd_sc_hvl__buf_8_0
-timestamp 1619722500
-transform 1 0 8523 0 1 6404
-box -66 -43 1986 897
-use sky130_fd_sc_hvl__fill_4  sky130_fd_sc_hvl__fill_4_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 10443 0 1 6404
-box -66 -43 450 897
-use sky130_fd_sc_hvl__inv_8  sky130_fd_sc_hvl__inv_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 9397 0 1 7438
-box -66 -43 1506 897
-use sky130_fd_pr__res_xhigh_po_0p69_S5N9F3  sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0
-timestamp 1606074388
-transform 1 0 5446 0 1 3098
-box -5446 -3098 5446 3098
-use sky130_fd_pr__cap_mim_m3_2_W5U4AW  sky130_fd_pr__cap_mim_m3_2_W5U4AW_0
-timestamp 1606502073
-transform 1 0 7970 0 1 3151
-box -3179 -3101 3201 3101
-use sky130_fd_pr__cap_mim_m3_1_WRT4AW  sky130_fd_pr__cap_mim_m3_1_WRT4AW_0
-timestamp 1606502073
-transform -1 0 7027 0 1 3151
-box -3136 -3100 3136 3100
-<< labels >>
-flabel metal4 s 38 7965 73 8283 0 FreeSans 320 0 0 0 vdd3v3
-port 0 nsew
-flabel metal4 s 38 7255 232 7655 0 FreeSans 320 0 0 0 vss
-port 2 nsew
-flabel metal4 s 10974 7962 11180 8291 0 FreeSans 320 0 0 0 vdd1v8
-port 1 nsew
-flabel metal3 11189 7491 11344 7551 0 FreeSans 320 0 0 0 por_l
-port 4 nsew
-flabel metal3 11188 7856 11343 7916 0 FreeSans 320 0 0 0 porb_l
-port 5 nsew
-flabel metal3 10969 6765 11342 6834 0 FreeSans 320 0 0 0 porb_h
-port 3 nsew
-<< properties >>
-string FIXED_BBOX 0 0 11344 8338
-<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag b/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
deleted file mode 100644
index f3164a4..0000000
--- a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
+++ /dev/null
@@ -1,33 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606502073
-<< metal3 >>
-rect -3136 3072 3136 3100
-rect -3136 -3072 3052 3072
-rect 3116 -3072 3136 3072
-rect -3136 -3100 3136 -3072
-<< via3 >>
-rect 3052 -3072 3116 3072
-<< mimcap >>
-rect -3036 2960 2964 3000
-rect -3036 -2960 2332 2960
-rect 2924 -2960 2964 2960
-rect -3036 -3000 2964 -2960
-<< mimcapcontact >>
-rect 2332 -2960 2924 2960
-<< metal4 >>
-rect 3036 3072 3132 3088
-rect 2331 2960 2925 2961
-rect 2331 -2960 2332 2960
-rect 2924 -2960 2925 2960
-rect 2331 -2961 2925 -2960
-rect 3036 -3072 3052 3072
-rect 3116 -3072 3132 3072
-rect 3036 -3088 3132 -3072
-<< properties >>
-string gencell sky130_fd_pr__cap_mim_m3_1
-string FIXED_BBOX -3136 -3100 3064 3100
-string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov -10
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag b/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
deleted file mode 100644
index 88818f6..0000000
--- a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
+++ /dev/null
@@ -1,33 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606502073
-<< metal4 >>
-rect -3179 3059 3179 3100
-rect -3179 -3059 2923 3059
-rect 3159 -3059 3179 3059
-rect -3179 -3100 3179 -3059
-<< via4 >>
-rect 2923 -3059 3159 3059
-<< mimcap2 >>
-rect -3079 2960 2921 3000
-rect -3079 -2960 -3039 2960
-rect 2289 -2960 2921 2960
-rect -3079 -3000 2921 -2960
-<< mimcap2contact >>
-rect -3039 -2960 2289 2960
-<< metal5 >>
-rect 2881 3059 3201 3101
-rect -3063 2960 2313 2984
-rect -3063 -2960 -3039 2960
-rect 2289 -2960 2313 2960
-rect -3063 -2984 2313 -2960
-rect 2881 -3059 2923 3059
-rect 3159 -3059 3201 3059
-rect 2881 -3101 3201 -3059
-<< properties >>
-string gencell sky130_fd_pr__cap_mim_m3_2
-string FIXED_BBOX -3179 -3100 3021 3100
-string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov +90
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
deleted file mode 100644
index 508a2da..0000000
--- a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
+++ /dev/null
@@ -1,98 +0,0 @@
-magic
-tech $PDK
-timestamp 1606063140
-<< pwell >>
-rect -154 -229 154 229
-<< mvnmos >>
-rect -40 -100 40 100
-<< mvndiff >>
-rect -69 94 -40 100
-rect -69 -94 -63 94
-rect -46 -94 -40 94
-rect -69 -100 -40 -94
-rect 40 94 69 100
-rect 40 -94 46 94
-rect 63 -94 69 94
-rect 40 -100 69 -94
-<< mvndiffc >>
-rect -63 -94 -46 94
-rect 46 -94 63 94
-<< mvpsubdiff >>
-rect -136 205 136 211
-rect -136 188 -82 205
-rect 82 188 136 205
-rect -136 182 136 188
-rect -136 -182 -107 182
-rect 107 157 136 182
-rect 107 -157 113 157
-rect 130 -157 136 157
-rect 107 -182 136 -157
-rect -136 -188 136 -182
-rect -136 -205 -82 -188
-rect 82 -205 136 -188
-rect -136 -211 136 -205
-<< mvpsubdiffcont >>
-rect -82 188 82 205
-rect 113 -157 130 157
-rect -82 -205 82 -188
-<< poly >>
-rect -40 136 40 144
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -40 100 40 119
-rect -40 -119 40 -100
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect -40 -144 40 -136
-<< polycont >>
-rect -32 119 32 136
-rect -32 -136 32 -119
-<< locali >>
-rect -130 188 -82 205
-rect 82 188 130 205
-rect -130 -19 -113 188
-rect 113 157 130 188
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -63 94 -46 102
-rect -63 -102 -46 -94
-rect 46 94 63 102
-rect 46 -102 63 -94
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect 113 -188 130 -157
-rect -130 -205 -82 -188
-rect 82 -205 130 -188
-<< viali >>
-rect -32 119 32 136
-rect -130 -188 -113 -19
-rect -63 -94 -46 94
-rect 46 -94 63 94
-rect -32 -136 32 -119
-<< metal1 >>
-rect -38 136 38 139
-rect -38 119 -32 136
-rect 32 119 38 136
-rect -38 116 38 119
-rect -66 94 -43 100
-rect -133 -19 -110 -13
-rect -133 -188 -130 -19
-rect -113 -188 -110 -19
-rect -66 -94 -63 94
-rect -46 -94 -43 94
-rect -66 -100 -43 -94
-rect 43 94 66 100
-rect 43 -94 46 94
-rect 63 -94 66 94
-rect 43 -100 66 -94
-rect -38 -119 38 -116
-rect -38 -136 -32 -119
-rect 32 -136 38 -119
-rect -38 -139 38 -136
-rect -133 -194 -110 -188
-<< properties >>
-string gencell sky130_fd_pr__nfet_g5v0d10v5
-string FIXED_BBOX -121 -196 121 196
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl +45 viagt 0
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
deleted file mode 100644
index dbb8180..0000000
--- a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
+++ /dev/null
@@ -1,326 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< pwell >>
-rect -962 -458 962 458
-<< mvnmos >>
-rect -734 -200 -574 200
-rect -516 -200 -356 200
-rect -298 -200 -138 200
-rect -80 -200 80 200
-rect 138 -200 298 200
-rect 356 -200 516 200
-rect 574 -200 734 200
-<< mvndiff >>
-rect -792 188 -734 200
-rect -792 -188 -780 188
-rect -746 -188 -734 188
-rect -792 -200 -734 -188
-rect -574 188 -516 200
-rect -574 -188 -562 188
-rect -528 -188 -516 188
-rect -574 -200 -516 -188
-rect -356 188 -298 200
-rect -356 -188 -344 188
-rect -310 -188 -298 188
-rect -356 -200 -298 -188
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-rect 298 188 356 200
-rect 298 -188 310 188
-rect 344 -188 356 188
-rect 298 -200 356 -188
-rect 516 188 574 200
-rect 516 -188 528 188
-rect 562 -188 574 188
-rect 516 -200 574 -188
-rect 734 188 792 200
-rect 734 -188 746 188
-rect 780 -188 792 188
-rect 734 -200 792 -188
-<< mvndiffc >>
-rect -780 -188 -746 188
-rect -562 -188 -528 188
-rect -344 -188 -310 188
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect 310 -188 344 188
-rect 528 -188 562 188
-rect 746 -188 780 188
-<< mvpsubdiff >>
-rect -926 410 926 422
-rect -926 376 -818 410
-rect 818 376 926 410
-rect -926 364 926 376
-rect -926 314 -868 364
-rect -926 -314 -914 314
-rect -880 -314 -868 314
-rect 868 314 926 364
-rect -926 -364 -868 -314
-rect 868 -314 880 314
-rect 914 -314 926 314
-rect 868 -364 926 -314
-rect -926 -376 926 -364
-rect -926 -410 -818 -376
-rect 818 -410 926 -376
-rect -926 -422 926 -410
-<< mvpsubdiffcont >>
-rect -818 376 818 410
-rect -914 -314 -880 314
-rect 880 -314 914 314
-rect -818 -410 818 -376
-<< poly >>
-rect -734 272 -574 288
-rect -734 238 -718 272
-rect -590 238 -574 272
-rect -734 200 -574 238
-rect -516 272 -356 288
-rect -516 238 -500 272
-rect -372 238 -356 272
-rect -516 200 -356 238
-rect -298 272 -138 288
-rect -298 238 -282 272
-rect -154 238 -138 272
-rect -298 200 -138 238
-rect -80 272 80 288
-rect -80 238 -64 272
-rect 64 238 80 272
-rect -80 200 80 238
-rect 138 272 298 288
-rect 138 238 154 272
-rect 282 238 298 272
-rect 138 200 298 238
-rect 356 272 516 288
-rect 356 238 372 272
-rect 500 238 516 272
-rect 356 200 516 238
-rect 574 272 734 288
-rect 574 238 590 272
-rect 718 238 734 272
-rect 574 200 734 238
-rect -734 -238 -574 -200
-rect -734 -272 -718 -238
-rect -590 -272 -574 -238
-rect -734 -288 -574 -272
-rect -516 -238 -356 -200
-rect -516 -272 -500 -238
-rect -372 -272 -356 -238
-rect -516 -288 -356 -272
-rect -298 -238 -138 -200
-rect -298 -272 -282 -238
-rect -154 -272 -138 -238
-rect -298 -288 -138 -272
-rect -80 -238 80 -200
-rect -80 -272 -64 -238
-rect 64 -272 80 -238
-rect -80 -288 80 -272
-rect 138 -238 298 -200
-rect 138 -272 154 -238
-rect 282 -272 298 -238
-rect 138 -288 298 -272
-rect 356 -238 516 -200
-rect 356 -272 372 -238
-rect 500 -272 516 -238
-rect 356 -288 516 -272
-rect 574 -238 734 -200
-rect 574 -272 590 -238
-rect 718 -272 734 -238
-rect 574 -288 734 -272
-<< polycont >>
-rect -718 238 -590 272
-rect -500 238 -372 272
-rect -282 238 -154 272
-rect -64 238 64 272
-rect 154 238 282 272
-rect 372 238 500 272
-rect 590 238 718 272
-rect -718 -272 -590 -238
-rect -500 -272 -372 -238
-rect -282 -272 -154 -238
-rect -64 -272 64 -238
-rect 154 -272 282 -238
-rect 372 -272 500 -238
-rect 590 -272 718 -238
-<< locali >>
-rect -914 376 -818 410
-rect 818 376 914 410
-rect -914 314 -880 376
-rect 880 314 914 376
-rect -734 238 -718 272
-rect -590 238 -574 272
-rect -516 238 -500 272
-rect -372 238 -356 272
-rect -298 238 -282 272
-rect -154 238 -138 272
-rect -80 238 -64 272
-rect 64 238 80 272
-rect 138 238 154 272
-rect 282 238 298 272
-rect 356 238 372 272
-rect 500 238 516 272
-rect 574 238 590 272
-rect 718 238 734 272
-rect -780 188 -746 204
-rect -780 -204 -746 -188
-rect -562 188 -528 204
-rect -562 -204 -528 -188
-rect -344 188 -310 204
-rect -344 -204 -310 -188
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect 310 188 344 204
-rect 310 -204 344 -188
-rect 528 188 562 204
-rect 528 -204 562 -188
-rect 746 188 780 204
-rect 746 -204 780 -188
-rect -734 -272 -718 -238
-rect -590 -272 -574 -238
-rect -516 -272 -500 -238
-rect -372 -272 -356 -238
-rect -298 -272 -282 -238
-rect -154 -272 -138 -238
-rect -80 -272 -64 -238
-rect 64 -272 80 -238
-rect 138 -272 154 -238
-rect 282 -272 298 -238
-rect 356 -272 372 -238
-rect 500 -272 516 -238
-rect 574 -272 590 -238
-rect 718 -272 734 -238
-rect -914 -376 -880 -314
-rect 880 -376 914 -314
-rect -914 -410 -818 -376
-rect 818 -410 914 -376
-<< viali >>
-rect -914 -263 -880 263
-rect -718 238 -590 272
-rect -500 238 -372 272
-rect -282 238 -154 272
-rect -64 238 64 272
-rect 154 238 282 272
-rect 372 238 500 272
-rect 590 238 718 272
-rect -780 21 -746 171
-rect -562 -171 -528 -21
-rect -344 21 -310 171
-rect -126 -171 -92 -21
-rect 92 21 126 171
-rect 310 -171 344 -21
-rect 528 21 562 171
-rect 746 -171 780 -21
-rect -718 -272 -590 -238
-rect -500 -272 -372 -238
-rect -282 -272 -154 -238
-rect -64 -272 64 -238
-rect 154 -272 282 -238
-rect 372 -272 500 -238
-rect 590 -272 718 -238
-<< metal1 >>
-rect -920 263 -874 275
-rect -920 -263 -914 263
-rect -880 -263 -874 263
-rect -730 272 -578 278
-rect -730 238 -718 272
-rect -590 238 -578 272
-rect -730 232 -578 238
-rect -512 272 -360 278
-rect -512 238 -500 272
-rect -372 238 -360 272
-rect -512 232 -360 238
-rect -294 272 -142 278
-rect -294 238 -282 272
-rect -154 238 -142 272
-rect -294 232 -142 238
-rect -76 272 76 278
-rect -76 238 -64 272
-rect 64 238 76 272
-rect -76 232 76 238
-rect 142 272 294 278
-rect 142 238 154 272
-rect 282 238 294 272
-rect 142 232 294 238
-rect 360 272 512 278
-rect 360 238 372 272
-rect 500 238 512 272
-rect 360 232 512 238
-rect 578 272 730 278
-rect 578 238 590 272
-rect 718 238 730 272
-rect 578 232 730 238
-rect -786 171 -740 183
-rect -786 21 -780 171
-rect -746 21 -740 171
-rect -786 9 -740 21
-rect -350 171 -304 183
-rect -350 21 -344 171
-rect -310 21 -304 171
-rect -350 9 -304 21
-rect 86 171 132 183
-rect 86 21 92 171
-rect 126 21 132 171
-rect 86 9 132 21
-rect 522 171 568 183
-rect 522 21 528 171
-rect 562 21 568 171
-rect 522 9 568 21
-rect -568 -21 -522 -9
-rect -568 -171 -562 -21
-rect -528 -171 -522 -21
-rect -568 -183 -522 -171
-rect -132 -21 -86 -9
-rect -132 -171 -126 -21
-rect -92 -171 -86 -21
-rect -132 -183 -86 -171
-rect 304 -21 350 -9
-rect 304 -171 310 -21
-rect 344 -171 350 -21
-rect 304 -183 350 -171
-rect 740 -21 786 -9
-rect 740 -171 746 -21
-rect 780 -171 786 -21
-rect 740 -183 786 -171
-rect -920 -275 -874 -263
-rect -730 -238 -578 -232
-rect -730 -272 -718 -238
-rect -590 -272 -578 -238
-rect -730 -278 -578 -272
-rect -512 -238 -360 -232
-rect -512 -272 -500 -238
-rect -372 -272 -360 -238
-rect -512 -278 -360 -272
-rect -294 -238 -142 -232
-rect -294 -272 -282 -238
-rect -154 -272 -142 -238
-rect -294 -278 -142 -272
-rect -76 -238 76 -232
-rect -76 -272 -64 -238
-rect 64 -272 76 -238
-rect -76 -278 76 -272
-rect 142 -238 294 -232
-rect 142 -272 154 -238
-rect 282 -272 294 -238
-rect 142 -278 294 -272
-rect 360 -238 512 -232
-rect 360 -272 372 -238
-rect 500 -272 512 -238
-rect 360 -278 512 -272
-rect 578 -238 730 -232
-rect 578 -272 590 -238
-rect 718 -272 730 -238
-rect 578 -278 730 -272
-<< properties >>
-string gencell sky130_fd_pr__nfet_g5v0d10v5
-string FIXED_BBOX -897 -393 897 393
-string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc +40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 70 viagt 0
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
deleted file mode 100644
index 64df388..0000000
--- a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
+++ /dev/null
@@ -1,93 +0,0 @@
-magic
-tech $PDK
-timestamp 1605994897
-<< pwell >>
-rect -154 -229 154 229
-<< mvnmos >>
-rect -40 -100 40 100
-<< mvndiff >>
-rect -69 94 -40 100
-rect -69 -94 -63 94
-rect -46 -94 -40 94
-rect -69 -100 -40 -94
-rect 40 94 69 100
-rect 40 -94 46 94
-rect 63 -94 69 94
-rect 40 -100 69 -94
-<< mvndiffc >>
-rect -63 -94 -46 94
-rect 46 -94 63 94
-<< mvpsubdiff >>
-rect -136 205 136 211
-rect -136 188 -82 205
-rect 82 188 136 205
-rect -136 182 136 188
-rect -136 -182 -107 182
-rect 107 157 136 182
-rect 107 -157 113 157
-rect 130 -157 136 157
-rect 107 -182 136 -157
-rect -136 -188 136 -182
-rect -136 -205 -82 -188
-rect 82 -205 136 -188
-rect -136 -211 136 -205
-<< mvpsubdiffcont >>
-rect -82 188 82 205
-rect 113 -157 130 157
-rect -82 -205 82 -188
-<< poly >>
-rect -40 136 40 144
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -40 100 40 119
-rect -40 -119 40 -100
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect -40 -144 40 -136
-<< polycont >>
-rect -32 119 32 136
-rect -32 -136 32 -119
-<< locali >>
-rect -130 188 -82 205
-rect 82 188 130 205
-rect -130 -188 -113 188
-rect 113 157 130 188
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -63 94 -46 102
-rect -63 -102 -46 -94
-rect 46 94 63 102
-rect 46 -102 63 -94
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect 113 -188 130 -157
-rect -130 -205 -82 -188
-rect 82 -205 130 -188
-<< viali >>
-rect -32 119 32 136
-rect -63 -94 -46 94
-rect 46 -94 63 94
-rect -32 -136 32 -119
-<< metal1 >>
-rect -38 136 38 139
-rect -38 119 -32 136
-rect 32 119 38 136
-rect -38 116 38 119
-rect -66 94 -43 100
-rect -66 -94 -63 94
-rect -46 -94 -43 94
-rect -66 -100 -43 -94
-rect 43 94 66 100
-rect 43 -94 46 94
-rect 63 -94 66 94
-rect 43 -100 66 -94
-rect -38 -119 38 -116
-rect -38 -136 -32 -119
-rect 32 -136 38 -119
-rect -38 -139 38 -136
-<< properties >>
-string gencell sky130_fd_pr__nfet_g5v0d10v5
-string FIXED_BBOX -121 -196 121 196
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
deleted file mode 100644
index cda05e3..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
+++ /dev/null
@@ -1,106 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< nwell >>
-rect -338 -497 338 497
-<< mvpmos >>
-rect -80 -200 80 200
-<< mvpdiff >>
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-<< mvpdiffc >>
-rect -126 -188 -92 188
-rect 92 -188 126 188
-<< mvnsubdiff >>
-rect -272 419 272 431
-rect -272 385 -164 419
-rect 164 385 272 419
-rect -272 373 272 385
-rect -272 323 -214 373
-rect -272 -323 -260 323
-rect -226 -323 -214 323
-rect 214 323 272 373
-rect -272 -373 -214 -323
-rect 214 -323 226 323
-rect 260 -323 272 323
-rect 214 -373 272 -323
-rect -272 -385 272 -373
-rect -272 -419 -164 -385
-rect 164 -419 272 -385
-rect -272 -431 272 -419
-<< mvnsubdiffcont >>
-rect -164 385 164 419
-rect -260 -323 -226 323
-rect 226 -323 260 323
-rect -164 -419 164 -385
-<< poly >>
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-<< polycont >>
-rect -64 247 64 281
-rect -64 -281 64 -247
-<< locali >>
-rect -260 385 -181 419
-rect 181 385 260 419
-rect -260 323 -226 385
-rect 226 323 260 385
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -260 -385 -226 -323
-rect 226 -385 260 -323
-rect -260 -419 -164 -385
-rect 164 -419 260 -385
-<< viali >>
-rect -181 385 -164 419
-rect -164 385 164 419
-rect 164 385 181 419
-rect -64 247 64 281
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect -64 -281 64 -247
-<< metal1 >>
-rect -193 419 193 425
-rect -193 385 -181 419
-rect 181 385 193 419
-rect -193 379 193 385
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect -132 188 -86 200
-rect -132 -188 -126 188
-rect -92 -188 -86 188
-rect -132 -200 -86 -188
-rect 86 188 132 200
-rect 86 -188 92 188
-rect 126 -188 132 188
-rect 86 -200 132 -188
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -243 -402 243 402
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
deleted file mode 100644
index 07202c9..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
+++ /dev/null
@@ -1,331 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< nwell >>
-rect -992 -497 992 497
-<< mvpmos >>
-rect -734 -200 -574 200
-rect -516 -200 -356 200
-rect -298 -200 -138 200
-rect -80 -200 80 200
-rect 138 -200 298 200
-rect 356 -200 516 200
-rect 574 -200 734 200
-<< mvpdiff >>
-rect -792 188 -734 200
-rect -792 -188 -780 188
-rect -746 -188 -734 188
-rect -792 -200 -734 -188
-rect -574 188 -516 200
-rect -574 -188 -562 188
-rect -528 -188 -516 188
-rect -574 -200 -516 -188
-rect -356 188 -298 200
-rect -356 -188 -344 188
-rect -310 -188 -298 188
-rect -356 -200 -298 -188
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-rect 298 188 356 200
-rect 298 -188 310 188
-rect 344 -188 356 188
-rect 298 -200 356 -188
-rect 516 188 574 200
-rect 516 -188 528 188
-rect 562 -188 574 188
-rect 516 -200 574 -188
-rect 734 188 792 200
-rect 734 -188 746 188
-rect 780 -188 792 188
-rect 734 -200 792 -188
-<< mvpdiffc >>
-rect -780 -188 -746 188
-rect -562 -188 -528 188
-rect -344 -188 -310 188
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect 310 -188 344 188
-rect 528 -188 562 188
-rect 746 -188 780 188
-<< mvnsubdiff >>
-rect -926 419 926 431
-rect -926 385 -818 419
-rect 818 385 926 419
-rect -926 373 926 385
-rect -926 323 -868 373
-rect -926 -323 -914 323
-rect -880 -323 -868 323
-rect 868 323 926 373
-rect -926 -373 -868 -323
-rect 868 -323 880 323
-rect 914 -323 926 323
-rect 868 -373 926 -323
-rect -926 -385 926 -373
-rect -926 -419 -818 -385
-rect 818 -419 926 -385
-rect -926 -431 926 -419
-<< mvnsubdiffcont >>
-rect -818 385 818 419
-rect -914 -323 -880 323
-rect 880 -323 914 323
-rect -818 -419 818 -385
-<< poly >>
-rect -734 281 -574 297
-rect -734 247 -718 281
-rect -590 247 -574 281
-rect -734 200 -574 247
-rect -516 281 -356 297
-rect -516 247 -500 281
-rect -372 247 -356 281
-rect -516 200 -356 247
-rect -298 281 -138 297
-rect -298 247 -282 281
-rect -154 247 -138 281
-rect -298 200 -138 247
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect 138 281 298 297
-rect 138 247 154 281
-rect 282 247 298 281
-rect 138 200 298 247
-rect 356 281 516 297
-rect 356 247 372 281
-rect 500 247 516 281
-rect 356 200 516 247
-rect 574 281 734 297
-rect 574 247 590 281
-rect 718 247 734 281
-rect 574 200 734 247
-rect -734 -247 -574 -200
-rect -734 -281 -718 -247
-rect -590 -281 -574 -247
-rect -734 -297 -574 -281
-rect -516 -247 -356 -200
-rect -516 -281 -500 -247
-rect -372 -281 -356 -247
-rect -516 -297 -356 -281
-rect -298 -247 -138 -200
-rect -298 -281 -282 -247
-rect -154 -281 -138 -247
-rect -298 -297 -138 -281
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-rect 138 -247 298 -200
-rect 138 -281 154 -247
-rect 282 -281 298 -247
-rect 138 -297 298 -281
-rect 356 -247 516 -200
-rect 356 -281 372 -247
-rect 500 -281 516 -247
-rect 356 -297 516 -281
-rect 574 -247 734 -200
-rect 574 -281 590 -247
-rect 718 -281 734 -247
-rect 574 -297 734 -281
-<< polycont >>
-rect -718 247 -590 281
-rect -500 247 -372 281
-rect -282 247 -154 281
-rect -64 247 64 281
-rect 154 247 282 281
-rect 372 247 500 281
-rect 590 247 718 281
-rect -718 -281 -590 -247
-rect -500 -281 -372 -247
-rect -282 -281 -154 -247
-rect -64 -281 64 -247
-rect 154 -281 282 -247
-rect 372 -281 500 -247
-rect 590 -281 718 -247
-<< locali >>
-rect -914 385 -818 419
-rect 818 385 914 419
-rect 880 323 914 385
-rect -734 247 -718 281
-rect -590 247 -574 281
-rect -516 247 -500 281
-rect -372 247 -356 281
-rect -298 247 -282 281
-rect -154 247 -138 281
-rect -80 247 -64 281
-rect 64 247 80 281
-rect 138 247 154 281
-rect 282 247 298 281
-rect 356 247 372 281
-rect 500 247 516 281
-rect 574 247 590 281
-rect 718 247 734 281
-rect -780 188 -746 204
-rect -780 -204 -746 -188
-rect -562 188 -528 204
-rect -562 -204 -528 -188
-rect -344 188 -310 204
-rect -344 -204 -310 -188
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect 310 188 344 204
-rect 310 -204 344 -188
-rect 528 188 562 204
-rect 528 -204 562 -188
-rect 746 188 780 204
-rect 746 -204 780 -188
-rect -734 -281 -718 -247
-rect -590 -281 -574 -247
-rect -516 -281 -500 -247
-rect -372 -281 -356 -247
-rect -298 -281 -282 -247
-rect -154 -281 -138 -247
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect 138 -281 154 -247
-rect 282 -281 298 -247
-rect 356 -281 372 -247
-rect 500 -281 516 -247
-rect 574 -281 590 -247
-rect 718 -281 734 -247
-rect -914 -385 -880 -323
-rect 880 -385 914 -323
-rect -914 -419 -818 -385
-rect 818 -419 914 -385
-<< viali >>
-rect -792 385 792 419
-rect -914 323 -880 385
-rect -914 38 -880 323
-rect -718 247 -590 281
-rect -500 247 -372 281
-rect -282 247 -154 281
-rect -64 247 64 281
-rect 154 247 282 281
-rect 372 247 500 281
-rect 590 247 718 281
-rect -780 21 -746 171
-rect -562 -171 -528 -21
-rect -344 21 -310 171
-rect -126 -171 -92 -21
-rect 92 21 126 171
-rect 310 -171 344 -21
-rect 528 21 562 171
-rect 746 -171 780 -21
-rect -718 -281 -590 -247
-rect -500 -281 -372 -247
-rect -282 -281 -154 -247
-rect -64 -281 64 -247
-rect 154 -281 282 -247
-rect 372 -281 500 -247
-rect 590 -281 718 -247
-<< metal1 >>
-rect -804 419 804 425
-rect -920 385 -874 397
-rect -920 38 -914 385
-rect -880 38 -874 385
-rect -804 385 -792 419
-rect 792 385 804 419
-rect -804 379 804 385
-rect -730 281 -578 287
-rect -730 247 -718 281
-rect -590 247 -578 281
-rect -730 241 -578 247
-rect -512 281 -360 287
-rect -512 247 -500 281
-rect -372 247 -360 281
-rect -512 241 -360 247
-rect -294 281 -142 287
-rect -294 247 -282 281
-rect -154 247 -142 281
-rect -294 241 -142 247
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect 142 281 294 287
-rect 142 247 154 281
-rect 282 247 294 281
-rect 142 241 294 247
-rect 360 281 512 287
-rect 360 247 372 281
-rect 500 247 512 281
-rect 360 241 512 247
-rect 578 281 730 287
-rect 578 247 590 281
-rect 718 247 730 281
-rect 578 241 730 247
-rect -920 26 -874 38
-rect -786 171 -740 183
-rect -786 21 -780 171
-rect -746 21 -740 171
-rect -786 9 -740 21
-rect -350 171 -304 183
-rect -350 21 -344 171
-rect -310 21 -304 171
-rect -350 9 -304 21
-rect 86 171 132 183
-rect 86 21 92 171
-rect 126 21 132 171
-rect 86 9 132 21
-rect 522 171 568 183
-rect 522 21 528 171
-rect 562 21 568 171
-rect 522 9 568 21
-rect -568 -21 -522 -9
-rect -568 -171 -562 -21
-rect -528 -171 -522 -21
-rect -568 -183 -522 -171
-rect -132 -21 -86 -9
-rect -132 -171 -126 -21
-rect -92 -171 -86 -21
-rect -132 -183 -86 -171
-rect 304 -21 350 -9
-rect 304 -171 310 -21
-rect 344 -171 350 -21
-rect 304 -183 350 -171
-rect 740 -21 786 -9
-rect 740 -171 746 -21
-rect 780 -171 786 -21
-rect 740 -183 786 -171
-rect -730 -247 -578 -241
-rect -730 -281 -718 -247
-rect -590 -281 -578 -247
-rect -730 -287 -578 -281
-rect -512 -247 -360 -241
-rect -512 -281 -500 -247
-rect -372 -281 -360 -247
-rect -512 -287 -360 -281
-rect -294 -247 -142 -241
-rect -294 -281 -282 -247
-rect -154 -281 -142 -247
-rect -294 -287 -142 -281
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-rect 142 -247 294 -241
-rect 142 -281 154 -247
-rect 282 -281 294 -247
-rect 142 -287 294 -281
-rect 360 -247 512 -241
-rect 360 -281 372 -247
-rect 500 -281 512 -247
-rect 360 -287 512 -281
-rect 578 -247 730 -241
-rect 578 -281 590 -247
-rect 718 -281 730 -247
-rect 578 -287 730 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -897 -402 897 402
-string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
deleted file mode 100644
index ceaf969..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
+++ /dev/null
@@ -1,114 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< error_p >>
-rect -221 351 -220 397
-rect -193 379 -192 419
-<< nwell >>
-rect -338 -497 338 497
-<< mvpmos >>
-rect -80 -200 80 200
-<< mvpdiff >>
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-<< mvpdiffc >>
-rect -126 -188 -92 188
-rect 92 -188 126 188
-<< mvnsubdiff >>
-rect -272 419 272 431
-rect -272 385 -164 419
-rect 164 385 272 419
-rect -272 373 272 385
-rect -272 323 -214 373
-rect -272 -323 -260 323
-rect -226 -323 -214 323
-rect 214 323 272 373
-rect -272 -373 -214 -323
-rect 214 -323 226 323
-rect 260 -323 272 323
-rect 214 -373 272 -323
-rect -272 -385 272 -373
-rect -272 -419 -164 -385
-rect 164 -419 272 -385
-rect -272 -431 272 -419
-<< mvnsubdiffcont >>
-rect -164 385 164 419
-rect -260 -323 -226 323
-rect 226 -323 260 323
-rect -164 -419 164 -385
-<< poly >>
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-<< polycont >>
-rect -64 247 64 281
-rect -64 -281 64 -247
-<< locali >>
-rect -260 385 -181 419
-rect 181 385 260 419
-rect 226 323 260 385
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -260 -385 -226 -323
-rect 226 -385 260 -323
-rect -260 -419 -164 -385
-rect 164 -419 260 -385
-<< viali >>
-rect -181 385 -164 419
-rect -164 385 164 419
-rect 164 385 181 419
-rect -260 323 -226 385
-rect -260 0 -226 323
-rect -64 247 64 281
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect -64 -281 64 -247
-<< metal1 >>
-rect -193 419 193 425
-rect -266 385 -220 397
-rect -266 0 -260 385
-rect -226 0 -220 385
-rect -193 385 -181 419
-rect 181 385 193 419
-rect -193 379 193 385
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect -266 -12 -220 0
-rect -132 188 -86 200
-rect -132 -188 -126 188
-rect -92 -188 -86 188
-rect -132 -200 -86 -188
-rect 86 188 132 200
-rect 86 -188 92 188
-rect 126 -188 132 188
-rect 86 -200 132 -188
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -243 -402 243 402
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
deleted file mode 100644
index 23ef875..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
+++ /dev/null
@@ -1,114 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< error_p >>
-rect -221 351 -220 397
-rect -193 379 -192 419
-<< nwell >>
-rect -338 -497 338 497
-<< mvpmos >>
-rect -80 -200 80 200
-<< mvpdiff >>
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-<< mvpdiffc >>
-rect -126 -188 -92 188
-rect 92 -188 126 188
-<< mvnsubdiff >>
-rect -272 419 272 431
-rect -272 385 -164 419
-rect 164 385 272 419
-rect -272 373 272 385
-rect -272 323 -214 373
-rect -272 -323 -260 323
-rect -226 -323 -214 323
-rect 214 323 272 373
-rect -272 -373 -214 -323
-rect 214 -323 226 323
-rect 260 -323 272 323
-rect 214 -373 272 -323
-rect -272 -385 272 -373
-rect -272 -419 -164 -385
-rect 164 -419 272 -385
-rect -272 -431 272 -419
-<< mvnsubdiffcont >>
-rect -164 385 164 419
-rect -260 -323 -226 323
-rect 226 -323 260 323
-rect -164 -419 164 -385
-<< poly >>
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-<< polycont >>
-rect -64 247 64 281
-rect -64 -281 64 -247
-<< locali >>
-rect -260 385 -181 419
-rect 181 385 260 419
-rect 226 323 260 385
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -260 -385 -226 -323
-rect 226 -385 260 -323
-rect -260 -419 -164 -385
-rect 164 -419 260 -385
-<< viali >>
-rect -181 385 -164 419
-rect -164 385 164 419
-rect 164 385 181 419
-rect -260 323 -226 385
-rect -260 38 -226 323
-rect -64 247 64 281
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect -64 -281 64 -247
-<< metal1 >>
-rect -193 419 193 425
-rect -266 385 -220 397
-rect -266 38 -260 385
-rect -226 38 -220 385
-rect -193 385 -181 419
-rect 181 385 193 419
-rect -193 379 193 385
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect -266 26 -220 38
-rect -132 188 -86 200
-rect -132 -188 -126 188
-rect -92 -188 -86 188
-rect -132 -200 -86 -188
-rect 86 188 132 200
-rect 86 -188 92 188
-rect 126 -188 132 188
-rect 86 -200 132 -188
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -243 -402 243 402
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
deleted file mode 100644
index f094850..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
+++ /dev/null
@@ -1,368 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< nwell >>
-rect -1101 -497 1101 497
-<< mvpmos >>
-rect -843 -200 -683 200
-rect -625 -200 -465 200
-rect -407 -200 -247 200
-rect -189 -200 -29 200
-rect 29 -200 189 200
-rect 247 -200 407 200
-rect 465 -200 625 200
-rect 683 -200 843 200
-<< mvpdiff >>
-rect -901 188 -843 200
-rect -901 -188 -889 188
-rect -855 -188 -843 188
-rect -901 -200 -843 -188
-rect -683 188 -625 200
-rect -683 -188 -671 188
-rect -637 -188 -625 188
-rect -683 -200 -625 -188
-rect -465 188 -407 200
-rect -465 -188 -453 188
-rect -419 -188 -407 188
-rect -465 -200 -407 -188
-rect -247 188 -189 200
-rect -247 -188 -235 188
-rect -201 -188 -189 188
-rect -247 -200 -189 -188
-rect -29 188 29 200
-rect -29 -188 -17 188
-rect 17 -188 29 188
-rect -29 -200 29 -188
-rect 189 188 247 200
-rect 189 -188 201 188
-rect 235 -188 247 188
-rect 189 -200 247 -188
-rect 407 188 465 200
-rect 407 -188 419 188
-rect 453 -188 465 188
-rect 407 -200 465 -188
-rect 625 188 683 200
-rect 625 -188 637 188
-rect 671 -188 683 188
-rect 625 -200 683 -188
-rect 843 188 901 200
-rect 843 -188 855 188
-rect 889 -188 901 188
-rect 843 -200 901 -188
-<< mvpdiffc >>
-rect -889 -188 -855 188
-rect -671 -188 -637 188
-rect -453 -188 -419 188
-rect -235 -188 -201 188
-rect -17 -188 17 188
-rect 201 -188 235 188
-rect 419 -188 453 188
-rect 637 -188 671 188
-rect 855 -188 889 188
-<< mvnsubdiff >>
-rect -1035 419 1035 431
-rect -1035 385 -927 419
-rect 927 385 1035 419
-rect -1035 373 1035 385
-rect -1035 323 -977 373
-rect -1035 -323 -1023 323
-rect -989 -323 -977 323
-rect 977 323 1035 373
-rect -1035 -373 -977 -323
-rect 977 -323 989 323
-rect 1023 -323 1035 323
-rect 977 -373 1035 -323
-rect -1035 -385 1035 -373
-rect -1035 -419 -927 -385
-rect 927 -419 1035 -385
-rect -1035 -431 1035 -419
-<< mvnsubdiffcont >>
-rect -927 385 927 419
-rect -1023 -323 -989 323
-rect 989 -323 1023 323
-rect -927 -419 927 -385
-<< poly >>
-rect -843 281 -683 297
-rect -843 247 -827 281
-rect -699 247 -683 281
-rect -843 200 -683 247
-rect -625 281 -465 297
-rect -625 247 -609 281
-rect -481 247 -465 281
-rect -625 200 -465 247
-rect -407 281 -247 297
-rect -407 247 -391 281
-rect -263 247 -247 281
-rect -407 200 -247 247
-rect -189 281 -29 297
-rect -189 247 -173 281
-rect -45 247 -29 281
-rect -189 200 -29 247
-rect 29 281 189 297
-rect 29 247 45 281
-rect 173 247 189 281
-rect 29 200 189 247
-rect 247 281 407 297
-rect 247 247 263 281
-rect 391 247 407 281
-rect 247 200 407 247
-rect 465 281 625 297
-rect 465 247 481 281
-rect 609 247 625 281
-rect 465 200 625 247
-rect 683 281 843 297
-rect 683 247 699 281
-rect 827 247 843 281
-rect 683 200 843 247
-rect -843 -247 -683 -200
-rect -843 -281 -827 -247
-rect -699 -281 -683 -247
-rect -843 -297 -683 -281
-rect -625 -247 -465 -200
-rect -625 -281 -609 -247
-rect -481 -281 -465 -247
-rect -625 -297 -465 -281
-rect -407 -247 -247 -200
-rect -407 -281 -391 -247
-rect -263 -281 -247 -247
-rect -407 -297 -247 -281
-rect -189 -247 -29 -200
-rect -189 -281 -173 -247
-rect -45 -281 -29 -247
-rect -189 -297 -29 -281
-rect 29 -247 189 -200
-rect 29 -281 45 -247
-rect 173 -281 189 -247
-rect 29 -297 189 -281
-rect 247 -247 407 -200
-rect 247 -281 263 -247
-rect 391 -281 407 -247
-rect 247 -297 407 -281
-rect 465 -247 625 -200
-rect 465 -281 481 -247
-rect 609 -281 625 -247
-rect 465 -297 625 -281
-rect 683 -247 843 -200
-rect 683 -281 699 -247
-rect 827 -281 843 -247
-rect 683 -297 843 -281
-<< polycont >>
-rect -827 247 -699 281
-rect -609 247 -481 281
-rect -391 247 -263 281
-rect -173 247 -45 281
-rect 45 247 173 281
-rect 263 247 391 281
-rect 481 247 609 281
-rect 699 247 827 281
-rect -827 -281 -699 -247
-rect -609 -281 -481 -247
-rect -391 -281 -263 -247
-rect -173 -281 -45 -247
-rect 45 -281 173 -247
-rect 263 -281 391 -247
-rect 481 -281 609 -247
-rect 699 -281 827 -247
-<< locali >>
-rect -1023 385 -927 419
-rect 927 385 1023 419
-rect 989 323 1023 385
-rect -843 247 -827 281
-rect -699 247 -683 281
-rect -625 247 -609 281
-rect -481 247 -465 281
-rect -407 247 -391 281
-rect -263 247 -247 281
-rect -189 247 -173 281
-rect -45 247 -29 281
-rect 29 247 45 281
-rect 173 247 189 281
-rect 247 247 263 281
-rect 391 247 407 281
-rect 465 247 481 281
-rect 609 247 625 281
-rect 683 247 699 281
-rect 827 247 843 281
-rect -889 188 -855 204
-rect -889 -204 -855 -188
-rect -671 188 -637 204
-rect -671 -204 -637 -188
-rect -453 188 -419 204
-rect -453 -204 -419 -188
-rect -235 188 -201 204
-rect -235 -204 -201 -188
-rect -17 188 17 204
-rect -17 -204 17 -188
-rect 201 188 235 204
-rect 201 -204 235 -188
-rect 419 188 453 204
-rect 419 -204 453 -188
-rect 637 188 671 204
-rect 637 -204 671 -188
-rect 855 188 889 204
-rect 855 -204 889 -188
-rect -843 -281 -827 -247
-rect -699 -281 -683 -247
-rect -625 -281 -609 -247
-rect -481 -281 -465 -247
-rect -407 -281 -391 -247
-rect -263 -281 -247 -247
-rect -189 -281 -173 -247
-rect -45 -281 -29 -247
-rect 29 -281 45 -247
-rect 173 -281 189 -247
-rect 247 -281 263 -247
-rect 391 -281 407 -247
-rect 465 -281 481 -247
-rect 609 -281 625 -247
-rect 683 -281 699 -247
-rect 827 -281 843 -247
-rect -1023 -385 -989 -323
-rect 989 -385 1023 -323
-rect -1023 -419 -927 -385
-rect 927 -419 1023 -385
-<< viali >>
-rect -890 385 890 419
-rect -1023 323 -989 385
-rect -1023 0 -989 323
-rect -827 247 -699 281
-rect -609 247 -481 281
-rect -391 247 -263 281
-rect -173 247 -45 281
-rect 45 247 173 281
-rect 263 247 391 281
-rect 481 247 609 281
-rect 699 247 827 281
-rect -889 21 -855 171
-rect -671 -171 -637 -21
-rect -453 21 -419 171
-rect -235 -171 -201 -21
-rect -17 21 17 171
-rect 201 -171 235 -21
-rect 419 21 453 171
-rect 637 -171 671 -21
-rect 855 21 889 171
-rect -827 -281 -699 -247
-rect -609 -281 -481 -247
-rect -391 -281 -263 -247
-rect -173 -281 -45 -247
-rect 45 -281 173 -247
-rect 263 -281 391 -247
-rect 481 -281 609 -247
-rect 699 -281 827 -247
-<< metal1 >>
-rect -902 419 902 425
-rect -1029 385 -983 397
-rect -1029 0 -1023 385
-rect -989 0 -983 385
-rect -902 385 -890 419
-rect 890 385 902 419
-rect -902 379 902 385
-rect -839 281 -687 287
-rect -839 247 -827 281
-rect -699 247 -687 281
-rect -839 241 -687 247
-rect -621 281 -469 287
-rect -621 247 -609 281
-rect -481 247 -469 281
-rect -621 241 -469 247
-rect -403 281 -251 287
-rect -403 247 -391 281
-rect -263 247 -251 281
-rect -403 241 -251 247
-rect -185 281 -33 287
-rect -185 247 -173 281
-rect -45 247 -33 281
-rect -185 241 -33 247
-rect 33 281 185 287
-rect 33 247 45 281
-rect 173 247 185 281
-rect 33 241 185 247
-rect 251 281 403 287
-rect 251 247 263 281
-rect 391 247 403 281
-rect 251 241 403 247
-rect 469 281 621 287
-rect 469 247 481 281
-rect 609 247 621 281
-rect 469 241 621 247
-rect 687 281 839 287
-rect 687 247 699 281
-rect 827 247 839 281
-rect 687 241 839 247
-rect -895 171 -849 183
-rect -895 21 -889 171
-rect -855 21 -849 171
-rect -895 9 -849 21
-rect -459 171 -413 183
-rect -459 21 -453 171
-rect -419 21 -413 171
-rect -459 9 -413 21
-rect -23 171 23 183
-rect -23 21 -17 171
-rect 17 21 23 171
-rect -23 9 23 21
-rect 413 171 459 183
-rect 413 21 419 171
-rect 453 21 459 171
-rect 413 9 459 21
-rect 849 171 895 183
-rect 849 21 855 171
-rect 889 21 895 171
-rect 849 9 895 21
-rect -1029 -12 -983 0
-rect -677 -21 -631 -9
-rect -677 -171 -671 -21
-rect -637 -171 -631 -21
-rect -677 -183 -631 -171
-rect -241 -21 -195 -9
-rect -241 -171 -235 -21
-rect -201 -171 -195 -21
-rect -241 -183 -195 -171
-rect 195 -21 241 -9
-rect 195 -171 201 -21
-rect 235 -171 241 -21
-rect 195 -183 241 -171
-rect 631 -21 677 -9
-rect 631 -171 637 -21
-rect 671 -171 677 -21
-rect 631 -183 677 -171
-rect -839 -247 -687 -241
-rect -839 -281 -827 -247
-rect -699 -281 -687 -247
-rect -839 -287 -687 -281
-rect -621 -247 -469 -241
-rect -621 -281 -609 -247
-rect -481 -281 -469 -247
-rect -621 -287 -469 -281
-rect -403 -247 -251 -241
-rect -403 -281 -391 -247
-rect -263 -281 -251 -247
-rect -403 -287 -251 -281
-rect -185 -247 -33 -241
-rect -185 -281 -173 -247
-rect -45 -281 -33 -247
-rect -185 -287 -33 -281
-rect 33 -247 185 -241
-rect 33 -281 45 -247
-rect 173 -281 185 -247
-rect 33 -287 185 -281
-rect 251 -247 403 -241
-rect 251 -281 263 -247
-rect 391 -281 403 -247
-rect 251 -287 403 -281
-rect 469 -247 621 -241
-rect 469 -281 481 -247
-rect 609 -281 621 -247
-rect 469 -287 621 -281
-rect 687 -247 839 -241
-rect 687 -281 699 -247
-rect 827 -281 839 -247
-rect 687 -287 839 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -1006 -402 1006 402
-string parameters w 2.00 l 0.80 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40
-string library sky130
-<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag b/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
deleted file mode 100644
index dbaae87..0000000
--- a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
+++ /dev/null
@@ -1,167 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606074388
-<< pwell >>
-rect -5446 -3098 5446 3098
-<< psubdiff >>
-rect -5410 3028 -5314 3062
-rect 5314 3028 5410 3062
-rect -5410 2966 -5376 3028
-rect 5376 2966 5410 3028
-rect -5410 -3028 -5376 -2966
-rect 5376 -3028 5410 -2966
-rect -5410 -3062 -5314 -3028
-rect 5314 -3062 5410 -3028
-<< psubdiffcont >>
-rect -5314 3028 5314 3062
-rect -5410 -2966 -5376 2966
-rect 5376 -2966 5410 2966
-rect -5314 -3062 5314 -3028
-<< xpolycontact >>
-rect -5280 2500 -5142 2932
-rect -5280 -2932 -5142 -2500
-rect -4894 2500 -4756 2932
-rect -4894 -2932 -4756 -2500
-rect -4508 2500 -4370 2932
-rect -4508 -2932 -4370 -2500
-rect -4122 2500 -3984 2932
-rect -4122 -2932 -3984 -2500
-rect -3736 2500 -3598 2932
-rect -3736 -2932 -3598 -2500
-rect -3350 2500 -3212 2932
-rect -3350 -2932 -3212 -2500
-rect -2964 2500 -2826 2932
-rect -2964 -2932 -2826 -2500
-rect -2578 2500 -2440 2932
-rect -2578 -2932 -2440 -2500
-rect -2192 2500 -2054 2932
-rect -2192 -2932 -2054 -2500
-rect -1806 2500 -1668 2932
-rect -1806 -2932 -1668 -2500
-rect -1420 2500 -1282 2932
-rect -1420 -2932 -1282 -2500
-rect -1034 2500 -896 2932
-rect -1034 -2932 -896 -2500
-rect -648 2500 -510 2932
-rect -648 -2932 -510 -2500
-rect -262 2500 -124 2932
-rect -262 -2932 -124 -2500
-rect 124 2500 262 2932
-rect 124 -2932 262 -2500
-rect 510 2500 648 2932
-rect 510 -2932 648 -2500
-rect 896 2500 1034 2932
-rect 896 -2932 1034 -2500
-rect 1282 2500 1420 2932
-rect 1282 -2932 1420 -2500
-rect 1668 2500 1806 2932
-rect 1668 -2932 1806 -2500
-rect 2054 2500 2192 2932
-rect 2054 -2932 2192 -2500
-rect 2440 2500 2578 2932
-rect 2440 -2932 2578 -2500
-rect 2826 2500 2964 2932
-rect 2826 -2932 2964 -2500
-rect 3212 2500 3350 2932
-rect 3212 -2932 3350 -2500
-rect 3598 2500 3736 2932
-rect 3598 -2932 3736 -2500
-rect 3984 2500 4122 2932
-rect 3984 -2932 4122 -2500
-rect 4370 2500 4508 2932
-rect 4370 -2932 4508 -2500
-rect 4756 2500 4894 2932
-rect 4756 -2932 4894 -2500
-rect 5142 2500 5280 2932
-rect 5142 -2932 5280 -2500
-<< xpolyres >>
-rect -5280 -2500 -5142 2500
-rect -4894 -2500 -4756 2500
-rect -4508 -2500 -4370 2500
-rect -4122 -2500 -3984 2500
-rect -3736 -2500 -3598 2500
-rect -3350 -2500 -3212 2500
-rect -2964 -2500 -2826 2500
-rect -2578 -2500 -2440 2500
-rect -2192 -2500 -2054 2500
-rect -1806 -2500 -1668 2500
-rect -1420 -2500 -1282 2500
-rect -1034 -2500 -896 2500
-rect -648 -2500 -510 2500
-rect -262 -2500 -124 2500
-rect 124 -2500 262 2500
-rect 510 -2500 648 2500
-rect 896 -2500 1034 2500
-rect 1282 -2500 1420 2500
-rect 1668 -2500 1806 2500
-rect 2054 -2500 2192 2500
-rect 2440 -2500 2578 2500
-rect 2826 -2500 2964 2500
-rect 3212 -2500 3350 2500
-rect 3598 -2500 3736 2500
-rect 3984 -2500 4122 2500
-rect 4370 -2500 4508 2500
-rect 4756 -2500 4894 2500
-rect 5142 -2500 5280 2500
-<< locali >>
-rect -5410 3028 -5314 3062
-rect 5314 3028 5410 3062
-rect -5410 2966 -5376 3028
-rect 5376 2966 5410 3028
-rect -5410 -3028 -5376 -2966
-rect 5376 -3028 5410 -2966
-rect -5410 -3062 -5314 -3028
-rect 5314 -3062 5410 -3028
-<< viali >>
-rect -5410 -2725 -5376 2725
-rect 5376 -2725 5410 2725
-rect -4838 -3062 4838 -3028
-<< metal1 >>
-rect -5416 2725 -5370 2737
-rect -5416 -2725 -5410 2725
-rect -5376 -2725 -5370 2725
-rect -5416 -2737 -5370 -2725
-rect 5370 2725 5416 2737
-rect 5370 -2725 5376 2725
-rect 5410 -2725 5416 2725
-rect 5370 -2737 5416 -2725
-rect -4850 -3028 4850 -3022
-rect -4850 -3062 -4838 -3028
-rect 4838 -3062 4850 -3028
-rect -4850 -3068 4850 -3062
-<< res0p69 >>
-rect -5282 -2502 -5140 2502
-rect -4896 -2502 -4754 2502
-rect -4510 -2502 -4368 2502
-rect -4124 -2502 -3982 2502
-rect -3738 -2502 -3596 2502
-rect -3352 -2502 -3210 2502
-rect -2966 -2502 -2824 2502
-rect -2580 -2502 -2438 2502
-rect -2194 -2502 -2052 2502
-rect -1808 -2502 -1666 2502
-rect -1422 -2502 -1280 2502
-rect -1036 -2502 -894 2502
-rect -650 -2502 -508 2502
-rect -264 -2502 -122 2502
-rect 122 -2502 264 2502
-rect 508 -2502 650 2502
-rect 894 -2502 1036 2502
-rect 1280 -2502 1422 2502
-rect 1666 -2502 1808 2502
-rect 2052 -2502 2194 2502
-rect 2438 -2502 2580 2502
-rect 2824 -2502 2966 2502
-rect 3210 -2502 3352 2502
-rect 3596 -2502 3738 2502
-rect 3982 -2502 4124 2502
-rect 4368 -2502 4510 2502
-rect 4754 -2502 4896 2502
-rect 5140 -2502 5282 2502
-<< properties >>
-string gencell sky130_fd_pr__res_xhigh_po_0p69
-string FIXED_BBOX -5393 -3045 5393 3045
-string parameters w 0.69 l 25.0 m 1 nx 28 wmin 0.690 lmin 0.50 rho 2000 val 72.811k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.690 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35  sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41  sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 0 viagb 90 viagt 0 viagl 90 viagr 90
-string library sky130
-<< end >>
diff --git a/mag/user_analog_proj_example.mag b/mag/user_analog_proj_example.mag
deleted file mode 100644
index fcac6f8..0000000
--- a/mag/user_analog_proj_example.mag
+++ /dev/null
@@ -1,18 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1639841760
-<< error_p >>
-rect 5036 7870 5051 7898
-rect 5008 7676 5023 7870
-rect 20366 7862 20381 7890
-rect 20394 7668 20409 7862
-use example_por  example_por_1
-timestamp 1639841760
-transform 1 0 14132 0 1 -22
-box 0 0 11344 8338
-use example_por  example_por_0
-timestamp 1639841760
-transform -1 0 11285 0 1 -14
-box 0 0 11344 8338
-<< end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
deleted file mode 100644
index f1198f1..0000000
--- a/mag/user_analog_project_wrapper.mag
+++ /dev/null
@@ -1,2362 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1639841760
-<< mvpsubdiff >>
-rect 345740 628255 345764 629032
-rect 371078 628255 371102 629032
-<< mvpsubdiffcont >>
-rect 345764 628255 371078 629032
-<< locali >>
-rect 345748 628255 345764 629032
-rect 371078 628255 371094 629032
-<< viali >>
-rect 357593 628300 359298 629000
-<< metal1 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
-<< via1 >>
-rect 357538 629000 359388 629399
-rect 357538 628300 357593 629000
-rect 357593 628300 359298 629000
-rect 359298 628300 359388 629000
-rect 357538 628057 359388 628300
-<< metal2 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
-rect 524 -800 636 480
-rect 1706 -800 1818 480
-rect 2888 -800 3000 480
-rect 4070 -800 4182 480
-rect 5252 -800 5364 480
-rect 6434 -800 6546 480
-rect 7616 -800 7728 480
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-rect 232196 -800 232308 480
-rect 233378 -800 233490 480
-rect 234560 -800 234672 480
-rect 235742 -800 235854 480
-rect 236924 -800 237036 480
-rect 238106 -800 238218 480
-rect 239288 -800 239400 480
-rect 240470 -800 240582 480
-rect 241652 -800 241764 480
-rect 242834 -800 242946 480
-rect 244016 -800 244128 480
-rect 245198 -800 245310 480
-rect 246380 -800 246492 480
-rect 247562 -800 247674 480
-rect 248744 -800 248856 480
-rect 249926 -800 250038 480
-rect 251108 -800 251220 480
-rect 252290 -800 252402 480
-rect 253472 -800 253584 480
-rect 254654 -800 254766 480
-rect 255836 -800 255948 480
-rect 257018 -800 257130 480
-rect 258200 -800 258312 480
-rect 259382 -800 259494 480
-rect 260564 -800 260676 480
-rect 261746 -800 261858 480
-rect 262928 -800 263040 480
-rect 264110 -800 264222 480
-rect 265292 -800 265404 480
-rect 266474 -800 266586 480
-rect 267656 -800 267768 480
-rect 268838 -800 268950 480
-rect 270020 -800 270132 480
-rect 271202 -800 271314 480
-rect 272384 -800 272496 480
-rect 273566 -800 273678 480
-rect 274748 -800 274860 480
-rect 275930 -800 276042 480
-rect 277112 -800 277224 480
-rect 278294 -800 278406 480
-rect 279476 -800 279588 480
-rect 280658 -800 280770 480
-rect 281840 -800 281952 480
-rect 283022 -800 283134 480
-rect 284204 -800 284316 480
-rect 285386 -800 285498 480
-rect 286568 -800 286680 480
-rect 287750 -800 287862 480
-rect 288932 -800 289044 480
-rect 290114 -800 290226 480
-rect 291296 -800 291408 480
-rect 292478 -800 292590 480
-rect 293660 -800 293772 480
-rect 294842 -800 294954 480
-rect 296024 -800 296136 480
-rect 297206 -800 297318 480
-rect 298388 -800 298500 480
-rect 299570 -800 299682 480
-rect 300752 -800 300864 480
-rect 301934 -800 302046 480
-rect 303116 -800 303228 480
-rect 304298 -800 304410 480
-rect 305480 -800 305592 480
-rect 306662 -800 306774 480
-rect 307844 -800 307956 480
-rect 309026 -800 309138 480
-rect 310208 -800 310320 480
-rect 311390 -800 311502 480
-rect 312572 -800 312684 480
-rect 313754 -800 313866 480
-rect 314936 -800 315048 480
-rect 316118 -800 316230 480
-rect 317300 -800 317412 480
-rect 318482 -800 318594 480
-rect 319664 -800 319776 480
-rect 320846 -800 320958 480
-rect 322028 -800 322140 480
-rect 323210 -800 323322 480
-rect 324392 -800 324504 480
-rect 325574 -800 325686 480
-rect 326756 -800 326868 480
-rect 327938 -800 328050 480
-rect 329120 -800 329232 480
-rect 330302 -800 330414 480
-rect 331484 -800 331596 480
-rect 332666 -800 332778 480
-rect 333848 -800 333960 480
-rect 335030 -800 335142 480
-rect 336212 -800 336324 480
-rect 337394 -800 337506 480
-rect 338576 -800 338688 480
-rect 339758 -800 339870 480
-rect 340940 -800 341052 480
-rect 342122 -800 342234 480
-rect 343304 -800 343416 480
-rect 344486 -800 344598 480
-rect 345668 -800 345780 480
-rect 346850 -800 346962 480
-rect 348032 -800 348144 480
-rect 349214 -800 349326 480
-rect 350396 -800 350508 480
-rect 351578 -800 351690 480
-rect 352760 -800 352872 480
-rect 353942 -800 354054 480
-rect 355124 -800 355236 480
-rect 356306 -800 356418 480
-rect 357488 -800 357600 480
-rect 358670 -800 358782 480
-rect 359852 -800 359964 480
-rect 361034 -800 361146 480
-rect 362216 -800 362328 480
-rect 363398 -800 363510 480
-rect 364580 -800 364692 480
-rect 365762 -800 365874 480
-rect 366944 -800 367056 480
-rect 368126 -800 368238 480
-rect 369308 -800 369420 480
-rect 370490 -800 370602 480
-rect 371672 -800 371784 480
-rect 372854 -800 372966 480
-rect 374036 -800 374148 480
-rect 375218 -800 375330 480
-rect 376400 -800 376512 480
-rect 377582 -800 377694 480
-rect 378764 -800 378876 480
-rect 379946 -800 380058 480
-rect 381128 -800 381240 480
-rect 382310 -800 382422 480
-rect 383492 -800 383604 480
-rect 384674 -800 384786 480
-rect 385856 -800 385968 480
-rect 387038 -800 387150 480
-rect 388220 -800 388332 480
-rect 389402 -800 389514 480
-rect 390584 -800 390696 480
-rect 391766 -800 391878 480
-rect 392948 -800 393060 480
-rect 394130 -800 394242 480
-rect 395312 -800 395424 480
-rect 396494 -800 396606 480
-rect 397676 -800 397788 480
-rect 398858 -800 398970 480
-rect 400040 -800 400152 480
-rect 401222 -800 401334 480
-rect 402404 -800 402516 480
-rect 403586 -800 403698 480
-rect 404768 -800 404880 480
-rect 405950 -800 406062 480
-rect 407132 -800 407244 480
-rect 408314 -800 408426 480
-rect 409496 -800 409608 480
-rect 410678 -800 410790 480
-rect 411860 -800 411972 480
-rect 413042 -800 413154 480
-rect 414224 -800 414336 480
-rect 415406 -800 415518 480
-rect 416588 -800 416700 480
-rect 417770 -800 417882 480
-rect 418952 -800 419064 480
-rect 420134 -800 420246 480
-rect 421316 -800 421428 480
-rect 422498 -800 422610 480
-rect 423680 -800 423792 480
-rect 424862 -800 424974 480
-rect 426044 -800 426156 480
-rect 427226 -800 427338 480
-rect 428408 -800 428520 480
-rect 429590 -800 429702 480
-rect 430772 -800 430884 480
-rect 431954 -800 432066 480
-rect 433136 -800 433248 480
-rect 434318 -800 434430 480
-rect 435500 -800 435612 480
-rect 436682 -800 436794 480
-rect 437864 -800 437976 480
-rect 439046 -800 439158 480
-rect 440228 -800 440340 480
-rect 441410 -800 441522 480
-rect 442592 -800 442704 480
-rect 443774 -800 443886 480
-rect 444956 -800 445068 480
-rect 446138 -800 446250 480
-rect 447320 -800 447432 480
-rect 448502 -800 448614 480
-rect 449684 -800 449796 480
-rect 450866 -800 450978 480
-rect 452048 -800 452160 480
-rect 453230 -800 453342 480
-rect 454412 -800 454524 480
-rect 455594 -800 455706 480
-rect 456776 -800 456888 480
-rect 457958 -800 458070 480
-rect 459140 -800 459252 480
-rect 460322 -800 460434 480
-rect 461504 -800 461616 480
-rect 462686 -800 462798 480
-rect 463868 -800 463980 480
-rect 465050 -800 465162 480
-rect 466232 -800 466344 480
-rect 467414 -800 467526 480
-rect 468596 -800 468708 480
-rect 469778 -800 469890 480
-rect 470960 -800 471072 480
-rect 472142 -800 472254 480
-rect 473324 -800 473436 480
-rect 474506 -800 474618 480
-rect 475688 -800 475800 480
-rect 476870 -800 476982 480
-rect 478052 -800 478164 480
-rect 479234 -800 479346 480
-rect 480416 -800 480528 480
-rect 481598 -800 481710 480
-rect 482780 -800 482892 480
-rect 483962 -800 484074 480
-rect 485144 -800 485256 480
-rect 486326 -800 486438 480
-rect 487508 -800 487620 480
-rect 488690 -800 488802 480
-rect 489872 -800 489984 480
-rect 491054 -800 491166 480
-rect 492236 -800 492348 480
-rect 493418 -800 493530 480
-rect 494600 -800 494712 480
-rect 495782 -800 495894 480
-rect 496964 -800 497076 480
-rect 498146 -800 498258 480
-rect 499328 -800 499440 480
-rect 500510 -800 500622 480
-rect 501692 -800 501804 480
-rect 502874 -800 502986 480
-rect 504056 -800 504168 480
-rect 505238 -800 505350 480
-rect 506420 -800 506532 480
-rect 507602 -800 507714 480
-rect 508784 -800 508896 480
-rect 509966 -800 510078 480
-rect 511148 -800 511260 480
-rect 512330 -800 512442 480
-rect 513512 -800 513624 480
-rect 514694 -800 514806 480
-rect 515876 -800 515988 480
-rect 517058 -800 517170 480
-rect 518240 -800 518352 480
-rect 519422 -800 519534 480
-rect 520604 -800 520716 480
-rect 521786 -800 521898 480
-rect 522968 -800 523080 480
-rect 524150 -800 524262 480
-rect 525332 -800 525444 480
-rect 526514 -800 526626 480
-rect 527696 -800 527808 480
-rect 528878 -800 528990 480
-rect 530060 -800 530172 480
-rect 531242 -800 531354 480
-rect 532424 -800 532536 480
-rect 533606 -800 533718 480
-rect 534788 -800 534900 480
-rect 535970 -800 536082 480
-rect 537152 -800 537264 480
-rect 538334 -800 538446 480
-rect 539516 -800 539628 480
-rect 540698 -800 540810 480
-rect 541880 -800 541992 480
-rect 543062 -800 543174 480
-rect 544244 -800 544356 480
-rect 545426 -800 545538 480
-rect 546608 -800 546720 480
-rect 547790 -800 547902 480
-rect 548972 -800 549084 480
-rect 550154 -800 550266 480
-rect 551336 -800 551448 480
-rect 552518 -800 552630 480
-rect 553700 -800 553812 480
-rect 554882 -800 554994 480
-rect 556064 -800 556176 480
-rect 557246 -800 557358 480
-rect 558428 -800 558540 480
-rect 559610 -800 559722 480
-rect 560792 -800 560904 480
-rect 561974 -800 562086 480
-rect 563156 -800 563268 480
-rect 564338 -800 564450 480
-rect 565520 -800 565632 480
-rect 566702 -800 566814 480
-rect 567884 -800 567996 480
-rect 569066 -800 569178 480
-rect 570248 -800 570360 480
-rect 571430 -800 571542 480
-rect 572612 -800 572724 480
-rect 573794 -800 573906 480
-rect 574976 -800 575088 480
-rect 576158 -800 576270 480
-rect 577340 -800 577452 480
-rect 578522 -800 578634 480
-rect 579704 -800 579816 480
-rect 580886 -800 580998 480
-rect 582068 -800 582180 480
-rect 583250 -800 583362 480
-<< via2 >>
-rect 357538 628057 359388 629399
-<< metal3 >>
-rect 16194 702300 21194 704800
-rect 68194 702300 73194 704800
-rect 120194 702300 125194 704800
-rect 165594 702300 170594 704800
-rect 170894 700788 173094 704800
-rect 170894 690603 173094 700738
-rect -800 680242 1700 685242
-rect 170894 683764 173094 684327
-rect 173394 700786 175594 704800
-rect 175894 702300 180894 704800
-rect 217294 702300 222294 704800
-rect 173394 690603 175594 700736
-rect 173394 683764 175594 684327
-rect 222594 700836 224794 704800
-rect 222594 690636 224794 700786
-rect 222594 683913 224794 684360
-rect 225094 700846 227294 704800
-rect 227594 702300 232594 704800
-rect 225094 690636 227294 700796
-rect 225094 683913 227294 684360
-rect 318994 649497 323994 704800
-rect 324294 701130 326494 704800
-rect 324294 690618 326494 701080
-rect 326794 701150 328994 704800
-rect 326794 694292 328994 701100
-rect 329294 694292 334294 704800
-rect 413394 702300 418394 704800
-rect 465394 702300 470394 704800
-rect 326794 692092 334294 694292
-rect 324294 684038 326494 684344
-rect -800 643842 1660 648642
-rect 318994 642983 323994 643740
-rect 329294 649497 334294 692092
-rect 329294 642983 334294 643740
-rect 510594 690564 515394 704800
-rect -800 633842 1660 638642
-rect 510594 637598 515394 684332
-rect 510594 631116 515394 631780
-rect 520594 690564 525394 704800
-rect 566594 702300 571594 704800
-rect 520594 637598 525394 684332
-rect 582300 677984 584800 682984
-rect 560050 639784 560566 644584
-rect 566742 639784 584800 644584
-rect 520594 631116 525394 631780
-rect 560050 629784 560566 634584
-rect 566742 629784 584800 634584
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
-rect 339960 620294 345660 620363
-rect 371099 620302 533609 620371
-rect -800 559442 1660 564242
-rect -800 549442 1660 554242
-rect 339960 511642 340072 620294
-rect 341733 619574 341739 619684
-rect 341849 619637 341855 619684
-rect 533089 619645 533095 619647
-rect 341849 619577 345660 619637
-rect 371099 619585 533095 619645
-rect 533089 619583 533095 619585
-rect 533159 619583 533165 619647
-rect 341849 619574 341855 619577
-rect 533105 619280 533111 619282
-rect -800 511530 340072 511642
-rect 340967 619212 345660 619272
-rect 371099 619220 533111 619280
-rect 533105 619218 533111 619220
-rect 533175 619218 533181 619282
-rect -800 510348 480 510460
-rect -800 509166 480 509278
-rect -800 507984 480 508096
-rect -800 506802 480 506914
-rect -800 505620 480 505732
-rect -800 468308 480 468420
-rect -800 467126 480 467238
-rect -800 465944 480 466056
-rect -800 464762 480 464874
-rect 340967 463692 341079 619212
-rect -800 463580 341079 463692
-rect 341738 618632 341850 618638
-rect -800 462398 660 462510
-rect 780 462398 13894 462510
-rect 17564 462398 17711 462510
-rect -800 425086 480 425198
-rect -800 423904 480 424016
-rect -800 422722 480 422834
-rect -800 421540 480 421652
-rect 341738 420470 341850 618520
-rect -800 420358 341850 420470
-rect -800 419176 676 419288
-rect 738 419176 13887 419288
-rect 17599 419176 17694 419288
-rect 533497 405408 533609 620302
-rect 533894 619647 533958 619653
-rect 533958 619585 539606 619645
-rect 533894 619577 533958 619583
-rect 533904 619282 533968 619288
-rect 533968 619220 537488 619280
-rect 533904 619212 533968 619218
-rect 537376 454558 537488 619220
-rect 539494 498980 539606 619585
-rect 583520 589472 584800 589584
-rect 583520 588290 584800 588402
-rect 583520 587108 584800 587220
-rect 583520 585926 584800 586038
-rect 583520 584744 584800 584856
-rect 583520 583562 584800 583674
-rect 555452 550562 556229 555362
-rect 562346 550562 584800 555362
-rect 555452 540562 556229 545362
-rect 562346 540562 584800 545362
-rect 573371 500050 573548 500162
-rect 576743 500050 583220 500162
-rect 583318 500050 584800 500162
-rect 539494 498868 584800 498980
-rect 583520 497686 584800 497798
-rect 583520 496504 584800 496616
-rect 583520 495322 584800 495434
-rect 583520 494140 584800 494252
-rect 573405 455628 573556 455740
-rect 576731 455628 583180 455740
-rect 583296 455628 584800 455740
-rect 537376 454446 584800 454558
-rect 583520 453264 584800 453376
-rect 583520 452082 584800 452194
-rect 583520 450900 584800 451012
-rect 583520 449718 584800 449830
-rect 583520 411206 584800 411318
-rect 583520 410024 584800 410136
-rect 583520 408842 584800 408954
-rect 583520 407660 584800 407772
-rect 583520 406478 584800 406590
-rect 533497 405296 584800 405408
-rect -800 381864 480 381976
-rect -800 380682 480 380794
-rect -800 379500 480 379612
-rect -800 378318 480 378430
-rect -800 377136 480 377248
-rect -800 375954 480 376066
-rect 583520 364784 584800 364896
-rect 583520 363602 584800 363714
-rect 583520 362420 584800 362532
-rect 583520 361238 584800 361350
-rect 583520 360056 584800 360168
-rect 583520 358874 584800 358986
-rect -800 338642 480 338754
-rect -800 337460 480 337572
-rect -800 336278 480 336390
-rect -800 335096 480 335208
-rect -800 333914 480 334026
-rect -800 332732 480 332844
-rect 583520 319562 584800 319674
-rect 583520 318380 584800 318492
-rect 583520 317198 584800 317310
-rect 583520 316016 584800 316128
-rect 583520 314834 584800 314946
-rect 583520 313652 584800 313764
-rect -800 295420 480 295532
-rect -800 294238 480 294350
-rect -800 293056 480 293168
-rect -800 291874 480 291986
-rect -800 290692 480 290804
-rect -800 289510 480 289622
-rect 583520 275140 584800 275252
-rect 583520 273958 584800 274070
-rect 583520 272776 584800 272888
-rect 583520 271594 584800 271706
-rect 583520 270412 584800 270524
-rect 583520 269230 584800 269342
-rect -800 252398 480 252510
-rect -800 251216 480 251328
-rect -800 250034 480 250146
-rect -800 248852 480 248964
-rect -800 247670 480 247782
-rect -800 246488 480 246600
-rect 582340 235230 584800 240030
-rect 582340 225230 584800 230030
-rect -800 214888 1660 219688
-rect -800 204888 1660 209688
-rect 13406 191430 13991 196230
-rect 17427 191430 573605 196230
-rect 576629 191430 584800 196230
-rect 582340 181430 584800 186230
-rect -800 172888 1660 177688
-rect -800 162888 1660 167688
-rect 582340 146830 584800 151630
-rect 582340 136830 584800 141630
-rect -800 124776 480 124888
-rect -800 123594 480 123706
-rect -800 122412 480 122524
-rect -800 121230 480 121342
-rect -800 120048 480 120160
-rect -800 118866 480 118978
-rect 583520 95118 584800 95230
-rect 583520 93936 584800 94048
-rect 583520 92754 584800 92866
-rect 583520 91572 584800 91684
-rect -800 81554 480 81666
-rect -800 80372 480 80484
-rect -800 79190 480 79302
-rect -800 78008 480 78120
-rect -800 76826 480 76938
-rect -800 75644 480 75756
-rect 583520 50460 584800 50572
-rect 583520 49278 584800 49390
-rect 583520 48096 584800 48208
-rect 583520 46914 584800 47026
-rect -800 38332 480 38444
-rect -800 37150 480 37262
-rect -800 35968 480 36080
-rect -800 34786 480 34898
-rect -800 33604 480 33716
-rect -800 32422 480 32534
-rect 583520 24002 584800 24114
-rect 583520 22820 584800 22932
-rect 583520 21638 584800 21750
-rect 583520 20456 584800 20568
-rect 583520 19274 584800 19386
-rect 583520 18092 584800 18204
-rect -800 16910 480 17022
-rect 583520 16910 584800 17022
-rect -800 15728 480 15840
-rect 583520 15728 584800 15840
-rect -800 14546 480 14658
-rect 583520 14546 584800 14658
-rect -800 13364 480 13476
-rect 583520 13364 584800 13476
-rect -800 12182 480 12294
-rect 583520 12182 584800 12294
-rect -800 11000 480 11112
-rect 583520 11000 584800 11112
-rect -800 9818 480 9930
-rect 583520 9818 584800 9930
-rect -800 8636 480 8748
-rect 583520 8636 584800 8748
-rect -800 7454 480 7566
-rect 583520 7454 584800 7566
-rect -800 6272 480 6384
-rect 583520 6272 584800 6384
-rect -800 5090 480 5202
-rect 583520 5090 584800 5202
-rect -800 3908 480 4020
-rect 583520 3908 584800 4020
-rect -800 2726 480 2838
-rect 583520 2726 584800 2838
-rect -800 1544 480 1656
-rect 583520 1544 584800 1656
-<< rmetal3 >>
-rect 170894 700738 173094 700788
-rect 173394 700736 175594 700786
-rect 222594 700786 224794 700836
-rect 225094 700796 227294 700846
-rect 324294 701080 326494 701130
-rect 326794 701100 328994 701150
-rect 660 462398 780 462510
-rect 676 419176 738 419288
-rect 583220 500050 583318 500162
-rect 583180 455628 583296 455740
-<< via3 >>
-rect 170894 684327 173094 690603
-rect 173394 684327 175594 690603
-rect 222594 684360 224794 690636
-rect 225094 684360 227294 690636
-rect 324294 684344 326494 690618
-rect 318994 643740 323994 649497
-rect 329294 643740 334294 649497
-rect 510594 684332 515394 690564
-rect 510594 631780 515394 637598
-rect 520594 684332 525394 690564
-rect 560566 639784 566742 644584
-rect 520594 631780 525394 637598
-rect 560566 629784 566742 634584
-rect 357538 628057 359388 629399
-rect 341739 619574 341849 619684
-rect 533095 619583 533159 619647
-rect 533111 619218 533175 619282
-rect 341738 618520 341850 618632
-rect 13894 462398 17564 462510
-rect 13887 419176 17599 419288
-rect 533894 619583 533958 619647
-rect 533904 619218 533968 619282
-rect 556229 550562 562346 555362
-rect 556229 540562 562346 545362
-rect 573548 500050 576743 500162
-rect 573556 455628 576731 455740
-rect 13991 191430 17427 196230
-rect 573605 191430 576629 196230
-<< metal4 >>
-rect 165594 702300 170594 704800
-rect 175894 702300 180894 704800
-rect 217294 702300 222294 704800
-rect 227594 702300 232594 704800
-rect 318994 702300 323994 704800
-rect 329294 702300 334294 704800
-rect 170628 690636 526162 690737
-rect 170628 690603 222594 690636
-rect 170628 684327 170894 690603
-rect 173094 684327 173394 690603
-rect 175594 684360 222594 690603
-rect 224794 684360 225094 690636
-rect 227294 690618 526162 690636
-rect 227294 684360 324294 690618
-rect 175594 684344 324294 684360
-rect 326494 690564 526162 690618
-rect 326494 684344 510594 690564
-rect 175594 684332 510594 684344
-rect 515394 684332 520594 690564
-rect 525394 684332 526162 690564
-rect 175594 684327 526162 684332
-rect 170628 684183 526162 684327
-rect 318330 649837 359973 649898
-rect 318330 649497 357559 649837
-rect 318330 643740 318994 649497
-rect 323994 643740 329294 649497
-rect 334294 643740 357559 649497
-rect 318330 643394 357559 643740
-rect 359314 643394 359973 649837
-rect 318330 643344 359973 643394
-rect 560425 644584 566979 644980
-rect 560425 639784 560566 644584
-rect 566742 639784 566979 644584
-rect 356144 637598 525696 637898
-rect 356144 631780 510594 637598
-rect 515394 631780 520594 637598
-rect 525394 631780 525696 637598
-rect 356144 631344 525696 631780
-rect 560425 634584 566979 639784
-rect 357442 629399 359470 631344
-rect 357442 628057 357538 629399
-rect 359388 628057 359470 629399
-rect 357442 619873 359470 628057
-rect 560425 629784 560566 634584
-rect 566742 629784 566979 634584
-rect 341738 619684 341850 619685
-rect 341738 619574 341739 619684
-rect 341849 619574 341850 619684
-rect 341738 618633 341850 619574
-rect 356867 619473 359885 619873
-rect 533094 619647 533160 619648
-rect 533094 619583 533095 619647
-rect 533159 619645 533160 619647
-rect 533893 619647 533959 619648
-rect 533893 619645 533894 619647
-rect 533159 619585 533894 619645
-rect 533159 619583 533160 619585
-rect 533094 619582 533160 619583
-rect 533893 619583 533894 619585
-rect 533958 619583 533959 619647
-rect 533893 619582 533959 619583
-rect 533110 619282 533176 619283
-rect 533110 619218 533111 619282
-rect 533175 619280 533176 619282
-rect 533903 619282 533969 619283
-rect 533903 619280 533904 619282
-rect 533175 619220 533904 619280
-rect 533175 619218 533176 619220
-rect 533110 619217 533176 619218
-rect 533903 619218 533904 619220
-rect 533968 619218 533969 619282
-rect 533903 619217 533969 619218
-rect 341737 618632 341851 618633
-rect 341737 618520 341738 618632
-rect 341850 618520 341851 618632
-rect 341737 618519 341851 618520
-rect 345773 613756 346828 618849
-rect 351928 617829 353757 618856
-rect 351928 615249 352028 617829
-rect 353603 615249 353757 617829
-rect 351928 615131 353757 615249
-rect 363328 617835 365157 618884
-rect 363328 615255 363412 617835
-rect 364987 615255 365157 617835
-rect 363328 615131 365157 615255
-rect 369823 613756 370980 618859
-rect 560425 613756 566979 629784
-rect 345256 607202 566979 613756
-rect 362658 601572 562613 601756
-rect 362658 597231 363414 601572
-rect 364992 597231 562613 601572
-rect 362658 595202 562613 597231
-rect 556059 555362 562613 595202
-rect 556059 550562 556229 555362
-rect 562346 550562 562613 555362
-rect 556059 545362 562613 550562
-rect 556059 540562 556229 545362
-rect 562346 540562 562613 545362
-rect 556059 540155 562613 540562
-rect 573464 500162 576816 500473
-rect 573464 500050 573548 500162
-rect 576743 500050 576816 500162
-rect 13814 462510 17684 462771
-rect 13814 462398 13894 462510
-rect 17564 462398 17684 462510
-rect 13814 419288 17684 462398
-rect 13814 419176 13887 419288
-rect 17599 419176 17684 419288
-rect 13814 227257 17684 419176
-rect 573464 455740 576816 500050
-rect 573464 455628 573556 455740
-rect 576731 455628 576816 455740
-rect 13811 196230 17688 227257
-rect 13811 191430 13991 196230
-rect 17427 191430 17688 196230
-rect 13811 191098 17688 191430
-rect 573464 196230 576816 455628
-rect 573464 191430 573605 196230
-rect 576629 191430 576816 196230
-rect 573464 191191 576816 191430
-<< via4 >>
-rect 357559 643394 359314 649837
-rect 352028 615249 353603 617829
-rect 363412 615255 364987 617835
-rect 363414 597231 364992 601572
-<< metal5 >>
-rect 165594 702300 170594 704800
-rect 175894 702300 180894 704800
-rect 217294 702300 222294 704800
-rect 227594 702300 232594 704800
-rect 318994 702300 323994 704800
-rect 329294 702300 334294 704800
-rect 357521 649837 359350 649991
-rect 357521 643394 357559 649837
-rect 359314 643394 359350 649837
-rect 351918 617829 353747 617929
-rect 351918 615249 352028 617829
-rect 353603 615249 353747 617829
-rect 351918 614900 353747 615249
-rect 357521 614900 359350 643394
-rect 351918 613071 359350 614900
-rect 363318 617835 365147 617929
-rect 363318 615255 363412 617835
-rect 364987 615255 365147 617835
-rect 363318 601572 365147 615255
-rect 363318 597231 363414 601572
-rect 364992 597231 365147 601572
-rect 363318 597052 365147 597231
-<< comment >>
-rect -100 704000 584100 704100
-rect -100 0 0 704000
-rect 584000 0 584100 704000
-rect -100 -100 584100 0
-use user_analog_proj_example  user_analog_proj_example_0
-timestamp 1639841760
-transform 1 0 345668 0 -1 627114
-box -59 -22 25476 8324
-<< labels >>
-flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
-port 0 nsew signal bidirectional
-flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
-port 1 nsew signal bidirectional
-flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
-port 2 nsew signal bidirectional
-flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
-port 3 nsew signal bidirectional
-flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
-port 4 nsew signal bidirectional
-flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
-port 5 nsew signal bidirectional
-flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
-port 6 nsew signal bidirectional
-flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
-port 7 nsew signal bidirectional
-flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
-port 8 nsew signal bidirectional
-flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
-port 9 nsew signal bidirectional
-flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
-port 10 nsew signal bidirectional
-flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
-port 11 nsew signal bidirectional
-flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
-port 12 nsew signal bidirectional
-flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
-port 13 nsew signal bidirectional
-flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
-port 14 nsew signal bidirectional
-flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
-port 15 nsew signal bidirectional
-flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
-port 16 nsew signal bidirectional
-flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
-port 17 nsew signal bidirectional
-flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
-port 18 nsew signal bidirectional
-flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
-port 19 nsew signal bidirectional
-flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
-port 20 nsew signal bidirectional
-flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
-port 21 nsew signal bidirectional
-flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
-port 22 nsew signal bidirectional
-flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
-port 23 nsew signal bidirectional
-flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
-port 24 nsew signal bidirectional
-flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
-port 25 nsew signal bidirectional
-flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
-port 26 nsew signal bidirectional
-flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
-port 27 nsew signal bidirectional
-flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
-port 28 nsew signal bidirectional
-flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
-port 29 nsew signal bidirectional
-flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
-port 30 nsew signal bidirectional
-flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
-port 31 nsew signal bidirectional
-flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
-port 32 nsew signal bidirectional
-flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
-port 33 nsew signal bidirectional
-flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
-port 34 nsew signal bidirectional
-flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
-port 35 nsew signal bidirectional
-flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
-port 36 nsew signal bidirectional
-flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
-port 37 nsew signal bidirectional
-flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
-port 38 nsew signal bidirectional
-flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
-port 39 nsew signal bidirectional
-flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
-port 40 nsew signal bidirectional
-flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
-port 41 nsew signal bidirectional
-flabel metal4 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
-port 41 nsew signal bidirectional
-flabel metal5 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
-port 41 nsew signal bidirectional
-flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 42 nsew signal bidirectional
-flabel metal4 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 42 nsew signal bidirectional
-flabel metal5 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 42 nsew signal bidirectional
-flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
-port 43 nsew signal bidirectional
-flabel metal4 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
-port 43 nsew signal bidirectional
-flabel metal5 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
-port 43 nsew signal bidirectional
-flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
-port 44 nsew signal bidirectional
-flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
-port 45 nsew signal bidirectional
-flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
-port 46 nsew signal bidirectional
-flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
-port 47 nsew signal bidirectional
-flabel metal4 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
-port 47 nsew signal bidirectional
-flabel metal5 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
-port 47 nsew signal bidirectional
-flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 48 nsew signal bidirectional
-flabel metal4 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 48 nsew signal bidirectional
-flabel metal5 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 48 nsew signal bidirectional
-flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
-port 49 nsew signal bidirectional
-flabel metal4 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
-port 49 nsew signal bidirectional
-flabel metal5 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
-port 49 nsew signal bidirectional
-flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
-port 50 nsew signal bidirectional
-flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
-port 51 nsew signal bidirectional
-flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
-port 52 nsew signal bidirectional
-flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
-port 53 nsew signal bidirectional
-flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
-port 54 nsew signal bidirectional
-flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
-port 55 nsew signal bidirectional
-flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
-port 56 nsew signal input
-flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
-port 57 nsew signal input
-flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
-port 58 nsew signal input
-flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
-port 59 nsew signal input
-flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
-port 60 nsew signal input
-flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
-port 61 nsew signal input
-flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
-port 62 nsew signal input
-flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
-port 63 nsew signal input
-flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
-port 64 nsew signal input
-flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
-port 65 nsew signal input
-flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
-port 66 nsew signal input
-flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
-port 67 nsew signal input
-flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
-port 68 nsew signal input
-flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
-port 69 nsew signal input
-flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
-port 70 nsew signal input
-flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
-port 71 nsew signal input
-flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
-port 72 nsew signal input
-flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
-port 73 nsew signal input
-flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
-port 74 nsew signal input
-flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
-port 75 nsew signal input
-flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
-port 76 nsew signal input
-flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
-port 77 nsew signal input
-flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
-port 78 nsew signal input
-flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
-port 79 nsew signal input
-flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
-port 80 nsew signal input
-flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
-port 81 nsew signal input
-flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
-port 82 nsew signal input
-flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
-port 83 nsew signal input
-flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
-port 84 nsew signal input
-flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
-port 85 nsew signal input
-flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
-port 86 nsew signal input
-flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
-port 87 nsew signal input
-flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
-port 88 nsew signal input
-flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
-port 89 nsew signal input
-flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
-port 90 nsew signal input
-flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
-port 91 nsew signal input
-flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
-port 92 nsew signal input
-flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
-port 93 nsew signal input
-flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
-port 94 nsew signal input
-flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
-port 95 nsew signal input
-flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
-port 96 nsew signal input
-flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
-port 97 nsew signal input
-flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
-port 98 nsew signal input
-flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
-port 99 nsew signal input
-flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
-port 100 nsew signal input
-flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
-port 101 nsew signal input
-flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
-port 102 nsew signal input
-flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
-port 103 nsew signal input
-flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
-port 104 nsew signal input
-flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
-port 105 nsew signal input
-flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
-port 106 nsew signal input
-flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
-port 107 nsew signal input
-flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
-port 108 nsew signal input
-flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
-port 109 nsew signal input
-flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
-port 110 nsew signal tristate
-flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
-port 111 nsew signal tristate
-flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
-port 112 nsew signal tristate
-flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
-port 113 nsew signal tristate
-flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
-port 114 nsew signal tristate
-flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
-port 115 nsew signal tristate
-flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
-port 116 nsew signal tristate
-flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
-port 117 nsew signal tristate
-flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
-port 118 nsew signal tristate
-flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
-port 119 nsew signal tristate
-flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
-port 120 nsew signal tristate
-flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
-port 121 nsew signal tristate
-flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
-port 122 nsew signal tristate
-flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
-port 123 nsew signal tristate
-flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
-port 124 nsew signal tristate
-flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
-port 125 nsew signal tristate
-flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
-port 126 nsew signal tristate
-flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
-port 127 nsew signal tristate
-flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
-port 128 nsew signal tristate
-flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
-port 129 nsew signal tristate
-flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
-port 130 nsew signal tristate
-flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
-port 131 nsew signal tristate
-flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
-port 132 nsew signal tristate
-flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
-port 133 nsew signal tristate
-flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
-port 134 nsew signal tristate
-flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
-port 135 nsew signal tristate
-flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
-port 136 nsew signal tristate
-flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
-port 137 nsew signal tristate
-flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
-port 138 nsew signal tristate
-flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
-port 139 nsew signal tristate
-flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
-port 140 nsew signal tristate
-flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
-port 141 nsew signal tristate
-flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
-port 142 nsew signal tristate
-flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
-port 143 nsew signal tristate
-flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
-port 144 nsew signal tristate
-flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
-port 145 nsew signal tristate
-flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
-port 146 nsew signal tristate
-flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
-port 147 nsew signal tristate
-flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
-port 148 nsew signal tristate
-flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
-port 149 nsew signal tristate
-flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
-port 150 nsew signal tristate
-flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
-port 151 nsew signal tristate
-flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
-port 152 nsew signal tristate
-flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
-port 153 nsew signal tristate
-flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
-port 154 nsew signal tristate
-flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
-port 155 nsew signal tristate
-flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
-port 156 nsew signal tristate
-flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
-port 157 nsew signal tristate
-flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
-port 158 nsew signal tristate
-flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
-port 159 nsew signal tristate
-flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
-port 160 nsew signal tristate
-flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
-port 161 nsew signal tristate
-flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
-port 162 nsew signal tristate
-flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
-port 163 nsew signal tristate
-flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
-port 164 nsew signal input
-flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
-port 165 nsew signal input
-flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
-port 166 nsew signal input
-flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
-port 167 nsew signal input
-flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
-port 168 nsew signal input
-flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
-port 169 nsew signal input
-flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
-port 170 nsew signal input
-flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
-port 171 nsew signal input
-flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
-port 172 nsew signal input
-flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
-port 173 nsew signal input
-flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
-port 174 nsew signal input
-flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
-port 175 nsew signal input
-flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
-port 176 nsew signal input
-flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
-port 177 nsew signal input
-flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
-port 178 nsew signal input
-flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
-port 179 nsew signal input
-flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
-port 180 nsew signal input
-flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
-port 181 nsew signal input
-flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
-port 182 nsew signal input
-flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
-port 183 nsew signal input
-flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
-port 184 nsew signal input
-flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
-port 185 nsew signal input
-flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
-port 186 nsew signal input
-flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
-port 187 nsew signal input
-flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
-port 188 nsew signal input
-flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
-port 189 nsew signal input
-flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
-port 190 nsew signal input
-flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
-port 191 nsew signal input
-flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
-port 192 nsew signal input
-flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
-port 193 nsew signal input
-flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
-port 194 nsew signal input
-flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
-port 195 nsew signal input
-flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
-port 196 nsew signal input
-flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
-port 197 nsew signal input
-flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
-port 198 nsew signal input
-flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
-port 199 nsew signal input
-flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
-port 200 nsew signal input
-flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
-port 201 nsew signal input
-flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
-port 202 nsew signal input
-flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
-port 203 nsew signal input
-flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
-port 204 nsew signal input
-flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
-port 205 nsew signal input
-flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
-port 206 nsew signal input
-flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
-port 207 nsew signal input
-flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
-port 208 nsew signal input
-flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
-port 209 nsew signal input
-flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
-port 210 nsew signal input
-flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
-port 211 nsew signal input
-flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
-port 212 nsew signal input
-flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
-port 213 nsew signal input
-flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
-port 214 nsew signal input
-flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
-port 215 nsew signal input
-flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
-port 216 nsew signal input
-flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
-port 217 nsew signal input
-flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
-port 218 nsew signal input
-flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
-port 219 nsew signal input
-flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
-port 220 nsew signal input
-flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
-port 221 nsew signal input
-flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
-port 222 nsew signal input
-flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
-port 223 nsew signal input
-flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
-port 224 nsew signal input
-flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
-port 225 nsew signal input
-flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
-port 226 nsew signal input
-flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
-port 227 nsew signal input
-flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
-port 228 nsew signal input
-flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
-port 229 nsew signal input
-flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
-port 230 nsew signal input
-flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
-port 231 nsew signal input
-flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
-port 232 nsew signal input
-flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
-port 233 nsew signal input
-flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
-port 234 nsew signal input
-flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
-port 235 nsew signal input
-flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
-port 236 nsew signal input
-flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
-port 237 nsew signal input
-flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
-port 238 nsew signal input
-flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
-port 239 nsew signal input
-flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
-port 240 nsew signal input
-flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
-port 241 nsew signal input
-flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
-port 242 nsew signal input
-flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
-port 243 nsew signal input
-flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
-port 244 nsew signal input
-flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
-port 245 nsew signal input
-flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
-port 246 nsew signal input
-flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
-port 247 nsew signal input
-flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
-port 248 nsew signal input
-flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
-port 249 nsew signal input
-flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
-port 250 nsew signal input
-flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
-port 251 nsew signal input
-flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
-port 252 nsew signal input
-flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
-port 253 nsew signal input
-flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
-port 254 nsew signal input
-flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
-port 255 nsew signal input
-flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
-port 256 nsew signal input
-flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
-port 257 nsew signal input
-flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
-port 258 nsew signal input
-flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
-port 259 nsew signal input
-flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
-port 260 nsew signal input
-flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
-port 261 nsew signal input
-flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
-port 262 nsew signal input
-flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
-port 263 nsew signal input
-flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
-port 264 nsew signal input
-flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
-port 265 nsew signal input
-flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
-port 266 nsew signal input
-flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
-port 267 nsew signal input
-flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
-port 268 nsew signal input
-flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
-port 269 nsew signal input
-flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
-port 270 nsew signal input
-flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
-port 271 nsew signal input
-flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
-port 272 nsew signal input
-flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
-port 273 nsew signal input
-flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
-port 274 nsew signal input
-flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
-port 275 nsew signal input
-flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
-port 276 nsew signal input
-flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
-port 277 nsew signal input
-flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
-port 278 nsew signal input
-flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
-port 279 nsew signal input
-flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
-port 280 nsew signal input
-flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
-port 281 nsew signal input
-flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
-port 282 nsew signal input
-flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
-port 283 nsew signal input
-flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
-port 284 nsew signal input
-flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
-port 285 nsew signal input
-flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
-port 286 nsew signal input
-flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
-port 287 nsew signal input
-flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
-port 288 nsew signal input
-flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
-port 289 nsew signal input
-flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
-port 290 nsew signal input
-flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
-port 291 nsew signal input
-flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
-port 292 nsew signal tristate
-flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
-port 293 nsew signal tristate
-flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
-port 294 nsew signal tristate
-flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
-port 295 nsew signal tristate
-flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
-port 296 nsew signal tristate
-flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
-port 297 nsew signal tristate
-flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
-port 298 nsew signal tristate
-flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
-port 299 nsew signal tristate
-flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
-port 300 nsew signal tristate
-flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
-port 301 nsew signal tristate
-flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
-port 302 nsew signal tristate
-flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
-port 303 nsew signal tristate
-flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
-port 304 nsew signal tristate
-flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
-port 305 nsew signal tristate
-flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
-port 306 nsew signal tristate
-flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
-port 307 nsew signal tristate
-flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
-port 308 nsew signal tristate
-flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
-port 309 nsew signal tristate
-flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
-port 310 nsew signal tristate
-flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
-port 311 nsew signal tristate
-flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
-port 312 nsew signal tristate
-flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
-port 313 nsew signal tristate
-flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
-port 314 nsew signal tristate
-flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
-port 315 nsew signal tristate
-flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
-port 316 nsew signal tristate
-flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
-port 317 nsew signal tristate
-flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
-port 318 nsew signal tristate
-flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
-port 319 nsew signal tristate
-flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
-port 320 nsew signal tristate
-flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
-port 321 nsew signal tristate
-flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
-port 322 nsew signal tristate
-flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
-port 323 nsew signal tristate
-flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
-port 324 nsew signal tristate
-flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
-port 325 nsew signal tristate
-flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
-port 326 nsew signal tristate
-flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
-port 327 nsew signal tristate
-flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
-port 328 nsew signal tristate
-flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
-port 329 nsew signal tristate
-flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
-port 330 nsew signal tristate
-flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
-port 331 nsew signal tristate
-flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
-port 332 nsew signal tristate
-flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
-port 333 nsew signal tristate
-flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
-port 334 nsew signal tristate
-flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
-port 335 nsew signal tristate
-flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
-port 336 nsew signal tristate
-flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
-port 337 nsew signal tristate
-flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
-port 338 nsew signal tristate
-flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
-port 339 nsew signal tristate
-flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
-port 340 nsew signal tristate
-flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
-port 341 nsew signal tristate
-flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
-port 342 nsew signal tristate
-flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
-port 343 nsew signal tristate
-flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
-port 344 nsew signal tristate
-flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
-port 345 nsew signal tristate
-flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
-port 346 nsew signal tristate
-flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
-port 347 nsew signal tristate
-flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
-port 348 nsew signal tristate
-flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
-port 349 nsew signal tristate
-flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
-port 350 nsew signal tristate
-flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
-port 351 nsew signal tristate
-flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
-port 352 nsew signal tristate
-flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
-port 353 nsew signal tristate
-flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
-port 354 nsew signal tristate
-flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
-port 355 nsew signal tristate
-flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
-port 356 nsew signal tristate
-flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
-port 357 nsew signal tristate
-flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
-port 358 nsew signal tristate
-flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
-port 359 nsew signal tristate
-flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
-port 360 nsew signal tristate
-flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
-port 361 nsew signal tristate
-flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
-port 362 nsew signal tristate
-flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
-port 363 nsew signal tristate
-flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
-port 364 nsew signal tristate
-flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
-port 365 nsew signal tristate
-flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
-port 366 nsew signal tristate
-flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
-port 367 nsew signal tristate
-flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
-port 368 nsew signal tristate
-flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
-port 369 nsew signal tristate
-flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
-port 370 nsew signal tristate
-flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
-port 371 nsew signal tristate
-flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
-port 372 nsew signal tristate
-flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
-port 373 nsew signal tristate
-flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
-port 374 nsew signal tristate
-flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
-port 375 nsew signal tristate
-flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
-port 376 nsew signal tristate
-flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
-port 377 nsew signal tristate
-flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
-port 378 nsew signal tristate
-flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
-port 379 nsew signal tristate
-flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
-port 380 nsew signal tristate
-flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
-port 381 nsew signal tristate
-flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
-port 382 nsew signal tristate
-flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
-port 383 nsew signal tristate
-flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
-port 384 nsew signal tristate
-flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
-port 385 nsew signal tristate
-flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
-port 386 nsew signal tristate
-flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
-port 387 nsew signal tristate
-flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
-port 388 nsew signal tristate
-flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
-port 389 nsew signal tristate
-flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
-port 390 nsew signal tristate
-flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
-port 391 nsew signal tristate
-flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
-port 392 nsew signal tristate
-flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
-port 393 nsew signal tristate
-flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
-port 394 nsew signal tristate
-flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
-port 395 nsew signal tristate
-flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
-port 396 nsew signal tristate
-flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
-port 397 nsew signal tristate
-flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
-port 398 nsew signal tristate
-flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
-port 399 nsew signal tristate
-flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
-port 400 nsew signal tristate
-flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
-port 401 nsew signal tristate
-flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
-port 402 nsew signal tristate
-flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
-port 403 nsew signal tristate
-flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
-port 404 nsew signal tristate
-flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
-port 405 nsew signal tristate
-flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
-port 406 nsew signal tristate
-flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
-port 407 nsew signal tristate
-flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
-port 408 nsew signal tristate
-flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
-port 409 nsew signal tristate
-flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
-port 410 nsew signal tristate
-flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
-port 411 nsew signal tristate
-flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
-port 412 nsew signal tristate
-flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
-port 413 nsew signal tristate
-flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
-port 414 nsew signal tristate
-flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
-port 415 nsew signal tristate
-flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
-port 416 nsew signal tristate
-flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
-port 417 nsew signal tristate
-flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
-port 418 nsew signal tristate
-flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
-port 419 nsew signal tristate
-flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
-port 420 nsew signal input
-flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
-port 421 nsew signal input
-flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
-port 422 nsew signal input
-flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
-port 423 nsew signal input
-flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
-port 424 nsew signal input
-flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
-port 425 nsew signal input
-flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
-port 426 nsew signal input
-flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
-port 427 nsew signal input
-flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
-port 428 nsew signal input
-flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
-port 429 nsew signal input
-flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
-port 430 nsew signal input
-flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
-port 431 nsew signal input
-flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
-port 432 nsew signal input
-flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
-port 433 nsew signal input
-flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
-port 434 nsew signal input
-flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
-port 435 nsew signal input
-flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
-port 436 nsew signal input
-flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
-port 437 nsew signal input
-flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
-port 438 nsew signal input
-flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
-port 439 nsew signal input
-flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
-port 440 nsew signal input
-flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
-port 441 nsew signal input
-flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
-port 442 nsew signal input
-flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
-port 443 nsew signal input
-flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
-port 444 nsew signal input
-flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
-port 445 nsew signal input
-flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
-port 446 nsew signal input
-flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
-port 447 nsew signal input
-flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
-port 448 nsew signal input
-flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
-port 449 nsew signal input
-flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
-port 450 nsew signal input
-flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
-port 451 nsew signal input
-flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
-port 452 nsew signal input
-flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
-port 453 nsew signal input
-flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
-port 454 nsew signal input
-flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
-port 455 nsew signal input
-flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
-port 456 nsew signal input
-flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
-port 457 nsew signal input
-flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
-port 458 nsew signal input
-flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
-port 459 nsew signal input
-flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
-port 460 nsew signal input
-flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
-port 461 nsew signal input
-flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
-port 462 nsew signal input
-flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
-port 463 nsew signal input
-flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
-port 464 nsew signal input
-flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
-port 465 nsew signal input
-flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
-port 466 nsew signal input
-flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
-port 467 nsew signal input
-flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
-port 468 nsew signal input
-flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
-port 469 nsew signal input
-flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
-port 470 nsew signal input
-flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
-port 471 nsew signal input
-flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
-port 472 nsew signal input
-flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
-port 473 nsew signal input
-flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
-port 474 nsew signal input
-flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
-port 475 nsew signal input
-flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
-port 476 nsew signal input
-flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
-port 477 nsew signal input
-flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
-port 478 nsew signal input
-flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
-port 479 nsew signal input
-flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
-port 480 nsew signal input
-flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
-port 481 nsew signal input
-flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
-port 482 nsew signal input
-flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
-port 483 nsew signal input
-flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
-port 484 nsew signal input
-flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
-port 485 nsew signal input
-flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
-port 486 nsew signal input
-flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
-port 487 nsew signal input
-flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
-port 488 nsew signal input
-flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
-port 489 nsew signal input
-flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
-port 490 nsew signal input
-flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
-port 491 nsew signal input
-flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
-port 492 nsew signal input
-flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
-port 493 nsew signal input
-flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
-port 494 nsew signal input
-flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
-port 495 nsew signal input
-flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
-port 496 nsew signal input
-flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
-port 497 nsew signal input
-flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
-port 498 nsew signal input
-flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
-port 499 nsew signal input
-flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
-port 500 nsew signal input
-flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
-port 501 nsew signal input
-flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
-port 502 nsew signal input
-flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
-port 503 nsew signal input
-flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
-port 504 nsew signal input
-flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
-port 505 nsew signal input
-flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
-port 506 nsew signal input
-flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
-port 507 nsew signal input
-flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
-port 508 nsew signal input
-flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
-port 509 nsew signal input
-flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
-port 510 nsew signal input
-flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
-port 511 nsew signal input
-flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
-port 512 nsew signal input
-flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
-port 513 nsew signal input
-flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
-port 514 nsew signal input
-flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
-port 515 nsew signal input
-flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
-port 516 nsew signal input
-flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
-port 517 nsew signal input
-flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
-port 518 nsew signal input
-flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
-port 519 nsew signal input
-flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
-port 520 nsew signal input
-flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
-port 521 nsew signal input
-flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
-port 522 nsew signal input
-flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
-port 523 nsew signal input
-flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
-port 524 nsew signal input
-flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
-port 525 nsew signal input
-flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
-port 526 nsew signal input
-flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
-port 527 nsew signal input
-flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
-port 528 nsew signal input
-flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
-port 529 nsew signal input
-flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
-port 530 nsew signal input
-flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
-port 531 nsew signal input
-flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
-port 532 nsew signal input
-flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
-port 533 nsew signal input
-flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
-port 534 nsew signal input
-flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
-port 535 nsew signal input
-flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
-port 536 nsew signal input
-flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
-port 537 nsew signal input
-flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
-port 538 nsew signal input
-flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
-port 539 nsew signal input
-flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
-port 540 nsew signal input
-flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
-port 541 nsew signal input
-flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
-port 542 nsew signal input
-flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
-port 543 nsew signal input
-flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
-port 544 nsew signal input
-flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
-port 545 nsew signal input
-flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
-port 546 nsew signal input
-flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
-port 547 nsew signal input
-flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
-port 548 nsew signal input
-flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
-port 549 nsew signal tristate
-flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
-port 550 nsew signal tristate
-flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
-port 551 nsew signal tristate
-flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
-port 552 nsew signal bidirectional
-flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
-port 553 nsew signal bidirectional
-flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
-port 554 nsew signal bidirectional
-flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
-port 555 nsew signal bidirectional
-flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
-port 556 nsew signal bidirectional
-flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
-port 557 nsew signal bidirectional
-flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
-port 558 nsew signal bidirectional
-flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
-port 559 nsew signal bidirectional
-flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
-port 560 nsew signal bidirectional
-flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
-port 561 nsew signal bidirectional
-flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
-port 562 nsew signal bidirectional
-flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
-port 563 nsew signal bidirectional
-flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
-port 564 nsew signal bidirectional
-flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
-port 565 nsew signal bidirectional
-flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
-port 566 nsew signal bidirectional
-flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
-port 567 nsew signal bidirectional
-flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
-port 568 nsew signal bidirectional
-flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
-port 569 nsew signal bidirectional
-flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
-port 570 nsew signal bidirectional
-flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
-port 571 nsew signal bidirectional
-flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
-port 572 nsew signal input
-flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
-port 573 nsew signal input
-flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
-port 574 nsew signal tristate
-flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
-port 575 nsew signal input
-flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
-port 576 nsew signal input
-flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
-port 577 nsew signal input
-flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
-port 578 nsew signal input
-flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
-port 579 nsew signal input
-flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
-port 580 nsew signal input
-flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
-port 581 nsew signal input
-flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
-port 582 nsew signal input
-flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
-port 583 nsew signal input
-flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
-port 584 nsew signal input
-flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
-port 585 nsew signal input
-flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
-port 586 nsew signal input
-flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
-port 587 nsew signal input
-flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
-port 588 nsew signal input
-flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
-port 589 nsew signal input
-flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
-port 590 nsew signal input
-flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
-port 591 nsew signal input
-flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
-port 592 nsew signal input
-flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
-port 593 nsew signal input
-flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
-port 594 nsew signal input
-flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
-port 595 nsew signal input
-flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
-port 596 nsew signal input
-flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
-port 597 nsew signal input
-flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
-port 598 nsew signal input
-flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
-port 599 nsew signal input
-flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
-port 600 nsew signal input
-flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
-port 601 nsew signal input
-flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
-port 602 nsew signal input
-flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
-port 603 nsew signal input
-flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
-port 604 nsew signal input
-flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
-port 605 nsew signal input
-flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
-port 606 nsew signal input
-flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
-port 607 nsew signal input
-flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
-port 608 nsew signal input
-flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
-port 609 nsew signal input
-flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
-port 610 nsew signal input
-flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
-port 611 nsew signal input
-flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
-port 612 nsew signal input
-flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
-port 613 nsew signal input
-flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
-port 614 nsew signal input
-flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
-port 615 nsew signal input
-flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
-port 616 nsew signal input
-flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
-port 617 nsew signal input
-flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
-port 618 nsew signal input
-flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
-port 619 nsew signal input
-flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
-port 620 nsew signal input
-flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
-port 621 nsew signal input
-flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
-port 622 nsew signal input
-flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
-port 623 nsew signal input
-flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
-port 624 nsew signal input
-flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
-port 625 nsew signal input
-flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
-port 626 nsew signal input
-flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
-port 627 nsew signal input
-flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
-port 628 nsew signal input
-flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
-port 629 nsew signal input
-flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
-port 630 nsew signal input
-flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
-port 631 nsew signal input
-flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
-port 632 nsew signal input
-flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
-port 633 nsew signal input
-flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
-port 634 nsew signal input
-flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
-port 635 nsew signal input
-flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
-port 636 nsew signal input
-flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
-port 637 nsew signal input
-flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
-port 638 nsew signal input
-flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
-port 639 nsew signal input
-flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
-port 640 nsew signal tristate
-flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
-port 641 nsew signal tristate
-flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
-port 642 nsew signal tristate
-flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
-port 643 nsew signal tristate
-flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
-port 644 nsew signal tristate
-flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
-port 645 nsew signal tristate
-flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
-port 646 nsew signal tristate
-flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
-port 647 nsew signal tristate
-flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
-port 648 nsew signal tristate
-flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
-port 649 nsew signal tristate
-flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
-port 650 nsew signal tristate
-flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
-port 651 nsew signal tristate
-flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
-port 652 nsew signal tristate
-flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
-port 653 nsew signal tristate
-flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
-port 654 nsew signal tristate
-flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
-port 655 nsew signal tristate
-flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
-port 656 nsew signal tristate
-flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
-port 657 nsew signal tristate
-flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
-port 658 nsew signal tristate
-flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
-port 659 nsew signal tristate
-flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
-port 660 nsew signal tristate
-flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
-port 661 nsew signal tristate
-flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
-port 662 nsew signal tristate
-flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
-port 663 nsew signal tristate
-flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
-port 664 nsew signal tristate
-flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
-port 665 nsew signal tristate
-flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
-port 666 nsew signal tristate
-flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
-port 667 nsew signal tristate
-flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
-port 668 nsew signal tristate
-flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
-port 669 nsew signal tristate
-flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
-port 670 nsew signal tristate
-flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
-port 671 nsew signal tristate
-flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
-port 672 nsew signal input
-flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
-port 673 nsew signal input
-flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
-port 674 nsew signal input
-flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
-port 675 nsew signal input
-flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
-port 676 nsew signal input
-flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
-port 677 nsew signal input
-flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
-flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
-flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
-flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
-<< properties >>
-string FIXED_BBOX 0 0 584000 704000
-<< end >>
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/user_analog_project_wrapper_empty.mag
deleted file mode 100644
index 0dc5bd5..0000000
--- a/mag/user_analog_project_wrapper_empty.mag
+++ /dev/null
@@ -1,2091 +0,0 @@
-magic
-tech $PDK
-timestamp 1632839657
-<< checkpaint >>
-rect -680 351370 292680 352680
-rect -680 630 630 351370
-rect 291370 630 292680 351370
-rect -680 -680 292680 630
-<< metal2 >>
-rect 262 -400 318 240
-rect 853 -400 909 240
-rect 1444 -400 1500 240
-rect 2035 -400 2091 240
-rect 2626 -400 2682 240
-rect 3217 -400 3273 240
-rect 3808 -400 3864 240
-rect 4399 -400 4455 240
-rect 4990 -400 5046 240
-rect 5581 -400 5637 240
-rect 6172 -400 6228 240
-rect 6763 -400 6819 240
-rect 7354 -400 7410 240
-rect 7945 -400 8001 240
-rect 8536 -400 8592 240
-rect 9127 -400 9183 240
-rect 9718 -400 9774 240
-rect 10309 -400 10365 240
-rect 10900 -400 10956 240
-rect 11491 -400 11547 240
-rect 12082 -400 12138 240
-rect 12673 -400 12729 240
-rect 13264 -400 13320 240
-rect 13855 -400 13911 240
-rect 14446 -400 14502 240
-rect 15037 -400 15093 240
-rect 15628 -400 15684 240
-rect 16219 -400 16275 240
-rect 16810 -400 16866 240
-rect 17401 -400 17457 240
-rect 17992 -400 18048 240
-rect 18583 -400 18639 240
-rect 19174 -400 19230 240
-rect 19765 -400 19821 240
-rect 20356 -400 20412 240
-rect 20947 -400 21003 240
-rect 21538 -400 21594 240
-rect 22129 -400 22185 240
-rect 22720 -400 22776 240
-rect 23311 -400 23367 240
-rect 23902 -400 23958 240
-rect 24493 -400 24549 240
-rect 25084 -400 25140 240
-rect 25675 -400 25731 240
-rect 26266 -400 26322 240
-rect 26857 -400 26913 240
-rect 27448 -400 27504 240
-rect 28039 -400 28095 240
-rect 28630 -400 28686 240
-rect 29221 -400 29277 240
-rect 29812 -400 29868 240
-rect 30403 -400 30459 240
-rect 30994 -400 31050 240
-rect 31585 -400 31641 240
-rect 32176 -400 32232 240
-rect 32767 -400 32823 240
-rect 33358 -400 33414 240
-rect 33949 -400 34005 240
-rect 34540 -400 34596 240
-rect 35131 -400 35187 240
-rect 35722 -400 35778 240
-rect 36313 -400 36369 240
-rect 36904 -400 36960 240
-rect 37495 -400 37551 240
-rect 38086 -400 38142 240
-rect 38677 -400 38733 240
-rect 39268 -400 39324 240
-rect 39859 -400 39915 240
-rect 40450 -400 40506 240
-rect 41041 -400 41097 240
-rect 41632 -400 41688 240
-rect 42223 -400 42279 240
-rect 42814 -400 42870 240
-rect 43405 -400 43461 240
-rect 43996 -400 44052 240
-rect 44587 -400 44643 240
-rect 45178 -400 45234 240
-rect 45769 -400 45825 240
-rect 46360 -400 46416 240
-rect 46951 -400 47007 240
-rect 47542 -400 47598 240
-rect 48133 -400 48189 240
-rect 48724 -400 48780 240
-rect 49315 -400 49371 240
-rect 49906 -400 49962 240
-rect 50497 -400 50553 240
-rect 51088 -400 51144 240
-rect 51679 -400 51735 240
-rect 52270 -400 52326 240
-rect 52861 -400 52917 240
-rect 53452 -400 53508 240
-rect 54043 -400 54099 240
-rect 54634 -400 54690 240
-rect 55225 -400 55281 240
-rect 55816 -400 55872 240
-rect 56407 -400 56463 240
-rect 56998 -400 57054 240
-rect 57589 -400 57645 240
-rect 58180 -400 58236 240
-rect 58771 -400 58827 240
-rect 59362 -400 59418 240
-rect 59953 -400 60009 240
-rect 60544 -400 60600 240
-rect 61135 -400 61191 240
-rect 61726 -400 61782 240
-rect 62317 -400 62373 240
-rect 62908 -400 62964 240
-rect 63499 -400 63555 240
-rect 64090 -400 64146 240
-rect 64681 -400 64737 240
-rect 65272 -400 65328 240
-rect 65863 -400 65919 240
-rect 66454 -400 66510 240
-rect 67045 -400 67101 240
-rect 67636 -400 67692 240
-rect 68227 -400 68283 240
-rect 68818 -400 68874 240
-rect 69409 -400 69465 240
-rect 70000 -400 70056 240
-rect 70591 -400 70647 240
-rect 71182 -400 71238 240
-rect 71773 -400 71829 240
-rect 72364 -400 72420 240
-rect 72955 -400 73011 240
-rect 73546 -400 73602 240
-rect 74137 -400 74193 240
-rect 74728 -400 74784 240
-rect 75319 -400 75375 240
-rect 75910 -400 75966 240
-rect 76501 -400 76557 240
-rect 77092 -400 77148 240
-rect 77683 -400 77739 240
-rect 78274 -400 78330 240
-rect 78865 -400 78921 240
-rect 79456 -400 79512 240
-rect 80047 -400 80103 240
-rect 80638 -400 80694 240
-rect 81229 -400 81285 240
-rect 81820 -400 81876 240
-rect 82411 -400 82467 240
-rect 83002 -400 83058 240
-rect 83593 -400 83649 240
-rect 84184 -400 84240 240
-rect 84775 -400 84831 240
-rect 85366 -400 85422 240
-rect 85957 -400 86013 240
-rect 86548 -400 86604 240
-rect 87139 -400 87195 240
-rect 87730 -400 87786 240
-rect 88321 -400 88377 240
-rect 88912 -400 88968 240
-rect 89503 -400 89559 240
-rect 90094 -400 90150 240
-rect 90685 -400 90741 240
-rect 91276 -400 91332 240
-rect 91867 -400 91923 240
-rect 92458 -400 92514 240
-rect 93049 -400 93105 240
-rect 93640 -400 93696 240
-rect 94231 -400 94287 240
-rect 94822 -400 94878 240
-rect 95413 -400 95469 240
-rect 96004 -400 96060 240
-rect 96595 -400 96651 240
-rect 97186 -400 97242 240
-rect 97777 -400 97833 240
-rect 98368 -400 98424 240
-rect 98959 -400 99015 240
-rect 99550 -400 99606 240
-rect 100141 -400 100197 240
-rect 100732 -400 100788 240
-rect 101323 -400 101379 240
-rect 101914 -400 101970 240
-rect 102505 -400 102561 240
-rect 103096 -400 103152 240
-rect 103687 -400 103743 240
-rect 104278 -400 104334 240
-rect 104869 -400 104925 240
-rect 105460 -400 105516 240
-rect 106051 -400 106107 240
-rect 106642 -400 106698 240
-rect 107233 -400 107289 240
-rect 107824 -400 107880 240
-rect 108415 -400 108471 240
-rect 109006 -400 109062 240
-rect 109597 -400 109653 240
-rect 110188 -400 110244 240
-rect 110779 -400 110835 240
-rect 111370 -400 111426 240
-rect 111961 -400 112017 240
-rect 112552 -400 112608 240
-rect 113143 -400 113199 240
-rect 113734 -400 113790 240
-rect 114325 -400 114381 240
-rect 114916 -400 114972 240
-rect 115507 -400 115563 240
-rect 116098 -400 116154 240
-rect 116689 -400 116745 240
-rect 117280 -400 117336 240
-rect 117871 -400 117927 240
-rect 118462 -400 118518 240
-rect 119053 -400 119109 240
-rect 119644 -400 119700 240
-rect 120235 -400 120291 240
-rect 120826 -400 120882 240
-rect 121417 -400 121473 240
-rect 122008 -400 122064 240
-rect 122599 -400 122655 240
-rect 123190 -400 123246 240
-rect 123781 -400 123837 240
-rect 124372 -400 124428 240
-rect 124963 -400 125019 240
-rect 125554 -400 125610 240
-rect 126145 -400 126201 240
-rect 126736 -400 126792 240
-rect 127327 -400 127383 240
-rect 127918 -400 127974 240
-rect 128509 -400 128565 240
-rect 129100 -400 129156 240
-rect 129691 -400 129747 240
-rect 130282 -400 130338 240
-rect 130873 -400 130929 240
-rect 131464 -400 131520 240
-rect 132055 -400 132111 240
-rect 132646 -400 132702 240
-rect 133237 -400 133293 240
-rect 133828 -400 133884 240
-rect 134419 -400 134475 240
-rect 135010 -400 135066 240
-rect 135601 -400 135657 240
-rect 136192 -400 136248 240
-rect 136783 -400 136839 240
-rect 137374 -400 137430 240
-rect 137965 -400 138021 240
-rect 138556 -400 138612 240
-rect 139147 -400 139203 240
-rect 139738 -400 139794 240
-rect 140329 -400 140385 240
-rect 140920 -400 140976 240
-rect 141511 -400 141567 240
-rect 142102 -400 142158 240
-rect 142693 -400 142749 240
-rect 143284 -400 143340 240
-rect 143875 -400 143931 240
-rect 144466 -400 144522 240
-rect 145057 -400 145113 240
-rect 145648 -400 145704 240
-rect 146239 -400 146295 240
-rect 146830 -400 146886 240
-rect 147421 -400 147477 240
-rect 148012 -400 148068 240
-rect 148603 -400 148659 240
-rect 149194 -400 149250 240
-rect 149785 -400 149841 240
-rect 150376 -400 150432 240
-rect 150967 -400 151023 240
-rect 151558 -400 151614 240
-rect 152149 -400 152205 240
-rect 152740 -400 152796 240
-rect 153331 -400 153387 240
-rect 153922 -400 153978 240
-rect 154513 -400 154569 240
-rect 155104 -400 155160 240
-rect 155695 -400 155751 240
-rect 156286 -400 156342 240
-rect 156877 -400 156933 240
-rect 157468 -400 157524 240
-rect 158059 -400 158115 240
-rect 158650 -400 158706 240
-rect 159241 -400 159297 240
-rect 159832 -400 159888 240
-rect 160423 -400 160479 240
-rect 161014 -400 161070 240
-rect 161605 -400 161661 240
-rect 162196 -400 162252 240
-rect 162787 -400 162843 240
-rect 163378 -400 163434 240
-rect 163969 -400 164025 240
-rect 164560 -400 164616 240
-rect 165151 -400 165207 240
-rect 165742 -400 165798 240
-rect 166333 -400 166389 240
-rect 166924 -400 166980 240
-rect 167515 -400 167571 240
-rect 168106 -400 168162 240
-rect 168697 -400 168753 240
-rect 169288 -400 169344 240
-rect 169879 -400 169935 240
-rect 170470 -400 170526 240
-rect 171061 -400 171117 240
-rect 171652 -400 171708 240
-rect 172243 -400 172299 240
-rect 172834 -400 172890 240
-rect 173425 -400 173481 240
-rect 174016 -400 174072 240
-rect 174607 -400 174663 240
-rect 175198 -400 175254 240
-rect 175789 -400 175845 240
-rect 176380 -400 176436 240
-rect 176971 -400 177027 240
-rect 177562 -400 177618 240
-rect 178153 -400 178209 240
-rect 178744 -400 178800 240
-rect 179335 -400 179391 240
-rect 179926 -400 179982 240
-rect 180517 -400 180573 240
-rect 181108 -400 181164 240
-rect 181699 -400 181755 240
-rect 182290 -400 182346 240
-rect 182881 -400 182937 240
-rect 183472 -400 183528 240
-rect 184063 -400 184119 240
-rect 184654 -400 184710 240
-rect 185245 -400 185301 240
-rect 185836 -400 185892 240
-rect 186427 -400 186483 240
-rect 187018 -400 187074 240
-rect 187609 -400 187665 240
-rect 188200 -400 188256 240
-rect 188791 -400 188847 240
-rect 189382 -400 189438 240
-rect 189973 -400 190029 240
-rect 190564 -400 190620 240
-rect 191155 -400 191211 240
-rect 191746 -400 191802 240
-rect 192337 -400 192393 240
-rect 192928 -400 192984 240
-rect 193519 -400 193575 240
-rect 194110 -400 194166 240
-rect 194701 -400 194757 240
-rect 195292 -400 195348 240
-rect 195883 -400 195939 240
-rect 196474 -400 196530 240
-rect 197065 -400 197121 240
-rect 197656 -400 197712 240
-rect 198247 -400 198303 240
-rect 198838 -400 198894 240
-rect 199429 -400 199485 240
-rect 200020 -400 200076 240
-rect 200611 -400 200667 240
-rect 201202 -400 201258 240
-rect 201793 -400 201849 240
-rect 202384 -400 202440 240
-rect 202975 -400 203031 240
-rect 203566 -400 203622 240
-rect 204157 -400 204213 240
-rect 204748 -400 204804 240
-rect 205339 -400 205395 240
-rect 205930 -400 205986 240
-rect 206521 -400 206577 240
-rect 207112 -400 207168 240
-rect 207703 -400 207759 240
-rect 208294 -400 208350 240
-rect 208885 -400 208941 240
-rect 209476 -400 209532 240
-rect 210067 -400 210123 240
-rect 210658 -400 210714 240
-rect 211249 -400 211305 240
-rect 211840 -400 211896 240
-rect 212431 -400 212487 240
-rect 213022 -400 213078 240
-rect 213613 -400 213669 240
-rect 214204 -400 214260 240
-rect 214795 -400 214851 240
-rect 215386 -400 215442 240
-rect 215977 -400 216033 240
-rect 216568 -400 216624 240
-rect 217159 -400 217215 240
-rect 217750 -400 217806 240
-rect 218341 -400 218397 240
-rect 218932 -400 218988 240
-rect 219523 -400 219579 240
-rect 220114 -400 220170 240
-rect 220705 -400 220761 240
-rect 221296 -400 221352 240
-rect 221887 -400 221943 240
-rect 222478 -400 222534 240
-rect 223069 -400 223125 240
-rect 223660 -400 223716 240
-rect 224251 -400 224307 240
-rect 224842 -400 224898 240
-rect 225433 -400 225489 240
-rect 226024 -400 226080 240
-rect 226615 -400 226671 240
-rect 227206 -400 227262 240
-rect 227797 -400 227853 240
-rect 228388 -400 228444 240
-rect 228979 -400 229035 240
-rect 229570 -400 229626 240
-rect 230161 -400 230217 240
-rect 230752 -400 230808 240
-rect 231343 -400 231399 240
-rect 231934 -400 231990 240
-rect 232525 -400 232581 240
-rect 233116 -400 233172 240
-rect 233707 -400 233763 240
-rect 234298 -400 234354 240
-rect 234889 -400 234945 240
-rect 235480 -400 235536 240
-rect 236071 -400 236127 240
-rect 236662 -400 236718 240
-rect 237253 -400 237309 240
-rect 237844 -400 237900 240
-rect 238435 -400 238491 240
-rect 239026 -400 239082 240
-rect 239617 -400 239673 240
-rect 240208 -400 240264 240
-rect 240799 -400 240855 240
-rect 241390 -400 241446 240
-rect 241981 -400 242037 240
-rect 242572 -400 242628 240
-rect 243163 -400 243219 240
-rect 243754 -400 243810 240
-rect 244345 -400 244401 240
-rect 244936 -400 244992 240
-rect 245527 -400 245583 240
-rect 246118 -400 246174 240
-rect 246709 -400 246765 240
-rect 247300 -400 247356 240
-rect 247891 -400 247947 240
-rect 248482 -400 248538 240
-rect 249073 -400 249129 240
-rect 249664 -400 249720 240
-rect 250255 -400 250311 240
-rect 250846 -400 250902 240
-rect 251437 -400 251493 240
-rect 252028 -400 252084 240
-rect 252619 -400 252675 240
-rect 253210 -400 253266 240
-rect 253801 -400 253857 240
-rect 254392 -400 254448 240
-rect 254983 -400 255039 240
-rect 255574 -400 255630 240
-rect 256165 -400 256221 240
-rect 256756 -400 256812 240
-rect 257347 -400 257403 240
-rect 257938 -400 257994 240
-rect 258529 -400 258585 240
-rect 259120 -400 259176 240
-rect 259711 -400 259767 240
-rect 260302 -400 260358 240
-rect 260893 -400 260949 240
-rect 261484 -400 261540 240
-rect 262075 -400 262131 240
-rect 262666 -400 262722 240
-rect 263257 -400 263313 240
-rect 263848 -400 263904 240
-rect 264439 -400 264495 240
-rect 265030 -400 265086 240
-rect 265621 -400 265677 240
-rect 266212 -400 266268 240
-rect 266803 -400 266859 240
-rect 267394 -400 267450 240
-rect 267985 -400 268041 240
-rect 268576 -400 268632 240
-rect 269167 -400 269223 240
-rect 269758 -400 269814 240
-rect 270349 -400 270405 240
-rect 270940 -400 270996 240
-rect 271531 -400 271587 240
-rect 272122 -400 272178 240
-rect 272713 -400 272769 240
-rect 273304 -400 273360 240
-rect 273895 -400 273951 240
-rect 274486 -400 274542 240
-rect 275077 -400 275133 240
-rect 275668 -400 275724 240
-rect 276259 -400 276315 240
-rect 276850 -400 276906 240
-rect 277441 -400 277497 240
-rect 278032 -400 278088 240
-rect 278623 -400 278679 240
-rect 279214 -400 279270 240
-rect 279805 -400 279861 240
-rect 280396 -400 280452 240
-rect 280987 -400 281043 240
-rect 281578 -400 281634 240
-rect 282169 -400 282225 240
-rect 282760 -400 282816 240
-rect 283351 -400 283407 240
-rect 283942 -400 283998 240
-rect 284533 -400 284589 240
-rect 285124 -400 285180 240
-rect 285715 -400 285771 240
-rect 286306 -400 286362 240
-rect 286897 -400 286953 240
-rect 287488 -400 287544 240
-rect 288079 -400 288135 240
-rect 288670 -400 288726 240
-rect 289261 -400 289317 240
-rect 289852 -400 289908 240
-rect 290443 -400 290499 240
-rect 291034 -400 291090 240
-rect 291625 -400 291681 240
-<< metal3 >>
-rect 8097 351150 10597 352400
-rect 34097 351150 36597 352400
-rect 60097 351150 62597 352400
-rect 82797 351150 85297 352400
-rect 85447 351150 86547 352400
-rect 86697 351150 87797 352400
-rect 87947 351150 90447 352400
-rect 108647 351150 111147 352400
-rect 111297 351150 112397 352400
-rect 112547 351150 113647 352400
-rect 113797 351150 116297 352400
-rect 159497 351150 161997 352400
-rect 162147 351150 163247 352400
-rect 163397 351150 164497 352400
-rect 164647 351150 167147 352400
-rect 206697 351150 209197 352400
-rect 232697 351150 235197 352400
-rect 255297 351170 257697 352400
-rect 260297 351170 262697 352400
-rect 283297 351150 285797 352400
-rect -400 340121 850 342621
-rect 291150 338992 292400 341492
-rect -400 321921 830 324321
-rect 291170 319892 292400 322292
-rect -400 316921 830 319321
-rect 291170 314892 292400 317292
-rect 291760 294736 292400 294792
-rect 291760 294145 292400 294201
-rect 291760 293554 292400 293610
-rect 291760 292963 292400 293019
-rect 291760 292372 292400 292428
-rect 291760 291781 292400 291837
-rect -400 279721 830 282121
-rect -400 274721 830 277121
-rect 291170 275281 292400 277681
-rect 291170 270281 292400 272681
-rect -400 255765 240 255821
-rect -400 255174 240 255230
-rect -400 254583 240 254639
-rect -400 253992 240 254048
-rect -400 253401 240 253457
-rect -400 252810 240 252866
-rect 291760 250025 292400 250081
-rect 291760 249434 292400 249490
-rect 291760 248843 292400 248899
-rect 291760 248252 292400 248308
-rect 291760 247661 292400 247717
-rect 291760 247070 292400 247126
-rect -400 234154 240 234210
-rect -400 233563 240 233619
-rect -400 232972 240 233028
-rect -400 232381 240 232437
-rect -400 231790 240 231846
-rect -400 231199 240 231255
-rect 291760 227814 292400 227870
-rect 291760 227223 292400 227279
-rect 291760 226632 292400 226688
-rect 291760 226041 292400 226097
-rect 291760 225450 292400 225506
-rect 291760 224859 292400 224915
-rect -400 212543 240 212599
-rect -400 211952 240 212008
-rect -400 211361 240 211417
-rect -400 210770 240 210826
-rect -400 210179 240 210235
-rect -400 209588 240 209644
-rect 291760 205603 292400 205659
-rect 291760 205012 292400 205068
-rect 291760 204421 292400 204477
-rect 291760 203830 292400 203886
-rect 291760 203239 292400 203295
-rect 291760 202648 292400 202704
-rect -400 190932 240 190988
-rect -400 190341 240 190397
-rect -400 189750 240 189806
-rect -400 189159 240 189215
-rect -400 188568 240 188624
-rect -400 187977 240 188033
-rect 291760 182392 292400 182448
-rect 291760 181801 292400 181857
-rect 291760 181210 292400 181266
-rect 291760 180619 292400 180675
-rect 291760 180028 292400 180084
-rect 291760 179437 292400 179493
-rect -400 169321 240 169377
-rect -400 168730 240 168786
-rect -400 168139 240 168195
-rect -400 167548 240 167604
-rect -400 166957 240 167013
-rect -400 166366 240 166422
-rect 291760 159781 292400 159837
-rect 291760 159190 292400 159246
-rect 291760 158599 292400 158655
-rect 291760 158008 292400 158064
-rect 291760 157417 292400 157473
-rect 291760 156826 292400 156882
-rect -400 147710 240 147766
-rect -400 147119 240 147175
-rect -400 146528 240 146584
-rect -400 145937 240 145993
-rect -400 145346 240 145402
-rect -400 144755 240 144811
-rect 291760 137570 292400 137626
-rect 291760 136979 292400 137035
-rect 291760 136388 292400 136444
-rect 291760 135797 292400 135853
-rect 291760 135206 292400 135262
-rect 291760 134615 292400 134671
-rect -400 126199 240 126255
-rect -400 125608 240 125664
-rect -400 125017 240 125073
-rect -400 124426 240 124482
-rect -400 123835 240 123891
-rect -400 123244 240 123300
-rect 291170 117615 292400 120015
-rect 291170 112615 292400 115015
-rect -400 107444 830 109844
-rect -400 102444 830 104844
-rect 291170 95715 292400 98115
-rect 291170 90715 292400 93115
-rect -400 86444 830 88844
-rect -400 81444 830 83844
-rect 291170 73415 292400 75815
-rect 291170 68415 292400 70815
-rect -400 62388 240 62444
-rect -400 61797 240 61853
-rect -400 61206 240 61262
-rect -400 60615 240 60671
-rect -400 60024 240 60080
-rect -400 59433 240 59489
-rect 291760 47559 292400 47615
-rect 291760 46968 292400 47024
-rect 291760 46377 292400 46433
-rect 291760 45786 292400 45842
-rect -400 40777 240 40833
-rect -400 40186 240 40242
-rect -400 39595 240 39651
-rect -400 39004 240 39060
-rect -400 38413 240 38469
-rect -400 37822 240 37878
-rect 291760 25230 292400 25286
-rect 291760 24639 292400 24695
-rect 291760 24048 292400 24104
-rect 291760 23457 292400 23513
-rect -400 19166 240 19222
-rect -400 18575 240 18631
-rect -400 17984 240 18040
-rect -400 17393 240 17449
-rect -400 16802 240 16858
-rect -400 16211 240 16267
-rect 291760 12001 292400 12057
-rect 291760 11410 292400 11466
-rect 291760 10819 292400 10875
-rect 291760 10228 292400 10284
-rect 291760 9637 292400 9693
-rect 291760 9046 292400 9102
-rect -400 8455 240 8511
-rect 291760 8455 292400 8511
-rect -400 7864 240 7920
-rect 291760 7864 292400 7920
-rect -400 7273 240 7329
-rect 291760 7273 292400 7329
-rect -400 6682 240 6738
-rect 291760 6682 292400 6738
-rect -400 6091 240 6147
-rect 291760 6091 292400 6147
-rect -400 5500 240 5556
-rect 291760 5500 292400 5556
-rect -400 4909 240 4965
-rect 291760 4909 292400 4965
-rect -400 4318 240 4374
-rect 291760 4318 292400 4374
-rect -400 3727 240 3783
-rect 291760 3727 292400 3783
-rect -400 3136 240 3192
-rect 291760 3136 292400 3192
-rect -400 2545 240 2601
-rect 291760 2545 292400 2601
-rect -400 1954 240 2010
-rect 291760 1954 292400 2010
-rect -400 1363 240 1419
-rect 291760 1363 292400 1419
-rect -400 772 240 828
-rect 291760 772 292400 828
-<< metal4 >>
-rect 82797 351150 85297 352400
-rect 87947 351150 90447 352400
-rect 108647 351150 111147 352400
-rect 113797 351150 116297 352400
-rect 159497 351150 161997 352400
-rect 164647 351150 167147 352400
-<< metal5 >>
-rect 82797 351150 85297 352400
-rect 87947 351150 90447 352400
-rect 108647 351150 111147 352400
-rect 113797 351150 116297 352400
-rect 159497 351150 161997 352400
-rect 164647 351150 167147 352400
-<< comment >>
-rect -50 352000 292050 352050
-rect -50 0 0 352000
-rect 292000 0 292050 352000
-rect -50 -50 292050 0
-<< labels >>
-flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
-port 0 nsew signal bidirectional
-flabel metal3 s -400 190932 240 190988 0 FreeSans 560 0 0 0 gpio_analog[10]
-port 1 nsew signal bidirectional
-flabel metal3 s -400 169321 240 169377 0 FreeSans 560 0 0 0 gpio_analog[11]
-port 2 nsew signal bidirectional
-flabel metal3 s -400 147710 240 147766 0 FreeSans 560 0 0 0 gpio_analog[12]
-port 3 nsew signal bidirectional
-flabel metal3 s -400 126199 240 126255 0 FreeSans 560 0 0 0 gpio_analog[13]
-port 4 nsew signal bidirectional
-flabel metal3 s -400 62388 240 62444 0 FreeSans 560 0 0 0 gpio_analog[14]
-port 5 nsew signal bidirectional
-flabel metal3 s -400 40777 240 40833 0 FreeSans 560 0 0 0 gpio_analog[15]
-port 6 nsew signal bidirectional
-flabel metal3 s -400 19166 240 19222 0 FreeSans 560 0 0 0 gpio_analog[16]
-port 7 nsew signal bidirectional
-flabel metal3 s -400 8455 240 8511 0 FreeSans 560 0 0 0 gpio_analog[17]
-port 8 nsew signal bidirectional
-flabel metal3 s 291760 156826 292400 156882 0 FreeSans 560 0 0 0 gpio_analog[1]
-port 9 nsew signal bidirectional
-flabel metal3 s 291760 179437 292400 179493 0 FreeSans 560 0 0 0 gpio_analog[2]
-port 10 nsew signal bidirectional
-flabel metal3 s 291760 202648 292400 202704 0 FreeSans 560 0 0 0 gpio_analog[3]
-port 11 nsew signal bidirectional
-flabel metal3 s 291760 224859 292400 224915 0 FreeSans 560 0 0 0 gpio_analog[4]
-port 12 nsew signal bidirectional
-flabel metal3 s 291760 247070 292400 247126 0 FreeSans 560 0 0 0 gpio_analog[5]
-port 13 nsew signal bidirectional
-flabel metal3 s 291760 291781 292400 291837 0 FreeSans 560 0 0 0 gpio_analog[6]
-port 14 nsew signal bidirectional
-flabel metal3 s -400 255765 240 255821 0 FreeSans 560 0 0 0 gpio_analog[7]
-port 15 nsew signal bidirectional
-flabel metal3 s -400 234154 240 234210 0 FreeSans 560 0 0 0 gpio_analog[8]
-port 16 nsew signal bidirectional
-flabel metal3 s -400 212543 240 212599 0 FreeSans 560 0 0 0 gpio_analog[9]
-port 17 nsew signal bidirectional
-flabel metal3 s 291760 135206 292400 135262 0 FreeSans 560 0 0 0 gpio_noesd[0]
-port 18 nsew signal bidirectional
-flabel metal3 s -400 190341 240 190397 0 FreeSans 560 0 0 0 gpio_noesd[10]
-port 19 nsew signal bidirectional
-flabel metal3 s -400 168730 240 168786 0 FreeSans 560 0 0 0 gpio_noesd[11]
-port 20 nsew signal bidirectional
-flabel metal3 s -400 147119 240 147175 0 FreeSans 560 0 0 0 gpio_noesd[12]
-port 21 nsew signal bidirectional
-flabel metal3 s -400 125608 240 125664 0 FreeSans 560 0 0 0 gpio_noesd[13]
-port 22 nsew signal bidirectional
-flabel metal3 s -400 61797 240 61853 0 FreeSans 560 0 0 0 gpio_noesd[14]
-port 23 nsew signal bidirectional
-flabel metal3 s -400 40186 240 40242 0 FreeSans 560 0 0 0 gpio_noesd[15]
-port 24 nsew signal bidirectional
-flabel metal3 s -400 18575 240 18631 0 FreeSans 560 0 0 0 gpio_noesd[16]
-port 25 nsew signal bidirectional
-flabel metal3 s -400 7864 240 7920 0 FreeSans 560 0 0 0 gpio_noesd[17]
-port 26 nsew signal bidirectional
-flabel metal3 s 291760 157417 292400 157473 0 FreeSans 560 0 0 0 gpio_noesd[1]
-port 27 nsew signal bidirectional
-flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
-port 28 nsew signal bidirectional
-flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
-port 29 nsew signal bidirectional
-flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
-port 30 nsew signal bidirectional
-flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
-port 31 nsew signal bidirectional
-flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
-port 32 nsew signal bidirectional
-flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
-port 33 nsew signal bidirectional
-flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
-port 34 nsew signal bidirectional
-flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
-port 35 nsew signal bidirectional
-flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
-port 36 nsew signal bidirectional
-flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
-port 37 nsew signal bidirectional
-flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
-port 38 nsew signal bidirectional
-flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
-port 39 nsew signal bidirectional
-flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
-port 40 nsew signal bidirectional
-flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
-port 41 nsew signal bidirectional
-flabel metal4 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
-port 41 nsew signal bidirectional
-flabel metal5 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
-port 41 nsew signal bidirectional
-flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
-port 42 nsew signal bidirectional
-flabel metal4 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
-port 42 nsew signal bidirectional
-flabel metal5 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
-port 42 nsew signal bidirectional
-flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
-port 43 nsew signal bidirectional
-flabel metal4 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
-port 43 nsew signal bidirectional
-flabel metal5 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
-port 43 nsew signal bidirectional
-flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
-port 44 nsew signal bidirectional
-flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
-port 45 nsew signal bidirectional
-flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
-port 46 nsew signal bidirectional
-flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
-port 47 nsew signal bidirectional
-flabel metal4 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
-port 47 nsew signal bidirectional
-flabel metal5 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
-port 47 nsew signal bidirectional
-flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
-port 48 nsew signal bidirectional
-flabel metal4 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
-port 48 nsew signal bidirectional
-flabel metal5 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
-port 48 nsew signal bidirectional
-flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
-port 49 nsew signal bidirectional
-flabel metal4 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
-port 49 nsew signal bidirectional
-flabel metal5 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
-port 49 nsew signal bidirectional
-flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
-port 50 nsew signal bidirectional
-flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
-port 51 nsew signal bidirectional
-flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
-port 52 nsew signal bidirectional
-flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
-port 53 nsew signal bidirectional
-flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
-port 54 nsew signal bidirectional
-flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
-port 55 nsew signal bidirectional
-flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
-port 56 nsew signal input
-flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
-port 57 nsew signal input
-flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
-port 58 nsew signal input
-flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
-port 59 nsew signal input
-flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
-port 60 nsew signal input
-flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
-port 61 nsew signal input
-flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
-port 62 nsew signal input
-flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
-port 63 nsew signal input
-flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
-port 64 nsew signal input
-flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
-port 65 nsew signal input
-flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
-port 66 nsew signal input
-flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
-port 67 nsew signal input
-flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
-port 68 nsew signal input
-flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
-port 69 nsew signal input
-flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
-port 70 nsew signal input
-flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
-port 71 nsew signal input
-flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
-port 72 nsew signal input
-flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
-port 73 nsew signal input
-flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
-port 74 nsew signal input
-flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
-port 75 nsew signal input
-flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
-port 76 nsew signal input
-flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
-port 77 nsew signal input
-flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
-port 78 nsew signal input
-flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
-port 79 nsew signal input
-flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
-port 80 nsew signal input
-flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
-port 81 nsew signal input
-flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
-port 82 nsew signal input
-flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
-port 83 nsew signal input
-flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
-port 84 nsew signal input
-flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
-port 85 nsew signal input
-flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
-port 86 nsew signal input
-flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
-port 87 nsew signal input
-flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
-port 88 nsew signal input
-flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
-port 89 nsew signal input
-flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
-port 90 nsew signal input
-flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
-port 91 nsew signal input
-flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
-port 92 nsew signal input
-flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
-port 93 nsew signal input
-flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
-port 94 nsew signal input
-flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
-port 95 nsew signal input
-flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
-port 96 nsew signal input
-flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
-port 97 nsew signal input
-flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
-port 98 nsew signal input
-flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
-port 99 nsew signal input
-flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
-port 100 nsew signal input
-flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
-port 101 nsew signal input
-flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
-port 102 nsew signal input
-flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
-port 103 nsew signal input
-flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
-port 104 nsew signal input
-flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
-port 105 nsew signal input
-flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
-port 106 nsew signal input
-flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
-port 107 nsew signal input
-flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
-port 108 nsew signal input
-flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
-port 109 nsew signal input
-flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
-port 110 nsew signal tristate
-flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
-port 111 nsew signal tristate
-flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
-port 112 nsew signal tristate
-flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
-port 113 nsew signal tristate
-flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
-port 114 nsew signal tristate
-flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
-port 115 nsew signal tristate
-flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
-port 116 nsew signal tristate
-flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
-port 117 nsew signal tristate
-flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
-port 118 nsew signal tristate
-flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
-port 119 nsew signal tristate
-flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
-port 120 nsew signal tristate
-flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
-port 121 nsew signal tristate
-flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
-port 122 nsew signal tristate
-flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
-port 123 nsew signal tristate
-flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
-port 124 nsew signal tristate
-flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
-port 125 nsew signal tristate
-flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
-port 126 nsew signal tristate
-flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
-port 127 nsew signal tristate
-flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
-port 128 nsew signal tristate
-flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
-port 129 nsew signal tristate
-flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
-port 130 nsew signal tristate
-flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
-port 131 nsew signal tristate
-flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
-port 132 nsew signal tristate
-flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
-port 133 nsew signal tristate
-flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
-port 134 nsew signal tristate
-flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
-port 135 nsew signal tristate
-flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
-port 136 nsew signal tristate
-flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
-port 137 nsew signal tristate
-flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
-port 138 nsew signal tristate
-flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
-port 139 nsew signal tristate
-flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
-port 140 nsew signal tristate
-flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
-port 141 nsew signal tristate
-flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
-port 142 nsew signal tristate
-flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
-port 143 nsew signal tristate
-flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
-port 144 nsew signal tristate
-flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
-port 145 nsew signal tristate
-flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
-port 146 nsew signal tristate
-flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
-port 147 nsew signal tristate
-flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
-port 148 nsew signal tristate
-flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
-port 149 nsew signal tristate
-flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
-port 150 nsew signal tristate
-flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
-port 151 nsew signal tristate
-flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
-port 152 nsew signal tristate
-flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
-port 153 nsew signal tristate
-flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
-port 154 nsew signal tristate
-flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
-port 155 nsew signal tristate
-flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
-port 156 nsew signal tristate
-flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
-port 157 nsew signal tristate
-flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
-port 158 nsew signal tristate
-flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
-port 159 nsew signal tristate
-flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
-port 160 nsew signal tristate
-flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
-port 161 nsew signal tristate
-flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
-port 162 nsew signal tristate
-flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
-port 163 nsew signal tristate
-flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
-port 164 nsew signal input
-flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
-port 165 nsew signal input
-flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
-port 166 nsew signal input
-flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
-port 167 nsew signal input
-flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
-port 168 nsew signal input
-flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
-port 169 nsew signal input
-flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
-port 170 nsew signal input
-flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
-port 171 nsew signal input
-flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
-port 172 nsew signal input
-flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
-port 173 nsew signal input
-flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
-port 174 nsew signal input
-flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
-port 175 nsew signal input
-flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
-port 176 nsew signal input
-flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
-port 177 nsew signal input
-flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
-port 178 nsew signal input
-flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
-port 179 nsew signal input
-flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
-port 180 nsew signal input
-flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
-port 181 nsew signal input
-flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
-port 182 nsew signal input
-flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
-port 183 nsew signal input
-flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
-port 184 nsew signal input
-flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
-port 185 nsew signal input
-flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
-port 186 nsew signal input
-flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
-port 187 nsew signal input
-flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
-port 188 nsew signal input
-flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
-port 189 nsew signal input
-flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
-port 190 nsew signal input
-flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
-port 191 nsew signal input
-flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
-port 192 nsew signal input
-flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
-port 193 nsew signal input
-flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
-port 194 nsew signal input
-flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
-port 195 nsew signal input
-flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
-port 196 nsew signal input
-flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
-port 197 nsew signal input
-flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
-port 198 nsew signal input
-flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
-port 199 nsew signal input
-flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
-port 200 nsew signal input
-flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
-port 201 nsew signal input
-flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
-port 202 nsew signal input
-flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
-port 203 nsew signal input
-flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
-port 204 nsew signal input
-flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
-port 205 nsew signal input
-flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
-port 206 nsew signal input
-flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
-port 207 nsew signal input
-flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
-port 208 nsew signal input
-flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
-port 209 nsew signal input
-flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
-port 210 nsew signal input
-flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
-port 211 nsew signal input
-flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
-port 212 nsew signal input
-flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
-port 213 nsew signal input
-flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
-port 214 nsew signal input
-flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
-port 215 nsew signal input
-flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
-port 216 nsew signal input
-flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
-port 217 nsew signal input
-flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
-port 218 nsew signal input
-flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
-port 219 nsew signal input
-flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
-port 220 nsew signal input
-flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
-port 221 nsew signal input
-flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
-port 222 nsew signal input
-flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
-port 223 nsew signal input
-flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
-port 224 nsew signal input
-flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
-port 225 nsew signal input
-flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
-port 226 nsew signal input
-flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
-port 227 nsew signal input
-flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
-port 228 nsew signal input
-flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
-port 229 nsew signal input
-flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
-port 230 nsew signal input
-flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
-port 231 nsew signal input
-flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
-port 232 nsew signal input
-flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
-port 233 nsew signal input
-flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
-port 234 nsew signal input
-flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
-port 235 nsew signal input
-flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
-port 236 nsew signal input
-flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
-port 237 nsew signal input
-flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
-port 238 nsew signal input
-flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
-port 239 nsew signal input
-flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
-port 240 nsew signal input
-flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
-port 241 nsew signal input
-flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
-port 242 nsew signal input
-flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
-port 243 nsew signal input
-flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
-port 244 nsew signal input
-flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
-port 245 nsew signal input
-flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
-port 246 nsew signal input
-flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
-port 247 nsew signal input
-flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
-port 248 nsew signal input
-flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
-port 249 nsew signal input
-flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
-port 250 nsew signal input
-flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
-port 251 nsew signal input
-flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
-port 252 nsew signal input
-flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
-port 253 nsew signal input
-flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
-port 254 nsew signal input
-flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
-port 255 nsew signal input
-flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
-port 256 nsew signal input
-flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
-port 257 nsew signal input
-flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
-port 258 nsew signal input
-flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
-port 259 nsew signal input
-flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
-port 260 nsew signal input
-flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
-port 261 nsew signal input
-flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
-port 262 nsew signal input
-flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
-port 263 nsew signal input
-flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
-port 264 nsew signal input
-flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
-port 265 nsew signal input
-flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
-port 266 nsew signal input
-flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
-port 267 nsew signal input
-flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
-port 268 nsew signal input
-flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
-port 269 nsew signal input
-flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
-port 270 nsew signal input
-flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
-port 271 nsew signal input
-flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
-port 272 nsew signal input
-flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
-port 273 nsew signal input
-flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
-port 274 nsew signal input
-flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
-port 275 nsew signal input
-flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
-port 276 nsew signal input
-flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
-port 277 nsew signal input
-flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
-port 278 nsew signal input
-flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
-port 279 nsew signal input
-flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
-port 280 nsew signal input
-flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
-port 281 nsew signal input
-flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
-port 282 nsew signal input
-flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
-port 283 nsew signal input
-flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
-port 284 nsew signal input
-flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
-port 285 nsew signal input
-flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
-port 286 nsew signal input
-flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
-port 287 nsew signal input
-flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
-port 288 nsew signal input
-flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
-port 289 nsew signal input
-flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
-port 290 nsew signal input
-flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
-port 291 nsew signal input
-flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
-port 292 nsew signal tristate
-flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
-port 293 nsew signal tristate
-flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
-port 294 nsew signal tristate
-flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
-port 295 nsew signal tristate
-flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
-port 296 nsew signal tristate
-flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
-port 297 nsew signal tristate
-flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
-port 298 nsew signal tristate
-flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
-port 299 nsew signal tristate
-flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
-port 300 nsew signal tristate
-flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
-port 301 nsew signal tristate
-flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
-port 302 nsew signal tristate
-flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
-port 303 nsew signal tristate
-flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
-port 304 nsew signal tristate
-flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
-port 305 nsew signal tristate
-flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
-port 306 nsew signal tristate
-flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
-port 307 nsew signal tristate
-flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
-port 308 nsew signal tristate
-flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
-port 309 nsew signal tristate
-flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
-port 310 nsew signal tristate
-flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
-port 311 nsew signal tristate
-flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
-port 312 nsew signal tristate
-flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
-port 313 nsew signal tristate
-flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
-port 314 nsew signal tristate
-flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
-port 315 nsew signal tristate
-flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
-port 316 nsew signal tristate
-flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
-port 317 nsew signal tristate
-flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
-port 318 nsew signal tristate
-flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
-port 319 nsew signal tristate
-flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
-port 320 nsew signal tristate
-flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
-port 321 nsew signal tristate
-flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
-port 322 nsew signal tristate
-flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
-port 323 nsew signal tristate
-flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
-port 324 nsew signal tristate
-flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
-port 325 nsew signal tristate
-flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
-port 326 nsew signal tristate
-flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
-port 327 nsew signal tristate
-flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
-port 328 nsew signal tristate
-flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
-port 329 nsew signal tristate
-flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
-port 330 nsew signal tristate
-flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
-port 331 nsew signal tristate
-flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
-port 332 nsew signal tristate
-flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
-port 333 nsew signal tristate
-flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
-port 334 nsew signal tristate
-flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
-port 335 nsew signal tristate
-flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
-port 336 nsew signal tristate
-flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
-port 337 nsew signal tristate
-flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
-port 338 nsew signal tristate
-flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
-port 339 nsew signal tristate
-flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
-port 340 nsew signal tristate
-flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
-port 341 nsew signal tristate
-flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
-port 342 nsew signal tristate
-flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
-port 343 nsew signal tristate
-flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
-port 344 nsew signal tristate
-flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
-port 345 nsew signal tristate
-flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
-port 346 nsew signal tristate
-flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
-port 347 nsew signal tristate
-flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
-port 348 nsew signal tristate
-flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
-port 349 nsew signal tristate
-flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
-port 350 nsew signal tristate
-flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
-port 351 nsew signal tristate
-flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
-port 352 nsew signal tristate
-flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
-port 353 nsew signal tristate
-flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
-port 354 nsew signal tristate
-flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
-port 355 nsew signal tristate
-flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
-port 356 nsew signal tristate
-flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
-port 357 nsew signal tristate
-flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
-port 358 nsew signal tristate
-flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
-port 359 nsew signal tristate
-flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
-port 360 nsew signal tristate
-flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
-port 361 nsew signal tristate
-flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
-port 362 nsew signal tristate
-flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
-port 363 nsew signal tristate
-flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
-port 364 nsew signal tristate
-flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
-port 365 nsew signal tristate
-flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
-port 366 nsew signal tristate
-flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
-port 367 nsew signal tristate
-flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
-port 368 nsew signal tristate
-flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
-port 369 nsew signal tristate
-flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
-port 370 nsew signal tristate
-flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
-port 371 nsew signal tristate
-flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
-port 372 nsew signal tristate
-flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
-port 373 nsew signal tristate
-flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
-port 374 nsew signal tristate
-flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
-port 375 nsew signal tristate
-flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
-port 376 nsew signal tristate
-flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
-port 377 nsew signal tristate
-flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
-port 378 nsew signal tristate
-flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
-port 379 nsew signal tristate
-flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
-port 380 nsew signal tristate
-flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
-port 381 nsew signal tristate
-flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
-port 382 nsew signal tristate
-flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
-port 383 nsew signal tristate
-flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
-port 384 nsew signal tristate
-flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
-port 385 nsew signal tristate
-flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
-port 386 nsew signal tristate
-flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
-port 387 nsew signal tristate
-flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
-port 388 nsew signal tristate
-flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
-port 389 nsew signal tristate
-flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
-port 390 nsew signal tristate
-flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
-port 391 nsew signal tristate
-flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
-port 392 nsew signal tristate
-flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
-port 393 nsew signal tristate
-flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
-port 394 nsew signal tristate
-flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
-port 395 nsew signal tristate
-flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
-port 396 nsew signal tristate
-flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
-port 397 nsew signal tristate
-flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
-port 398 nsew signal tristate
-flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
-port 399 nsew signal tristate
-flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
-port 400 nsew signal tristate
-flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
-port 401 nsew signal tristate
-flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
-port 402 nsew signal tristate
-flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
-port 403 nsew signal tristate
-flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
-port 404 nsew signal tristate
-flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
-port 405 nsew signal tristate
-flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
-port 406 nsew signal tristate
-flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
-port 407 nsew signal tristate
-flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
-port 408 nsew signal tristate
-flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
-port 409 nsew signal tristate
-flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
-port 410 nsew signal tristate
-flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
-port 411 nsew signal tristate
-flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
-port 412 nsew signal tristate
-flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
-port 413 nsew signal tristate
-flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
-port 414 nsew signal tristate
-flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
-port 415 nsew signal tristate
-flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
-port 416 nsew signal tristate
-flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
-port 417 nsew signal tristate
-flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
-port 418 nsew signal tristate
-flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
-port 419 nsew signal tristate
-flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
-port 420 nsew signal input
-flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
-port 421 nsew signal input
-flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
-port 422 nsew signal input
-flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
-port 423 nsew signal input
-flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
-port 424 nsew signal input
-flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
-port 425 nsew signal input
-flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
-port 426 nsew signal input
-flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
-port 427 nsew signal input
-flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
-port 428 nsew signal input
-flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
-port 429 nsew signal input
-flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
-port 430 nsew signal input
-flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
-port 431 nsew signal input
-flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
-port 432 nsew signal input
-flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
-port 433 nsew signal input
-flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
-port 434 nsew signal input
-flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
-port 435 nsew signal input
-flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
-port 436 nsew signal input
-flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
-port 437 nsew signal input
-flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
-port 438 nsew signal input
-flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
-port 439 nsew signal input
-flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
-port 440 nsew signal input
-flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
-port 441 nsew signal input
-flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
-port 442 nsew signal input
-flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
-port 443 nsew signal input
-flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
-port 444 nsew signal input
-flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
-port 445 nsew signal input
-flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
-port 446 nsew signal input
-flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
-port 447 nsew signal input
-flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
-port 448 nsew signal input
-flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
-port 449 nsew signal input
-flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
-port 450 nsew signal input
-flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
-port 451 nsew signal input
-flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
-port 452 nsew signal input
-flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
-port 453 nsew signal input
-flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
-port 454 nsew signal input
-flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
-port 455 nsew signal input
-flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
-port 456 nsew signal input
-flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
-port 457 nsew signal input
-flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
-port 458 nsew signal input
-flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
-port 459 nsew signal input
-flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
-port 460 nsew signal input
-flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
-port 461 nsew signal input
-flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
-port 462 nsew signal input
-flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
-port 463 nsew signal input
-flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
-port 464 nsew signal input
-flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
-port 465 nsew signal input
-flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
-port 466 nsew signal input
-flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
-port 467 nsew signal input
-flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
-port 468 nsew signal input
-flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
-port 469 nsew signal input
-flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
-port 470 nsew signal input
-flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
-port 471 nsew signal input
-flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
-port 472 nsew signal input
-flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
-port 473 nsew signal input
-flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
-port 474 nsew signal input
-flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
-port 475 nsew signal input
-flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
-port 476 nsew signal input
-flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
-port 477 nsew signal input
-flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
-port 478 nsew signal input
-flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
-port 479 nsew signal input
-flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
-port 480 nsew signal input
-flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
-port 481 nsew signal input
-flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
-port 482 nsew signal input
-flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
-port 483 nsew signal input
-flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
-port 484 nsew signal input
-flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
-port 485 nsew signal input
-flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
-port 486 nsew signal input
-flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
-port 487 nsew signal input
-flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
-port 488 nsew signal input
-flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
-port 489 nsew signal input
-flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
-port 490 nsew signal input
-flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
-port 491 nsew signal input
-flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
-port 492 nsew signal input
-flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
-port 493 nsew signal input
-flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
-port 494 nsew signal input
-flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
-port 495 nsew signal input
-flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
-port 496 nsew signal input
-flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
-port 497 nsew signal input
-flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
-port 498 nsew signal input
-flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
-port 499 nsew signal input
-flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
-port 500 nsew signal input
-flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
-port 501 nsew signal input
-flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
-port 502 nsew signal input
-flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
-port 503 nsew signal input
-flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
-port 504 nsew signal input
-flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
-port 505 nsew signal input
-flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
-port 506 nsew signal input
-flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
-port 507 nsew signal input
-flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
-port 508 nsew signal input
-flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
-port 509 nsew signal input
-flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
-port 510 nsew signal input
-flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
-port 511 nsew signal input
-flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
-port 512 nsew signal input
-flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
-port 513 nsew signal input
-flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
-port 514 nsew signal input
-flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
-port 515 nsew signal input
-flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
-port 516 nsew signal input
-flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
-port 517 nsew signal input
-flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
-port 518 nsew signal input
-flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
-port 519 nsew signal input
-flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
-port 520 nsew signal input
-flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
-port 521 nsew signal input
-flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
-port 522 nsew signal input
-flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
-port 523 nsew signal input
-flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
-port 524 nsew signal input
-flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
-port 525 nsew signal input
-flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
-port 526 nsew signal input
-flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
-port 527 nsew signal input
-flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
-port 528 nsew signal input
-flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
-port 529 nsew signal input
-flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
-port 530 nsew signal input
-flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
-port 531 nsew signal input
-flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
-port 532 nsew signal input
-flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
-port 533 nsew signal input
-flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
-port 534 nsew signal input
-flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
-port 535 nsew signal input
-flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
-port 536 nsew signal input
-flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
-port 537 nsew signal input
-flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
-port 538 nsew signal input
-flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
-port 539 nsew signal input
-flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
-port 540 nsew signal input
-flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
-port 541 nsew signal input
-flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
-port 542 nsew signal input
-flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
-port 543 nsew signal input
-flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
-port 544 nsew signal input
-flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
-port 545 nsew signal input
-flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
-port 546 nsew signal input
-flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
-port 547 nsew signal input
-flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
-port 548 nsew signal input
-flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
-port 549 nsew signal tristate
-flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
-port 550 nsew signal tristate
-flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
-port 551 nsew signal tristate
-flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
-port 552 nsew signal bidirectional
-flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
-port 553 nsew signal bidirectional
-flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
-port 554 nsew signal bidirectional
-flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
-port 555 nsew signal bidirectional
-flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
-port 556 nsew signal bidirectional
-flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
-port 557 nsew signal bidirectional
-flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
-port 558 nsew signal bidirectional
-flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
-port 559 nsew signal bidirectional
-flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
-port 560 nsew signal bidirectional
-flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
-port 561 nsew signal bidirectional
-flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
-port 562 nsew signal bidirectional
-flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
-port 563 nsew signal bidirectional
-flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
-port 564 nsew signal bidirectional
-flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
-port 565 nsew signal bidirectional
-flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
-port 566 nsew signal bidirectional
-flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
-port 567 nsew signal bidirectional
-flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
-port 568 nsew signal bidirectional
-flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
-port 569 nsew signal bidirectional
-flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
-port 570 nsew signal bidirectional
-flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
-port 571 nsew signal bidirectional
-flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
-port 572 nsew signal input
-flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
-port 573 nsew signal input
-flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
-port 574 nsew signal tristate
-flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
-port 575 nsew signal input
-flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
-port 576 nsew signal input
-flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
-port 577 nsew signal input
-flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
-port 578 nsew signal input
-flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
-port 579 nsew signal input
-flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
-port 580 nsew signal input
-flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
-port 581 nsew signal input
-flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
-port 582 nsew signal input
-flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
-port 583 nsew signal input
-flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
-port 584 nsew signal input
-flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
-port 585 nsew signal input
-flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
-port 586 nsew signal input
-flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
-port 587 nsew signal input
-flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
-port 588 nsew signal input
-flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
-port 589 nsew signal input
-flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
-port 590 nsew signal input
-flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
-port 591 nsew signal input
-flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
-port 592 nsew signal input
-flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
-port 593 nsew signal input
-flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
-port 594 nsew signal input
-flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
-port 595 nsew signal input
-flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
-port 596 nsew signal input
-flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
-port 597 nsew signal input
-flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
-port 598 nsew signal input
-flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
-port 599 nsew signal input
-flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
-port 600 nsew signal input
-flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
-port 601 nsew signal input
-flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
-port 602 nsew signal input
-flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
-port 603 nsew signal input
-flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
-port 604 nsew signal input
-flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
-port 605 nsew signal input
-flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
-port 606 nsew signal input
-flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
-port 607 nsew signal input
-flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
-port 608 nsew signal input
-flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
-port 609 nsew signal input
-flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
-port 610 nsew signal input
-flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
-port 611 nsew signal input
-flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
-port 612 nsew signal input
-flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
-port 613 nsew signal input
-flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
-port 614 nsew signal input
-flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
-port 615 nsew signal input
-flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
-port 616 nsew signal input
-flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
-port 617 nsew signal input
-flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
-port 618 nsew signal input
-flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
-port 619 nsew signal input
-flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
-port 620 nsew signal input
-flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
-port 621 nsew signal input
-flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
-port 622 nsew signal input
-flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
-port 623 nsew signal input
-flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
-port 624 nsew signal input
-flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
-port 625 nsew signal input
-flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
-port 626 nsew signal input
-flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
-port 627 nsew signal input
-flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
-port 628 nsew signal input
-flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
-port 629 nsew signal input
-flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
-port 630 nsew signal input
-flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
-port 631 nsew signal input
-flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
-port 632 nsew signal input
-flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
-port 633 nsew signal input
-flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
-port 634 nsew signal input
-flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
-port 635 nsew signal input
-flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
-port 636 nsew signal input
-flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
-port 637 nsew signal input
-flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
-port 638 nsew signal input
-flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
-port 639 nsew signal input
-flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
-port 640 nsew signal tristate
-flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
-port 641 nsew signal tristate
-flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
-port 642 nsew signal tristate
-flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
-port 643 nsew signal tristate
-flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
-port 644 nsew signal tristate
-flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
-port 645 nsew signal tristate
-flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
-port 646 nsew signal tristate
-flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
-port 647 nsew signal tristate
-flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
-port 648 nsew signal tristate
-flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
-port 649 nsew signal tristate
-flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
-port 650 nsew signal tristate
-flabel metal2 s 7354 -400 7410 240 0 FreeSans 560 90 0 0 wbs_dat_o[1]
-port 651 nsew signal tristate
-flabel metal2 s 42814 -400 42870 240 0 FreeSans 560 90 0 0 wbs_dat_o[20]
-port 652 nsew signal tristate
-flabel metal2 s 44587 -400 44643 240 0 FreeSans 560 90 0 0 wbs_dat_o[21]
-port 653 nsew signal tristate
-flabel metal2 s 46360 -400 46416 240 0 FreeSans 560 90 0 0 wbs_dat_o[22]
-port 654 nsew signal tristate
-flabel metal2 s 48133 -400 48189 240 0 FreeSans 560 90 0 0 wbs_dat_o[23]
-port 655 nsew signal tristate
-flabel metal2 s 49906 -400 49962 240 0 FreeSans 560 90 0 0 wbs_dat_o[24]
-port 656 nsew signal tristate
-flabel metal2 s 51679 -400 51735 240 0 FreeSans 560 90 0 0 wbs_dat_o[25]
-port 657 nsew signal tristate
-flabel metal2 s 53452 -400 53508 240 0 FreeSans 560 90 0 0 wbs_dat_o[26]
-port 658 nsew signal tristate
-flabel metal2 s 55225 -400 55281 240 0 FreeSans 560 90 0 0 wbs_dat_o[27]
-port 659 nsew signal tristate
-flabel metal2 s 56998 -400 57054 240 0 FreeSans 560 90 0 0 wbs_dat_o[28]
-port 660 nsew signal tristate
-flabel metal2 s 58771 -400 58827 240 0 FreeSans 560 90 0 0 wbs_dat_o[29]
-port 661 nsew signal tristate
-flabel metal2 s 9718 -400 9774 240 0 FreeSans 560 90 0 0 wbs_dat_o[2]
-port 662 nsew signal tristate
-flabel metal2 s 60544 -400 60600 240 0 FreeSans 560 90 0 0 wbs_dat_o[30]
-port 663 nsew signal tristate
-flabel metal2 s 62317 -400 62373 240 0 FreeSans 560 90 0 0 wbs_dat_o[31]
-port 664 nsew signal tristate
-flabel metal2 s 12082 -400 12138 240 0 FreeSans 560 90 0 0 wbs_dat_o[3]
-port 665 nsew signal tristate
-flabel metal2 s 14446 -400 14502 240 0 FreeSans 560 90 0 0 wbs_dat_o[4]
-port 666 nsew signal tristate
-flabel metal2 s 16219 -400 16275 240 0 FreeSans 560 90 0 0 wbs_dat_o[5]
-port 667 nsew signal tristate
-flabel metal2 s 17992 -400 18048 240 0 FreeSans 560 90 0 0 wbs_dat_o[6]
-port 668 nsew signal tristate
-flabel metal2 s 19765 -400 19821 240 0 FreeSans 560 90 0 0 wbs_dat_o[7]
-port 669 nsew signal tristate
-flabel metal2 s 21538 -400 21594 240 0 FreeSans 560 90 0 0 wbs_dat_o[8]
-port 670 nsew signal tristate
-flabel metal2 s 23311 -400 23367 240 0 FreeSans 560 90 0 0 wbs_dat_o[9]
-port 671 nsew signal tristate
-flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
-port 672 nsew signal input
-flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
-port 673 nsew signal input
-flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
-port 674 nsew signal input
-flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
-port 675 nsew signal input
-flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
-port 676 nsew signal input
-flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
-port 677 nsew signal input
-<< properties >>
-string FIXED_BBOX 0 0 292000 352000
-<< end >>
diff --git a/netgen/comp.out b/netgen/comp.out
deleted file mode 100644
index 42163df..0000000
--- a/netgen/comp.out
+++ /dev/null
@@ -1,2097 +0,0 @@
-Equate elements:  no current cell.
-Equate elements:  no current cell.
-Equate elements:  no current cell.
-Equate elements:  no current cell.
-Equate elements:  no current cell.
-Equate elements:  no current cell.
-Equate elements:  no current cell.
-
-Class sky130_fd_sc_hvl__buf_8(0):  Merged 18 parallel devices.
-Class sky130_fd_sc_hvl__buf_8(1):  Merged 18 parallel devices.
-Subcircuit summary:
-Circuit 1: sky130_fd_sc_hvl__buf_8         |Circuit 2: sky130_fd_sc_hvl__buf_8         
--------------------------------------------|-------------------------------------------
-sky130_fd_pr__nfet_g5v0d10v5 (2)           |sky130_fd_pr__nfet_g5v0d10v5 (2)           
-sky130_fd_pr__pfet_g5v0d10v5 (2)           |sky130_fd_pr__pfet_g5v0d10v5 (2)           
-Number of devices: 4                       |Number of devices: 4                       
-Number of nets: 7                          |Number of nets: 7                          
----------------------------------------------------------------------------------------
-Circuits match uniquely.
-Netlists match uniquely.
-
-Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__buf_8         |Circuit 2: sky130_fd_sc_hvl__buf_8         
--------------------------------------------|-------------------------------------------
-A                                          |A                                          
-VPWR                                       |VPWR                                       
-VPB                                        |VPB                                        
-X                                          |X                                          
-VGND                                       |VGND                                       
-VNB                                        |VNB                                        
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__buf_8 and sky130_fd_sc_hvl__buf_8 are equivalent.
-
-Subcircuit summary:
-Circuit 1: sky130_fd_sc_hvl__schmittbuf_1  |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1  
--------------------------------------------|-------------------------------------------
-sky130_fd_pr__nfet_g5v0d10v5 (4)           |sky130_fd_pr__nfet_g5v0d10v5 (4)           
-sky130_fd_pr__pfet_g5v0d10v5 (4)           |sky130_fd_pr__pfet_g5v0d10v5 (4)           
-sky130_fd_pr__res_generic_nd__hv (1)       |sky130_fd_pr__res_generic_nd__hv (1)       
-sky130_fd_pr__res_generic_pd__hv (1)       |sky130_fd_pr__res_generic_pd__hv (1)       
-Number of devices: 10                      |Number of devices: 10                      
-Number of nets: 11                         |Number of nets: 11                         
----------------------------------------------------------------------------------------
-Circuits match uniquely.
-Netlists match uniquely.
-
-Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__schmittbuf_1  |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1  
--------------------------------------------|-------------------------------------------
-A                                          |A                                          
-VPB                                        |VPB                                        
-VNB                                        |VNB                                        
-VGND                                       |VGND                                       
-VPWR                                       |VPWR                                       
-X                                          |X                                          
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__schmittbuf_1 and sky130_fd_sc_hvl__schmittbuf_1 are equivalent.
-
-Class sky130_fd_sc_hvl__inv_8(0):  Merged 14 parallel devices.
-Class sky130_fd_sc_hvl__inv_8(1):  Merged 14 parallel devices.
-Subcircuit summary:
-Circuit 1: sky130_fd_sc_hvl__inv_8         |Circuit 2: sky130_fd_sc_hvl__inv_8         
--------------------------------------------|-------------------------------------------
-sky130_fd_pr__pfet_g5v0d10v5 (1)           |sky130_fd_pr__pfet_g5v0d10v5 (1)           
-sky130_fd_pr__nfet_g5v0d10v5 (1)           |sky130_fd_pr__nfet_g5v0d10v5 (1)           
-Number of devices: 2                       |Number of devices: 2                       
-Number of nets: 6                          |Number of nets: 6                          
----------------------------------------------------------------------------------------
-Circuits match uniquely.
-Netlists match uniquely.
-
-Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__inv_8         |Circuit 2: sky130_fd_sc_hvl__inv_8         
--------------------------------------------|-------------------------------------------
-VPWR                                       |VPWR                                       
-VPB                                        |VPB                                        
-VGND                                       |VGND                                       
-VNB                                        |VNB                                        
-A                                          |A                                          
-Y                                          |Y                                          
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__inv_8 and sky130_fd_sc_hvl__inv_8 are equivalent.
-Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_W5U4AW in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_3YBPVB in circuit example_por (0)(4 instances)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_WRT4AW in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in circuit example_por (0)(1 instance)
-
-Class example_por(0):  Merged 20 parallel devices.
-Class example_por(0):  Merged 24 series devices.
-Subcircuit summary:
-Circuit 1: example_por                     |Circuit 2: example_por                     
--------------------------------------------|-------------------------------------------
-sky130_fd_pr__cap_mim_m3_2 (1)             |sky130_fd_pr__cap_mim_m3_2 (1)             
-sky130_fd_sc_hvl__buf_8 (2)                |sky130_fd_sc_hvl__buf_8 (2)                
-sky130_fd_pr__pfet_g5v0d10v5 (8)           |sky130_fd_pr__pfet_g5v0d10v5 (8)           
-sky130_fd_pr__nfet_g5v0d10v5 (3)           |sky130_fd_pr__nfet_g5v0d10v5 (3)           
-sky130_fd_pr__res_xhigh_po_0p69 (3)        |sky130_fd_pr__res_xhigh_po_0p69 (3)        
-sky130_fd_sc_hvl__schmittbuf_1 (1)         |sky130_fd_sc_hvl__schmittbuf_1 (1)         
-sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
-sky130_fd_sc_hvl__inv_8 (1)                |sky130_fd_sc_hvl__inv_8 (1)                
-Number of devices: 20                      |Number of devices: 20                      
-Number of nets: 16                         |Number of nets: 16                         
----------------------------------------------------------------------------------------
-Circuits match uniquely.
-Netlists match uniquely.
-
-Subcircuit pins:
-Circuit 1: example_por                     |Circuit 2: example_por                     
--------------------------------------------|-------------------------------------------
-vdd3v3                                     |vdd3v3                                     
-porb_h                                     |porb_h                                     
-porb_l                                     |porb_l                                     
-por_l                                      |por_l                                      
-vdd1v8                                     |vdd1v8                                     
-vss                                        |vss                                        
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes example_por and example_por are equivalent.
-Flattening unmatched subcell user_analog_proj_example in circuit user_analog_project_wrapper (0)(1 instance)
-
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[0]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[10]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[11]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[12]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[13]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[14]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[15]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[16]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[17]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[1]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[2]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[4]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[5]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[6]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[8]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[9]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[0]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[10]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[11]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[12]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[13]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[14]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[15]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[16]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[17]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[1]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[2]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[3]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[4]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[5]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[6]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[7]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[8]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[11]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[12]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[15]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[16]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[24]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[25]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[11]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[12]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[15]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[16]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[24]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[25]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[24]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[25]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[24]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[25]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[9]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[0]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[100]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[101]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[102]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[103]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[104]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[105]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[106]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[107]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[108]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[109]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[10]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[110]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[111]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[112]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[113]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[114]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[115]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[116]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[117]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[118]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[119]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[11]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[120]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[121]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[122]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[123]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[124]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[125]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[126]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[127]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[12]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[13]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[14]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[15]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[16]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[17]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[18]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[19]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[1]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[20]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[21]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[22]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[23]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[24]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[25]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[26]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[27]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[28]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[29]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[2]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[30]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[31]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[32]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[33]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[34]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[35]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[36]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[37]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[38]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[39]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[3]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[40]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[41]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[42]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[43]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[44]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[45]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[46]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[47]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[48]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[49]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[4]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[50]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[51]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[52]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[53]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[54]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[55]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[56]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[57]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[58]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[59]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[5]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[60]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[61]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[62]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[63]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[64]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[65]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[66]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[67]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[68]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[69]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[6]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[70]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[71]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[72]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[73]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[74]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[75]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[76]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[77]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[78]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[79]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[7]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[80]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[81]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[82]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[83]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[84]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[85]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[86]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[87]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[88]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[89]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[8]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[90]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[91]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[92]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[93]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[94]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[95]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[96]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[97]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[98]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[99]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[9]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[0]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[100]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[101]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[102]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[103]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[104]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[105]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[106]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[107]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[108]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[109]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[10]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[110]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[111]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[112]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[113]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[114]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[115]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[116]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[117]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[118]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[119]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[11]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[120]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[121]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[122]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[123]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[124]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[125]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[126]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[127]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[12]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[13]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[14]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[15]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[16]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[17]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[18]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[19]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[1]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[20]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[21]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[22]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[23]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[24]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[25]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[26]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[27]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[28]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[29]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[2]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[30]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[31]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[32]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[33]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[34]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[35]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[36]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[37]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[38]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[39]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[3]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[40]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[41]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[42]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[43]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[44]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[45]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[46]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[47]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[48]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[49]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[4]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[50]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[51]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[52]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[53]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[54]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[55]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[56]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[57]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[58]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[59]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[5]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[60]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[61]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[62]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[63]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[64]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[65]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[66]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[67]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[68]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[69]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[6]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[70]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[71]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[72]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[73]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[74]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[75]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[76]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[77]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[78]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[79]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[7]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[80]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[81]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[82]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[83]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[84]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[85]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[86]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[87]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[88]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[89]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[8]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[90]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[91]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[92]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[93]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[94]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[95]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[96]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[97]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[98]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[99]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[9]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[0]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[100]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[101]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[102]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[103]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[104]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[105]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[106]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[107]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[108]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[109]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[10]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[110]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[111]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[112]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[113]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[114]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[115]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[116]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[117]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[118]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[119]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[11]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[120]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[121]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[122]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[123]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[124]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[125]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[126]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[127]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[12]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[13]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[14]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[15]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[16]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[17]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[18]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[19]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[1]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[20]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[21]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[22]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[23]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[24]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[25]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[26]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[27]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[28]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[29]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[2]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[30]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[31]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[32]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[33]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[34]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[35]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[36]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[37]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[38]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[39]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[3]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[40]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[41]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[42]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[43]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[44]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[45]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[46]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[47]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[48]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[49]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[4]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[50]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[51]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[52]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[53]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[54]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[55]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[56]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[57]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[58]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[59]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[5]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[60]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[61]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[62]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[63]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[64]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[65]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[66]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[67]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[68]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[69]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[6]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[70]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[71]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[72]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[73]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[74]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[75]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[76]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[77]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[78]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[79]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[7]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[80]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[81]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[82]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[83]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[84]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[85]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[86]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[87]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[88]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[89]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[8]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[90]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[91]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[92]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[93]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[94]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[95]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[96]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[97]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[98]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[99]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[9]
-Cell user_analog_project_wrapper(0) disconnected node: user_clock2
-Cell user_analog_project_wrapper(0) disconnected node: user_irq[0]
-Cell user_analog_project_wrapper(0) disconnected node: user_irq[1]
-Cell user_analog_project_wrapper(0) disconnected node: user_irq[2]
-Cell user_analog_project_wrapper(0) disconnected node: vccd2
-Cell user_analog_project_wrapper(0) disconnected node: vdda2
-Cell user_analog_project_wrapper(0) disconnected node: vssa2
-Cell user_analog_project_wrapper(0) disconnected node: vssd2
-Cell user_analog_project_wrapper(0) disconnected node: wb_clk_i
-Cell user_analog_project_wrapper(0) disconnected node: wb_rst_i
-Cell user_analog_project_wrapper(0) disconnected node: wbs_ack_o
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[0]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[10]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[11]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[12]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[13]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[14]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[15]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[16]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[17]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[18]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[19]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[20]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[21]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[22]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[23]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[24]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[25]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[26]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[27]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[28]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[29]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[30]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[31]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[4]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[5]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[6]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[7]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[8]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[9]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_cyc_i
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[0]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[10]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[11]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[12]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[13]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[14]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[15]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[16]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[17]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[18]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[19]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[20]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[21]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[22]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[23]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[24]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[25]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[26]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[27]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[28]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[29]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[30]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[31]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[4]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[5]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[6]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[7]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[8]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[9]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[0]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[10]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[11]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[12]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[13]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[14]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[15]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[16]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[17]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[18]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[19]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[20]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[21]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[22]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[23]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[24]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[25]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[26]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[27]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[28]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[29]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[30]
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-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[4]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[5]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[6]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[7]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[8]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[9]
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-Cell user_analog_project_wrapper(0) disconnected node: wbs_sel_i[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_sel_i[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_sel_i[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_stb_i
-Cell user_analog_project_wrapper(0) disconnected node: wbs_we_i
-Cell user_analog_project_wrapper(1) disconnected node: vdda2
-Cell user_analog_project_wrapper(1) disconnected node: vssa2
-Cell user_analog_project_wrapper(1) disconnected node: vccd2
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-Cell user_analog_project_wrapper(1) disconnected node: wb_clk_i
-Cell user_analog_project_wrapper(1) disconnected node: wb_rst_i
-Cell user_analog_project_wrapper(1) disconnected node: wbs_stb_i
-Cell user_analog_project_wrapper(1) disconnected node: wbs_cyc_i
-Cell user_analog_project_wrapper(1) disconnected node: wbs_we_i
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-Cell user_analog_project_wrapper(1) disconnected node: wbs_sel_i[2]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_sel_i[1]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_sel_i[0]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[31]
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-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[27]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[26]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[25]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[24]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[23]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[22]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[21]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[20]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[19]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[18]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[17]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[16]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[15]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[14]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[13]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[12]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[11]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[10]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[9]
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-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[7]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[6]
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-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[4]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[3]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[2]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[1]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[0]
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-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[26]
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-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[24]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[23]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[22]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[21]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[20]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[19]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[18]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[17]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[16]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[15]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[14]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[13]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[12]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[11]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[10]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[9]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[8]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[7]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[6]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[5]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[4]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[3]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[2]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[1]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_adr_i[0]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_ack_o
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[31]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[30]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[29]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[28]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[27]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[26]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[25]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[24]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[23]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[22]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[21]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[20]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[19]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[18]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[17]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[16]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[15]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[14]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[13]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[12]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[11]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[10]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[9]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[8]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[7]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[6]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[5]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[4]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[3]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[2]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[1]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_o[0]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[127]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[126]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[125]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[116]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[113]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[99]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[98]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[97]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[96]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[95]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[94]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[93]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[92]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[91]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[90]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[89]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[88]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[87]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[86]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[85]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[84]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[83]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[82]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[81]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[80]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[79]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[78]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[77]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[76]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[75]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[74]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[73]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[72]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[71]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[70]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[69]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[68]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[67]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[66]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[65]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[64]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[63]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[62]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[61]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[60]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[59]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[58]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[57]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[56]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[55]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[54]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[53]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[52]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[51]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[50]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[49]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[48]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[47]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[46]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[45]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[44]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[42]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[41]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[40]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[39]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[38]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[37]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[36]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[35]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[34]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[33]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[32]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[31]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[30]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[29]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[28]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[27]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[26]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[25]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[24]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[23]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[22]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[21]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[20]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[19]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[18]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[17]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[16]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[15]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[14]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[13]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[12]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[11]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[10]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[9]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[8]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[7]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[6]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[5]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[4]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[3]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[2]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[1]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_in[0]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[127]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[34]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[17]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[16]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[15]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[14]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[13]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[9]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[4]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[3]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[2]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[1]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[0]
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-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[1]
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-Cell user_analog_project_wrapper(1) disconnected node: io_in[26]
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-Cell user_analog_project_wrapper(1) disconnected node: io_in[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[26]
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-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[11]
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-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[5]
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-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[26]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[25]
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-Cell user_analog_project_wrapper(1) disconnected node: io_out[23]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[22]
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-Cell user_analog_project_wrapper(1) disconnected node: io_out[20]
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-Cell user_analog_project_wrapper(1) disconnected node: io_out[18]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[17]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[14]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[13]
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-Cell user_analog_project_wrapper(1) disconnected node: io_out[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[6]
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-Cell user_analog_project_wrapper(1) disconnected node: io_out[4]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[26]
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-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[23]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[22]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[21]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[20]
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-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[9]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[8]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[5]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[4]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[0]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[17]
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-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[2]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[1]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[0]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[17]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[16]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[15]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[14]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[13]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[12]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[11]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[10]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[9]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[8]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[7]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[6]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[5]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[4]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[3]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[2]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[1]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[10]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[9]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[8]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[5]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[0]
-Cell user_analog_project_wrapper(1) disconnected node: user_clock2
-Cell user_analog_project_wrapper(1) disconnected node: user_irq[2]
-Cell user_analog_project_wrapper(1) disconnected node: user_irq[1]
-Cell user_analog_project_wrapper(1) disconnected node: user_irq[0]
-Subcircuit summary:
-Circuit 1: user_analog_project_wrapper     |Circuit 2: user_analog_project_wrapper     
--------------------------------------------|-------------------------------------------
-example_por (2)                            |example_por (2)                            
-sky130_fd_pr__res_generic_m3 (10)          |sky130_fd_pr__res_generic_m3 (10)          
-Number of devices: 12                      |Number of devices: 12                      
-Number of nets: 21                         |Number of nets: 21                         
----------------------------------------------------------------------------------------
-Resolving automorphisms by property value.
-Resolving automorphisms by pin name.
-Netlists match uniquely.
-Circuits match correctly.
-
-Subcircuit pins:
-Circuit 1: user_analog_project_wrapper     |Circuit 2: user_analog_project_wrapper     
--------------------------------------------|-------------------------------------------
-vssd1                                      |vssd1                                      
-vssa1                                      |vssa1                                      
-vccd1                                      |vccd1                                      
-io_analog[4]                               |io_analog[4]                               
-vdda1                                      |vdda1                                      
-gpio_analog[3]                             |gpio_analog[3]                             
-io_out[11]                                 |io_out[11]                                 
-io_out[12]                                 |io_out[12]                                 
-gpio_analog[7]                             |gpio_analog[7]                             
-io_out[15]                                 |io_out[15]                                 
-io_out[16]                                 |io_out[16]                                 
-io_clamp_low[2]                            |io_clamp_low[2]                            
-io_clamp_high[2]                           |io_clamp_high[2]                           
-io_clamp_low[1]                            |io_clamp_low[1]                            
-io_clamp_high[1]                           |io_clamp_high[1]                           
-io_clamp_low[0]                            |io_clamp_low[0]                            
-io_clamp_high[0]                           |io_clamp_high[0]                           
-io_oeb[12]                                 |io_oeb[12]                                 
-io_oeb[16]                                 |io_oeb[16]                                 
-io_oeb[11]                                 |io_oeb[11]                                 
-io_oeb[15]                                 |io_oeb[15]                                 
-gpio_analog[0]                             |gpio_analog[0]                             
-gpio_analog[10]                            |gpio_analog[10]                            
-gpio_analog[11]                            |gpio_analog[11]                            
-gpio_analog[12]                            |gpio_analog[12]                            
-gpio_analog[13]                            |gpio_analog[13]                            
-gpio_analog[14]                            |gpio_analog[14]                            
-gpio_analog[15]                            |gpio_analog[15]                            
-gpio_analog[16]                            |gpio_analog[16]                            
-gpio_analog[17]                            |gpio_analog[17]                            
-gpio_analog[1]                             |gpio_analog[1]                             
-gpio_analog[2]                             |gpio_analog[2]                             
-gpio_analog[4]                             |gpio_analog[4]                             
-gpio_analog[5]                             |gpio_analog[5]                             
-gpio_analog[6]                             |gpio_analog[6]                             
-gpio_analog[8]                             |gpio_analog[8]                             
-gpio_analog[9]                             |gpio_analog[9]                             
-gpio_noesd[0]                              |gpio_noesd[0]                              
-gpio_noesd[10]                             |gpio_noesd[10]                             
-gpio_noesd[11]                             |gpio_noesd[11]                             
-gpio_noesd[12]                             |gpio_noesd[12]                             
-gpio_noesd[13]                             |gpio_noesd[13]                             
-gpio_noesd[14]                             |gpio_noesd[14]                             
-gpio_noesd[15]                             |gpio_noesd[15]                             
-gpio_noesd[16]                             |gpio_noesd[16]                             
-gpio_noesd[17]                             |gpio_noesd[17]                             
-gpio_noesd[1]                              |gpio_noesd[1]                              
-gpio_noesd[2]                              |gpio_noesd[2]                              
-gpio_noesd[3]                              |gpio_noesd[3]                              
-gpio_noesd[4]                              |gpio_noesd[4]                              
-gpio_noesd[5]                              |gpio_noesd[5]                              
-gpio_noesd[6]                              |gpio_noesd[6]                              
-gpio_noesd[7]                              |gpio_noesd[7]                              
-gpio_noesd[8]                              |gpio_noesd[8]                              
-gpio_noesd[9]                              |gpio_noesd[9]                              
-io_analog[0]                               |io_analog[0]                               
-io_analog[10]                              |io_analog[10]                              
-io_analog[1]                               |io_analog[1]                               
-io_analog[2]                               |io_analog[2]                               
-io_analog[3]                               |io_analog[3]                               
-io_analog[7]                               |io_analog[7]                               
-io_analog[8]                               |io_analog[8]                               
-io_analog[9]                               |io_analog[9]                               
-io_analog[5]                               |io_analog[5]                               
-io_analog[6]                               |io_analog[6]                               
-io_in[0]                                   |io_in[0]                                   
-io_in[10]                                  |io_in[10]                                  
-io_in[11]                                  |io_in[11]                                  
-io_in[12]                                  |io_in[12]                                  
-io_in[13]                                  |io_in[13]                                  
-io_in[14]                                  |io_in[14]                                  
-io_in[15]                                  |io_in[15]                                  
-io_in[16]                                  |io_in[16]                                  
-io_in[17]                                  |io_in[17]                                  
-io_in[18]                                  |io_in[18]                                  
-io_in[19]                                  |io_in[19]                                  
-io_in[1]                                   |io_in[1]                                   
-io_in[20]                                  |io_in[20]                                  
-io_in[21]                                  |io_in[21]                                  
-io_in[22]                                  |io_in[22]                                  
-io_in[23]                                  |io_in[23]                                  
-io_in[24]                                  |io_in[24]                                  
-io_in[25]                                  |io_in[25]                                  
-io_in[26]                                  |io_in[26]                                  
-io_in[2]                                   |io_in[2]                                   
-io_in[3]                                   |io_in[3]                                   
-io_in[4]                                   |io_in[4]                                   
-io_in[5]                                   |io_in[5]                                   
-io_in[6]                                   |io_in[6]                                   
-io_in[7]                                   |io_in[7]                                   
-io_in[8]                                   |io_in[8]                                   
-io_in[9]                                   |io_in[9]                                   
-io_in_3v3[0]                               |io_in_3v3[0]                               
-io_in_3v3[10]                              |io_in_3v3[10]                              
-io_in_3v3[11]                              |io_in_3v3[11]                              
-io_in_3v3[12]                              |io_in_3v3[12]                              
-io_in_3v3[13]                              |io_in_3v3[13]                              
-io_in_3v3[14]                              |io_in_3v3[14]                              
-io_in_3v3[15]                              |io_in_3v3[15]                              
-io_in_3v3[16]                              |io_in_3v3[16]                              
-io_in_3v3[17]                              |io_in_3v3[17]                              
-io_in_3v3[18]                              |io_in_3v3[18]                              
-io_in_3v3[19]                              |io_in_3v3[19]                              
-io_in_3v3[1]                               |io_in_3v3[1]                               
-io_in_3v3[20]                              |io_in_3v3[20]                              
-io_in_3v3[21]                              |io_in_3v3[21]                              
-io_in_3v3[22]                              |io_in_3v3[22]                              
-io_in_3v3[23]                              |io_in_3v3[23]                              
-io_in_3v3[24]                              |io_in_3v3[24]                              
-io_in_3v3[25]                              |io_in_3v3[25]                              
-io_in_3v3[26]                              |io_in_3v3[26]                              
-io_in_3v3[2]                               |io_in_3v3[2]                               
-io_in_3v3[3]                               |io_in_3v3[3]                               
-io_in_3v3[4]                               |io_in_3v3[4]                               
-io_in_3v3[5]                               |io_in_3v3[5]                               
-io_in_3v3[6]                               |io_in_3v3[6]                               
-io_in_3v3[7]                               |io_in_3v3[7]                               
-io_in_3v3[8]                               |io_in_3v3[8]                               
-io_in_3v3[9]                               |io_in_3v3[9]                               
-io_oeb[0]                                  |io_oeb[0]                                  
-io_oeb[10]                                 |io_oeb[10]                                 
-io_oeb[13]                                 |io_oeb[13]                                 
-io_oeb[14]                                 |io_oeb[14]                                 
-io_oeb[17]                                 |io_oeb[17]                                 
-io_oeb[18]                                 |io_oeb[18]                                 
-io_oeb[19]                                 |io_oeb[19]                                 
-io_oeb[1]                                  |io_oeb[1]                                  
-io_oeb[20]                                 |io_oeb[20]                                 
-io_oeb[21]                                 |io_oeb[21]                                 
-io_oeb[22]                                 |io_oeb[22]                                 
-io_oeb[23]                                 |io_oeb[23]                                 
-io_oeb[24]                                 |io_oeb[24]                                 
-io_oeb[25]                                 |io_oeb[25]                                 
-io_oeb[26]                                 |io_oeb[26]                                 
-io_oeb[2]                                  |io_oeb[2]                                  
-io_oeb[3]                                  |io_oeb[3]                                  
-io_oeb[4]                                  |io_oeb[4]                                  
-io_oeb[5]                                  |io_oeb[5]                                  
-io_oeb[6]                                  |io_oeb[6]                                  
-io_oeb[7]                                  |io_oeb[7]                                  
-io_oeb[8]                                  |io_oeb[8]                                  
-io_oeb[9]                                  |io_oeb[9]                                  
-io_out[0]                                  |io_out[0]                                  
-io_out[10]                                 |io_out[10]                                 
-io_out[13]                                 |io_out[13]                                 
-io_out[14]                                 |io_out[14]                                 
-io_out[17]                                 |io_out[17]                                 
-io_out[18]                                 |io_out[18]                                 
-io_out[19]                                 |io_out[19]                                 
-io_out[1]                                  |io_out[1]                                  
-io_out[20]                                 |io_out[20]                                 
-io_out[21]                                 |io_out[21]                                 
-io_out[22]                                 |io_out[22]                                 
-io_out[23]                                 |io_out[23]                                 
-io_out[24]                                 |io_out[24]                                 
-io_out[25]                                 |io_out[25]                                 
-io_out[26]                                 |io_out[26]                                 
-io_out[2]                                  |io_out[2]                                  
-io_out[3]                                  |io_out[3]                                  
-io_out[4]                                  |io_out[4]                                  
-io_out[5]                                  |io_out[5]                                  
-io_out[6]                                  |io_out[6]                                  
-io_out[7]                                  |io_out[7]                                  
-io_out[8]                                  |io_out[8]                                  
-io_out[9]                                  |io_out[9]                                  
-la_data_in[0]                              |la_data_in[0]                              
-la_data_in[100]                            |la_data_in[100]                            
-la_data_in[101]                            |la_data_in[101]                            
-la_data_in[102]                            |la_data_in[102]                            
-la_data_in[103]                            |la_data_in[103]                            
-la_data_in[104]                            |la_data_in[104]                            
-la_data_in[105]                            |la_data_in[105]                            
-la_data_in[106]                            |la_data_in[106]                            
-la_data_in[107]                            |la_data_in[107]                            
-la_data_in[108]                            |la_data_in[108]                            
-la_data_in[109]                            |la_data_in[109]                            
-la_data_in[10]                             |la_data_in[10]                             
-la_data_in[110]                            |la_data_in[110]                            
-la_data_in[111]                            |la_data_in[111]                            
-la_data_in[112]                            |la_data_in[112]                            
-la_data_in[113]                            |la_data_in[113]                            
-la_data_in[114]                            |la_data_in[114]                            
-la_data_in[115]                            |la_data_in[115]                            
-la_data_in[116]                            |la_data_in[116]                            
-la_data_in[117]                            |la_data_in[117]                            
-la_data_in[118]                            |la_data_in[118]                            
-la_data_in[119]                            |la_data_in[119]                            
-la_data_in[11]                             |la_data_in[11]                             
-la_data_in[120]                            |la_data_in[120]                            
-la_data_in[121]                            |la_data_in[121]                            
-la_data_in[122]                            |la_data_in[122]                            
-la_data_in[123]                            |la_data_in[123]                            
-la_data_in[124]                            |la_data_in[124]                            
-la_data_in[125]                            |la_data_in[125]                            
-la_data_in[126]                            |la_data_in[126]                            
-la_data_in[127]                            |la_data_in[127]                            
-la_data_in[12]                             |la_data_in[12]                             
-la_data_in[13]                             |la_data_in[13]                             
-la_data_in[14]                             |la_data_in[14]                             
-la_data_in[15]                             |la_data_in[15]                             
-la_data_in[16]                             |la_data_in[16]                             
-la_data_in[17]                             |la_data_in[17]                             
-la_data_in[18]                             |la_data_in[18]                             
-la_data_in[19]                             |la_data_in[19]                             
-la_data_in[1]                              |la_data_in[1]                              
-la_data_in[20]                             |la_data_in[20]                             
-la_data_in[21]                             |la_data_in[21]                             
-la_data_in[22]                             |la_data_in[22]                             
-la_data_in[23]                             |la_data_in[23]                             
-la_data_in[24]                             |la_data_in[24]                             
-la_data_in[25]                             |la_data_in[25]                             
-la_data_in[26]                             |la_data_in[26]                             
-la_data_in[27]                             |la_data_in[27]                             
-la_data_in[28]                             |la_data_in[28]                             
-la_data_in[29]                             |la_data_in[29]                             
-la_data_in[2]                              |la_data_in[2]                              
-la_data_in[30]                             |la_data_in[30]                             
-la_data_in[31]                             |la_data_in[31]                             
-la_data_in[32]                             |la_data_in[32]                             
-la_data_in[33]                             |la_data_in[33]                             
-la_data_in[34]                             |la_data_in[34]                             
-la_data_in[35]                             |la_data_in[35]                             
-la_data_in[36]                             |la_data_in[36]                             
-la_data_in[37]                             |la_data_in[37]                             
-la_data_in[38]                             |la_data_in[38]                             
-la_data_in[39]                             |la_data_in[39]                             
-la_data_in[3]                              |la_data_in[3]                              
-la_data_in[40]                             |la_data_in[40]                             
-la_data_in[41]                             |la_data_in[41]                             
-la_data_in[42]                             |la_data_in[42]                             
-la_data_in[43]                             |la_data_in[43]                             
-la_data_in[44]                             |la_data_in[44]                             
-la_data_in[45]                             |la_data_in[45]                             
-la_data_in[46]                             |la_data_in[46]                             
-la_data_in[47]                             |la_data_in[47]                             
-la_data_in[48]                             |la_data_in[48]                             
-la_data_in[49]                             |la_data_in[49]                             
-la_data_in[4]                              |la_data_in[4]                              
-la_data_in[50]                             |la_data_in[50]                             
-la_data_in[51]                             |la_data_in[51]                             
-la_data_in[52]                             |la_data_in[52]                             
-la_data_in[53]                             |la_data_in[53]                             
-la_data_in[54]                             |la_data_in[54]                             
-la_data_in[55]                             |la_data_in[55]                             
-la_data_in[56]                             |la_data_in[56]                             
-la_data_in[57]                             |la_data_in[57]                             
-la_data_in[58]                             |la_data_in[58]                             
-la_data_in[59]                             |la_data_in[59]                             
-la_data_in[5]                              |la_data_in[5]                              
-la_data_in[60]                             |la_data_in[60]                             
-la_data_in[61]                             |la_data_in[61]                             
-la_data_in[62]                             |la_data_in[62]                             
-la_data_in[63]                             |la_data_in[63]                             
-la_data_in[64]                             |la_data_in[64]                             
-la_data_in[65]                             |la_data_in[65]                             
-la_data_in[66]                             |la_data_in[66]                             
-la_data_in[67]                             |la_data_in[67]                             
-la_data_in[68]                             |la_data_in[68]                             
-la_data_in[69]                             |la_data_in[69]                             
-la_data_in[6]                              |la_data_in[6]                              
-la_data_in[70]                             |la_data_in[70]                             
-la_data_in[71]                             |la_data_in[71]                             
-la_data_in[72]                             |la_data_in[72]                             
-la_data_in[73]                             |la_data_in[73]                             
-la_data_in[74]                             |la_data_in[74]                             
-la_data_in[75]                             |la_data_in[75]                             
-la_data_in[76]                             |la_data_in[76]                             
-la_data_in[77]                             |la_data_in[77]                             
-la_data_in[78]                             |la_data_in[78]                             
-la_data_in[79]                             |la_data_in[79]                             
-la_data_in[7]                              |la_data_in[7]                              
-la_data_in[80]                             |la_data_in[80]                             
-la_data_in[81]                             |la_data_in[81]                             
-la_data_in[82]                             |la_data_in[82]                             
-la_data_in[83]                             |la_data_in[83]                             
-la_data_in[84]                             |la_data_in[84]                             
-la_data_in[85]                             |la_data_in[85]                             
-la_data_in[86]                             |la_data_in[86]                             
-la_data_in[87]                             |la_data_in[87]                             
-la_data_in[88]                             |la_data_in[88]                             
-la_data_in[89]                             |la_data_in[89]                             
-la_data_in[8]                              |la_data_in[8]                              
-la_data_in[90]                             |la_data_in[90]                             
-la_data_in[91]                             |la_data_in[91]                             
-la_data_in[92]                             |la_data_in[92]                             
-la_data_in[93]                             |la_data_in[93]                             
-la_data_in[94]                             |la_data_in[94]                             
-la_data_in[95]                             |la_data_in[95]                             
-la_data_in[96]                             |la_data_in[96]                             
-la_data_in[97]                             |la_data_in[97]                             
-la_data_in[98]                             |la_data_in[98]                             
-la_data_in[99]                             |la_data_in[99]                             
-la_data_in[9]                              |la_data_in[9]                              
-la_data_out[0]                             |la_data_out[0]                             
-la_data_out[100]                           |la_data_out[100]                           
-la_data_out[101]                           |la_data_out[101]                           
-la_data_out[102]                           |la_data_out[102]                           
-la_data_out[103]                           |la_data_out[103]                           
-la_data_out[104]                           |la_data_out[104]                           
-la_data_out[105]                           |la_data_out[105]                           
-la_data_out[106]                           |la_data_out[106]                           
-la_data_out[107]                           |la_data_out[107]                           
-la_data_out[108]                           |la_data_out[108]                           
-la_data_out[109]                           |la_data_out[109]                           
-la_data_out[10]                            |la_data_out[10]                            
-la_data_out[110]                           |la_data_out[110]                           
-la_data_out[111]                           |la_data_out[111]                           
-la_data_out[112]                           |la_data_out[112]                           
-la_data_out[113]                           |la_data_out[113]                           
-la_data_out[114]                           |la_data_out[114]                           
-la_data_out[115]                           |la_data_out[115]                           
-la_data_out[116]                           |la_data_out[116]                           
-la_data_out[117]                           |la_data_out[117]                           
-la_data_out[118]                           |la_data_out[118]                           
-la_data_out[119]                           |la_data_out[119]                           
-la_data_out[11]                            |la_data_out[11]                            
-la_data_out[120]                           |la_data_out[120]                           
-la_data_out[121]                           |la_data_out[121]                           
-la_data_out[122]                           |la_data_out[122]                           
-la_data_out[123]                           |la_data_out[123]                           
-la_data_out[124]                           |la_data_out[124]                           
-la_data_out[125]                           |la_data_out[125]                           
-la_data_out[126]                           |la_data_out[126]                           
-la_data_out[127]                           |la_data_out[127]                           
-la_data_out[12]                            |la_data_out[12]                            
-la_data_out[13]                            |la_data_out[13]                            
-la_data_out[14]                            |la_data_out[14]                            
-la_data_out[15]                            |la_data_out[15]                            
-la_data_out[16]                            |la_data_out[16]                            
-la_data_out[17]                            |la_data_out[17]                            
-la_data_out[18]                            |la_data_out[18]                            
-la_data_out[19]                            |la_data_out[19]                            
-la_data_out[1]                             |la_data_out[1]                             
-la_data_out[20]                            |la_data_out[20]                            
-la_data_out[21]                            |la_data_out[21]                            
-la_data_out[22]                            |la_data_out[22]                            
-la_data_out[23]                            |la_data_out[23]                            
-la_data_out[24]                            |la_data_out[24]                            
-la_data_out[25]                            |la_data_out[25]                            
-la_data_out[26]                            |la_data_out[26]                            
-la_data_out[27]                            |la_data_out[27]                            
-la_data_out[28]                            |la_data_out[28]                            
-la_data_out[29]                            |la_data_out[29]                            
-la_data_out[2]                             |la_data_out[2]                             
-la_data_out[30]                            |la_data_out[30]                            
-la_data_out[31]                            |la_data_out[31]                            
-la_data_out[32]                            |la_data_out[32]                            
-la_data_out[33]                            |la_data_out[33]                            
-la_data_out[34]                            |la_data_out[34]                            
-la_data_out[35]                            |la_data_out[35]                            
-la_data_out[36]                            |la_data_out[36]                            
-la_data_out[37]                            |la_data_out[37]                            
-la_data_out[38]                            |la_data_out[38]                            
-la_data_out[39]                            |la_data_out[39]                            
-la_data_out[3]                             |la_data_out[3]                             
-la_data_out[40]                            |la_data_out[40]                            
-la_data_out[41]                            |la_data_out[41]                            
-la_data_out[42]                            |la_data_out[42]                            
-la_data_out[43]                            |la_data_out[43]                            
-la_data_out[44]                            |la_data_out[44]                            
-la_data_out[45]                            |la_data_out[45]                            
-la_data_out[46]                            |la_data_out[46]                            
-la_data_out[47]                            |la_data_out[47]                            
-la_data_out[48]                            |la_data_out[48]                            
-la_data_out[49]                            |la_data_out[49]                            
-la_data_out[4]                             |la_data_out[4]                             
-la_data_out[50]                            |la_data_out[50]                            
-la_data_out[51]                            |la_data_out[51]                            
-la_data_out[52]                            |la_data_out[52]                            
-la_data_out[53]                            |la_data_out[53]                            
-la_data_out[54]                            |la_data_out[54]                            
-la_data_out[55]                            |la_data_out[55]                            
-la_data_out[56]                            |la_data_out[56]                            
-la_data_out[57]                            |la_data_out[57]                            
-la_data_out[58]                            |la_data_out[58]                            
-la_data_out[59]                            |la_data_out[59]                            
-la_data_out[5]                             |la_data_out[5]                             
-la_data_out[60]                            |la_data_out[60]                            
-la_data_out[61]                            |la_data_out[61]                            
-la_data_out[62]                            |la_data_out[62]                            
-la_data_out[63]                            |la_data_out[63]                            
-la_data_out[64]                            |la_data_out[64]                            
-la_data_out[65]                            |la_data_out[65]                            
-la_data_out[66]                            |la_data_out[66]                            
-la_data_out[67]                            |la_data_out[67]                            
-la_data_out[68]                            |la_data_out[68]                            
-la_data_out[69]                            |la_data_out[69]                            
-la_data_out[6]                             |la_data_out[6]                             
-la_data_out[70]                            |la_data_out[70]                            
-la_data_out[71]                            |la_data_out[71]                            
-la_data_out[72]                            |la_data_out[72]                            
-la_data_out[73]                            |la_data_out[73]                            
-la_data_out[74]                            |la_data_out[74]                            
-la_data_out[75]                            |la_data_out[75]                            
-la_data_out[76]                            |la_data_out[76]                            
-la_data_out[77]                            |la_data_out[77]                            
-la_data_out[78]                            |la_data_out[78]                            
-la_data_out[79]                            |la_data_out[79]                            
-la_data_out[7]                             |la_data_out[7]                             
-la_data_out[80]                            |la_data_out[80]                            
-la_data_out[81]                            |la_data_out[81]                            
-la_data_out[82]                            |la_data_out[82]                            
-la_data_out[83]                            |la_data_out[83]                            
-la_data_out[84]                            |la_data_out[84]                            
-la_data_out[85]                            |la_data_out[85]                            
-la_data_out[86]                            |la_data_out[86]                            
-la_data_out[87]                            |la_data_out[87]                            
-la_data_out[88]                            |la_data_out[88]                            
-la_data_out[89]                            |la_data_out[89]                            
-la_data_out[8]                             |la_data_out[8]                             
-la_data_out[90]                            |la_data_out[90]                            
-la_data_out[91]                            |la_data_out[91]                            
-la_data_out[92]                            |la_data_out[92]                            
-la_data_out[93]                            |la_data_out[93]                            
-la_data_out[94]                            |la_data_out[94]                            
-la_data_out[95]                            |la_data_out[95]                            
-la_data_out[96]                            |la_data_out[96]                            
-la_data_out[97]                            |la_data_out[97]                            
-la_data_out[98]                            |la_data_out[98]                            
-la_data_out[99]                            |la_data_out[99]                            
-la_data_out[9]                             |la_data_out[9]                             
-la_oenb[0]                                 |la_oenb[0]                                 
-la_oenb[100]                               |la_oenb[100]                               
-la_oenb[101]                               |la_oenb[101]                               
-la_oenb[102]                               |la_oenb[102]                               
-la_oenb[103]                               |la_oenb[103]                               
-la_oenb[104]                               |la_oenb[104]                               
-la_oenb[105]                               |la_oenb[105]                               
-la_oenb[106]                               |la_oenb[106]                               
-la_oenb[107]                               |la_oenb[107]                               
-la_oenb[108]                               |la_oenb[108]                               
-la_oenb[109]                               |la_oenb[109]                               
-la_oenb[10]                                |la_oenb[10]                                
-la_oenb[110]                               |la_oenb[110]                               
-la_oenb[111]                               |la_oenb[111]                               
-la_oenb[112]                               |la_oenb[112]                               
-la_oenb[113]                               |la_oenb[113]                               
-la_oenb[114]                               |la_oenb[114]                               
-la_oenb[115]                               |la_oenb[115]                               
-la_oenb[116]                               |la_oenb[116]                               
-la_oenb[117]                               |la_oenb[117]                               
-la_oenb[118]                               |la_oenb[118]                               
-la_oenb[119]                               |la_oenb[119]                               
-la_oenb[11]                                |la_oenb[11]                                
-la_oenb[120]                               |la_oenb[120]                               
-la_oenb[121]                               |la_oenb[121]                               
-la_oenb[122]                               |la_oenb[122]                               
-la_oenb[123]                               |la_oenb[123]                               
-la_oenb[124]                               |la_oenb[124]                               
-la_oenb[125]                               |la_oenb[125]                               
-la_oenb[126]                               |la_oenb[126]                               
-la_oenb[127]                               |la_oenb[127]                               
-la_oenb[12]                                |la_oenb[12]                                
-la_oenb[13]                                |la_oenb[13]                                
-la_oenb[14]                                |la_oenb[14]                                
-la_oenb[15]                                |la_oenb[15]                                
-la_oenb[16]                                |la_oenb[16]                                
-la_oenb[17]                                |la_oenb[17]                                
-la_oenb[18]                                |la_oenb[18]                                
-la_oenb[19]                                |la_oenb[19]                                
-la_oenb[1]                                 |la_oenb[1]                                 
-la_oenb[20]                                |la_oenb[20]                                
-la_oenb[21]                                |la_oenb[21]                                
-la_oenb[22]                                |la_oenb[22]                                
-la_oenb[23]                                |la_oenb[23]                                
-la_oenb[24]                                |la_oenb[24]                                
-la_oenb[25]                                |la_oenb[25]                                
-la_oenb[26]                                |la_oenb[26]                                
-la_oenb[27]                                |la_oenb[27]                                
-la_oenb[28]                                |la_oenb[28]                                
-la_oenb[29]                                |la_oenb[29]                                
-la_oenb[2]                                 |la_oenb[2]                                 
-la_oenb[30]                                |la_oenb[30]                                
-la_oenb[31]                                |la_oenb[31]                                
-la_oenb[32]                                |la_oenb[32]                                
-la_oenb[33]                                |la_oenb[33]                                
-la_oenb[34]                                |la_oenb[34]                                
-la_oenb[35]                                |la_oenb[35]                                
-la_oenb[36]                                |la_oenb[36]                                
-la_oenb[37]                                |la_oenb[37]                                
-la_oenb[38]                                |la_oenb[38]                                
-la_oenb[39]                                |la_oenb[39]                                
-la_oenb[3]                                 |la_oenb[3]                                 
-la_oenb[40]                                |la_oenb[40]                                
-la_oenb[41]                                |la_oenb[41]                                
-la_oenb[42]                                |la_oenb[42]                                
-la_oenb[43]                                |la_oenb[43]                                
-la_oenb[44]                                |la_oenb[44]                                
-la_oenb[45]                                |la_oenb[45]                                
-la_oenb[46]                                |la_oenb[46]                                
-la_oenb[47]                                |la_oenb[47]                                
-la_oenb[48]                                |la_oenb[48]                                
-la_oenb[49]                                |la_oenb[49]                                
-la_oenb[4]                                 |la_oenb[4]                                 
-la_oenb[50]                                |la_oenb[50]                                
-la_oenb[51]                                |la_oenb[51]                                
-la_oenb[52]                                |la_oenb[52]                                
-la_oenb[53]                                |la_oenb[53]                                
-la_oenb[54]                                |la_oenb[54]                                
-la_oenb[55]                                |la_oenb[55]                                
-la_oenb[56]                                |la_oenb[56]                                
-la_oenb[57]                                |la_oenb[57]                                
-la_oenb[58]                                |la_oenb[58]                                
-la_oenb[59]                                |la_oenb[59]                                
-la_oenb[5]                                 |la_oenb[5]                                 
-la_oenb[60]                                |la_oenb[60]                                
-la_oenb[61]                                |la_oenb[61]                                
-la_oenb[62]                                |la_oenb[62]                                
-la_oenb[63]                                |la_oenb[63]                                
-la_oenb[64]                                |la_oenb[64]                                
-la_oenb[65]                                |la_oenb[65]                                
-la_oenb[66]                                |la_oenb[66]                                
-la_oenb[67]                                |la_oenb[67]                                
-la_oenb[68]                                |la_oenb[68]                                
-la_oenb[69]                                |la_oenb[69]                                
-la_oenb[6]                                 |la_oenb[6]                                 
-la_oenb[70]                                |la_oenb[70]                                
-la_oenb[71]                                |la_oenb[71]                                
-la_oenb[72]                                |la_oenb[72]                                
-la_oenb[73]                                |la_oenb[73]                                
-la_oenb[74]                                |la_oenb[74]                                
-la_oenb[75]                                |la_oenb[75]                                
-la_oenb[76]                                |la_oenb[76]                                
-la_oenb[77]                                |la_oenb[77]                                
-la_oenb[78]                                |la_oenb[78]                                
-la_oenb[79]                                |la_oenb[79]                                
-la_oenb[7]                                 |la_oenb[7]                                 
-la_oenb[80]                                |la_oenb[80]                                
-la_oenb[81]                                |la_oenb[81]                                
-la_oenb[82]                                |la_oenb[82]                                
-la_oenb[83]                                |la_oenb[83]                                
-la_oenb[84]                                |la_oenb[84]                                
-la_oenb[85]                                |la_oenb[85]                                
-la_oenb[86]                                |la_oenb[86]                                
-la_oenb[87]                                |la_oenb[87]                                
-la_oenb[88]                                |la_oenb[88]                                
-la_oenb[89]                                |la_oenb[89]                                
-la_oenb[8]                                 |la_oenb[8]                                 
-la_oenb[90]                                |la_oenb[90]                                
-la_oenb[91]                                |la_oenb[91]                                
-la_oenb[92]                                |la_oenb[92]                                
-la_oenb[93]                                |la_oenb[93]                                
-la_oenb[94]                                |la_oenb[94]                                
-la_oenb[95]                                |la_oenb[95]                                
-la_oenb[96]                                |la_oenb[96]                                
-la_oenb[97]                                |la_oenb[97]                                
-la_oenb[98]                                |la_oenb[98]                                
-la_oenb[99]                                |la_oenb[99]                                
-la_oenb[9]                                 |la_oenb[9]                                 
-user_clock2                                |user_clock2                                
-user_irq[0]                                |user_irq[0]                                
-user_irq[1]                                |user_irq[1]                                
-user_irq[2]                                |user_irq[2]                                
-vccd2                                      |vccd2                                      
-vdda2                                      |vdda2                                      
-vssa2                                      |vssa2                                      
-vssd2                                      |vssd2                                      
-wb_clk_i                                   |wb_clk_i                                   
-wb_rst_i                                   |wb_rst_i                                   
-wbs_ack_o                                  |wbs_ack_o                                  
-wbs_adr_i[0]                               |wbs_adr_i[0]                               
-wbs_adr_i[10]                              |wbs_adr_i[10]                              
-wbs_adr_i[11]                              |wbs_adr_i[11]                              
-wbs_adr_i[12]                              |wbs_adr_i[12]                              
-wbs_adr_i[13]                              |wbs_adr_i[13]                              
-wbs_adr_i[14]                              |wbs_adr_i[14]                              
-wbs_adr_i[15]                              |wbs_adr_i[15]                              
-wbs_adr_i[16]                              |wbs_adr_i[16]                              
-wbs_adr_i[17]                              |wbs_adr_i[17]                              
-wbs_adr_i[18]                              |wbs_adr_i[18]                              
-wbs_adr_i[19]                              |wbs_adr_i[19]                              
-wbs_adr_i[1]                               |wbs_adr_i[1]                               
-wbs_adr_i[20]                              |wbs_adr_i[20]                              
-wbs_adr_i[21]                              |wbs_adr_i[21]                              
-wbs_adr_i[22]                              |wbs_adr_i[22]                              
-wbs_adr_i[23]                              |wbs_adr_i[23]                              
-wbs_adr_i[24]                              |wbs_adr_i[24]                              
-wbs_adr_i[25]                              |wbs_adr_i[25]                              
-wbs_adr_i[26]                              |wbs_adr_i[26]                              
-wbs_adr_i[27]                              |wbs_adr_i[27]                              
-wbs_adr_i[28]                              |wbs_adr_i[28]                              
-wbs_adr_i[29]                              |wbs_adr_i[29]                              
-wbs_adr_i[2]                               |wbs_adr_i[2]                               
-wbs_adr_i[30]                              |wbs_adr_i[30]                              
-wbs_adr_i[31]                              |wbs_adr_i[31]                              
-wbs_adr_i[3]                               |wbs_adr_i[3]                               
-wbs_adr_i[4]                               |wbs_adr_i[4]                               
-wbs_adr_i[5]                               |wbs_adr_i[5]                               
-wbs_adr_i[6]                               |wbs_adr_i[6]                               
-wbs_adr_i[7]                               |wbs_adr_i[7]                               
-wbs_adr_i[8]                               |wbs_adr_i[8]                               
-wbs_adr_i[9]                               |wbs_adr_i[9]                               
-wbs_cyc_i                                  |wbs_cyc_i                                  
-wbs_dat_i[0]                               |wbs_dat_i[0]                               
-wbs_dat_i[10]                              |wbs_dat_i[10]                              
-wbs_dat_i[11]                              |wbs_dat_i[11]                              
-wbs_dat_i[12]                              |wbs_dat_i[12]                              
-wbs_dat_i[13]                              |wbs_dat_i[13]                              
-wbs_dat_i[14]                              |wbs_dat_i[14]                              
-wbs_dat_i[15]                              |wbs_dat_i[15]                              
-wbs_dat_i[16]                              |wbs_dat_i[16]                              
-wbs_dat_i[17]                              |wbs_dat_i[17]                              
-wbs_dat_i[18]                              |wbs_dat_i[18]                              
-wbs_dat_i[19]                              |wbs_dat_i[19]                              
-wbs_dat_i[1]                               |wbs_dat_i[1]                               
-wbs_dat_i[20]                              |wbs_dat_i[20]                              
-wbs_dat_i[21]                              |wbs_dat_i[21]                              
-wbs_dat_i[22]                              |wbs_dat_i[22]                              
-wbs_dat_i[23]                              |wbs_dat_i[23]                              
-wbs_dat_i[24]                              |wbs_dat_i[24]                              
-wbs_dat_i[25]                              |wbs_dat_i[25]                              
-wbs_dat_i[26]                              |wbs_dat_i[26]                              
-wbs_dat_i[27]                              |wbs_dat_i[27]                              
-wbs_dat_i[28]                              |wbs_dat_i[28]                              
-wbs_dat_i[29]                              |wbs_dat_i[29]                              
-wbs_dat_i[2]                               |wbs_dat_i[2]                               
-wbs_dat_i[30]                              |wbs_dat_i[30]                              
-wbs_dat_i[31]                              |wbs_dat_i[31]                              
-wbs_dat_i[3]                               |wbs_dat_i[3]                               
-wbs_dat_i[4]                               |wbs_dat_i[4]                               
-wbs_dat_i[5]                               |wbs_dat_i[5]                               
-wbs_dat_i[6]                               |wbs_dat_i[6]                               
-wbs_dat_i[7]                               |wbs_dat_i[7]                               
-wbs_dat_i[8]                               |wbs_dat_i[8]                               
-wbs_dat_i[9]                               |wbs_dat_i[9]                               
-wbs_dat_o[0]                               |wbs_dat_o[0]                               
-wbs_dat_o[10]                              |wbs_dat_o[10]                              
-wbs_dat_o[11]                              |wbs_dat_o[11]                              
-wbs_dat_o[12]                              |wbs_dat_o[12]                              
-wbs_dat_o[13]                              |wbs_dat_o[13]                              
-wbs_dat_o[14]                              |wbs_dat_o[14]                              
-wbs_dat_o[15]                              |wbs_dat_o[15]                              
-wbs_dat_o[16]                              |wbs_dat_o[16]                              
-wbs_dat_o[17]                              |wbs_dat_o[17]                              
-wbs_dat_o[18]                              |wbs_dat_o[18]                              
-wbs_dat_o[19]                              |wbs_dat_o[19]                              
-wbs_dat_o[1]                               |wbs_dat_o[1]                               
-wbs_dat_o[20]                              |wbs_dat_o[20]                              
-wbs_dat_o[21]                              |wbs_dat_o[21]                              
-wbs_dat_o[22]                              |wbs_dat_o[22]                              
-wbs_dat_o[23]                              |wbs_dat_o[23]                              
-wbs_dat_o[24]                              |wbs_dat_o[24]                              
-wbs_dat_o[25]                              |wbs_dat_o[25]                              
-wbs_dat_o[26]                              |wbs_dat_o[26]                              
-wbs_dat_o[27]                              |wbs_dat_o[27]                              
-wbs_dat_o[28]                              |wbs_dat_o[28]                              
-wbs_dat_o[29]                              |wbs_dat_o[29]                              
-wbs_dat_o[2]                               |wbs_dat_o[2]                               
-wbs_dat_o[30]                              |wbs_dat_o[30]                              
-wbs_dat_o[31]                              |wbs_dat_o[31]                              
-wbs_dat_o[3]                               |wbs_dat_o[3]                               
-wbs_dat_o[4]                               |wbs_dat_o[4]                               
-wbs_dat_o[5]                               |wbs_dat_o[5]                               
-wbs_dat_o[6]                               |wbs_dat_o[6]                               
-wbs_dat_o[7]                               |wbs_dat_o[7]                               
-wbs_dat_o[8]                               |wbs_dat_o[8]                               
-wbs_dat_o[9]                               |wbs_dat_o[9]                               
-wbs_sel_i[0]                               |wbs_sel_i[0]                               
-wbs_sel_i[1]                               |wbs_sel_i[1]                               
-wbs_sel_i[2]                               |wbs_sel_i[2]                               
-wbs_sel_i[3]                               |wbs_sel_i[3]                               
-wbs_stb_i                                  |wbs_stb_i                                  
-wbs_we_i                                   |wbs_we_i                                   
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes user_analog_project_wrapper and user_analog_project_wrapper are equivalent.
-Circuits match uniquely.
diff --git a/netgen/example_por.spice b/netgen/example_por.spice
deleted file mode 100644
index 499f397..0000000
--- a/netgen/example_por.spice
+++ /dev/null
@@ -1,213 +0,0 @@
-* NGSPICE file created from example_por.ext - technology: sky130A
-
-.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW VSUBS m4_n3179_n3100# c2_n3079_n3000#
-X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
-.ends
-
-.subckt sky130_fd_sc_hvl__buf_8 A VGND VNB VPB VPWR X
-X0 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=2.9175e+12p pd=2.189e+07u as=8.475e+11p ps=7.13e+06u w=1.5e+06u l=500000u
-X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.45875e+12p pd=1.289e+07u as=8.4e+11p ps=8.24e+06u w=750000u l=500000u
-X2 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.68e+12p ps=1.424e+07u w=1.5e+06u l=500000u
-X3 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X4 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X5 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=4.2375e+11p pd=4.13e+06u as=0p ps=0u w=750000u l=500000u
-X6 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X9 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X10 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X12 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X14 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X15 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X16 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X18 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X19 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X20 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X21 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ VSUBS a_n465_n200# a_n247_n200# a_n29_n200#
-+ a_843_n200# w_n1101_n497# a_n843_n297# a_625_n200# a_683_n297# a_n625_n297# a_407_n200#
-+ a_465_n297# a_n407_n297# a_247_n297# a_n901_n200# a_189_n200# a_29_n297# a_n189_n297#
-+ a_n683_n200#
-X0 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X2 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X4 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
-X6 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X7 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n80_n288# a_n574_n200# a_n356_n200#
-+ a_n138_n200# a_n734_n288# a_574_n288# a_n516_n288# a_356_n288# a_80_n200# a_n298_n288#
-+ a_138_n288# w_n962_n458# a_734_n200# a_516_n200# a_298_n200# a_n792_n200#
-X0 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X2 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X3 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X4 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
-X6 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n2578_n2932# a_5142_2500# a_n1034_n2932#
-+ a_n262_2500# a_1668_2500# a_n262_n2932# a_n3736_2500# a_3984_n2932# a_n2192_2500#
-+ a_3984_2500# a_2440_n2932# a_2440_2500# a_4370_n2932# a_3598_2500# a_2054_2500#
-+ a_n4508_n2932# a_510_2500# a_n4122_2500# a_n2964_n2932# a_124_2500# a_n4894_n2932#
-+ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_4370_2500# a_n3350_n2932# a_n648_n2932#
-+ a_n648_2500# a_n5280_n2932# a_n1420_2500# a_n2964_2500# a_n2578_2500# a_n1034_2500#
-+ a_2826_n2932# a_n2192_n2932# a_2826_2500# a_4756_n2932# w_n5446_n3098# a_1282_2500#
-+ a_3212_n2932# a_n4894_2500# a_n3350_2500# a_n4508_2500# a_5142_n2932# a_896_2500#
-+ a_510_n2932# a_1668_n2932# a_n1806_n2932# a_4756_2500# a_n3736_n2932# a_3598_n2932#
-+ a_3212_2500# a_2054_n2932# a_896_n2932# a_n5280_2500# a_n4122_n2932# a_n1806_2500#
-X0 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X1 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X2 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X3 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X4 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X5 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X6 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X7 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X8 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X9 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X10 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X11 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X12 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X13 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X14 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X15 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X16 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X17 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X18 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X19 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X20 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X21 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X22 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X23 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X24 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X25 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X26 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X27 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB VSUBS a_n138_n200# w_n338_n497# a_80_n200#
-+ a_n80_n297#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VNB VPB VPWR X
-X0 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
-X1 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=4.0875e+11p pd=4.09e+06u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
-X2 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=2.289e+11p pd=2.77e+06u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
-X3 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.02225e+12p pd=5.2e+06u as=0p ps=0u w=750000u l=500000u
-X4 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
-X5 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.9875e+11p pd=2.03e+06u as=9.478e+11p ps=4.36e+06u w=750000u l=500000u
-X6 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
-X7 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=3.975e+11p pd=3.53e+06u as=0p ps=0u w=1.5e+06u l=500000u
-X8 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-X9 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE VSUBS a_n138_n200# w_n338_n497# a_80_n200#
-+ a_n80_n297#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW VSUBS m3_n3136_n3100# c1_n3036_n3000#
-X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV VSUBS w_n992_n497# a_n574_n200# a_n356_n200#
-+ a_n138_n200# a_80_n200# a_n80_n297# a_734_n200# a_n734_n297# a_516_n200# a_574_n297#
-+ a_n516_n297# a_356_n297# a_298_n200# a_n298_n297# a_138_n297# a_n792_n200#
-X0 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X1 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X2 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
-X3 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X4 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X5 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-X6 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG VSUBS a_n138_n200# w_n338_n497# a_80_n200#
-+ a_n80_n297#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_sc_hvl__inv_8 A VGND VNB VPB VPWR Y
-X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.68e+12p pd=1.424e+07u as=2.055e+12p ps=1.774e+07u w=1.5e+06u l=500000u
-X1 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=8.4e+11p pd=8.24e+06u as=1.14e+12p ps=1.054e+07u w=750000u l=500000u
-X2 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X3 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X4 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X5 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X6 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X7 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X9 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X10 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X11 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X13 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-.ends
-
-.subckt example_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
-Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_2_W5U4AW
-Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 porb_l
-+ sky130_fd_sc_hvl__buf_8
-Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 vss vdd3v3 m1_502_7653# vdd3v3 vdd3v3 vdd3v3
-+ m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653#
-+ m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
-Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss m1_721_6815#
-+ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
-+ vss m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
-Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_2935_165# vss li_4479_165# li_4866_5813#
-+ li_7182_5813# li_5251_165# li_1778_5813# li_9111_165# li_3322_5813# li_9498_5813#
-+ li_7567_165# li_7954_5813# li_9883_165# li_8726_5813# li_7182_5813# li_619_165#
-+ li_5638_5813# li_1006_5813# li_2163_165# li_5638_5813# li_619_165# li_6795_165#
-+ li_5251_165# li_3707_165# li_9498_5813# li_2163_165# li_4479_165# li_4866_5813#
-+ vss li_4094_5813# li_2550_5813# li_2550_5813# li_4094_5813# li_8339_165# li_2935_165#
-+ li_7954_5813# li_9883_165# vss li_6410_5813# li_8339_165# vss li_1778_5813# li_1006_5813#
-+ vss li_6410_5813# li_6023_165# li_6795_165# li_3707_165# vdd3v3 li_1391_165# li_9111_165#
-+ li_8726_5813# li_7567_165# li_6023_165# vss li_1391_165# li_3322_5813# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 vss m1_2993_7658# vdd3v3 m1_721_6815# m1_185_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss vdd3v3
-+ vdd3v3 sky130_fd_sc_hvl__inv_8_0/A sky130_fd_sc_hvl__schmittbuf_1
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 vss m1_2756_6573# vdd3v3 m1_4283_8081# m1_2756_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 vss m1_6249_7690# vdd3v3 sky130_fd_sc_hvl__schmittbuf_1_0/A
-+ m1_2756_6573# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 vss m1_185_6573# vdd3v3 m1_502_7653# m1_185_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 vss vdd3v3 vdd3v3 m1_6249_7690# m1_4283_8081#
-+ sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
-Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 m1_721_6815# vss m1_2756_6573# vss sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
-Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 li_2550_5813# vss m1_185_6573# vss sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
-Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 vss vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_1_WRT4AW
-Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vss vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081#
-+ vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081#
-+ m1_4283_8081# m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 vss vdd3v3 vdd3v3 m1_2993_7658# m1_502_7653#
-+ sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
-Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 por_l
-+ sky130_fd_sc_hvl__inv_8
-Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd3v3 vdd3v3 porb_h
-+ sky130_fd_sc_hvl__buf_8
-.ends
-
diff --git a/netgen/run_lvs_por.sh b/netgen/run_lvs_por.sh
deleted file mode 100755
index be822b5..0000000
--- a/netgen/run_lvs_por.sh
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/bin/sh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-#--------------------------------------------------------------------------------
-# Run LVS on the example_por layout
-#
-# NOTE:  By specifying the testbench for the schematic-side netlist, the proper
-# includes used by the testbench simulation are picked up.  Otherwise, the LVS
-# itself compares just the simple_por subcircuit from the testbench.
-#--------------------------------------------------------------------------------
-netgen -batch lvs "example_por.spice example_por" "../xschem/example_por_tb.spice example_por" $PDK_ROOT/$PDK/libs.tech/netgen/$PDK\_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_verilog.sh b/netgen/run_lvs_wrapper_verilog.sh
deleted file mode 100755
index 5c63236..0000000
--- a/netgen/run_lvs_wrapper_verilog.sh
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/sh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-#--------------------------------------------------------------------------------
-# Run LVS on the user_analog_project_wrapper layout, comparing against the
-# top-level verilog module.
-#
-#--------------------------------------------------------------------------------
-netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../verilog/rtl/user_analog_project_wrapper.v user_analog_project_wrapper" $PDK_ROOT/$PDK/libs.tech/netgen/$PDK\_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_xschem.sh b/netgen/run_lvs_wrapper_xschem.sh
deleted file mode 100755
index 2fa97c0..0000000
--- a/netgen/run_lvs_wrapper_xschem.sh
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/sh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-#--------------------------------------------------------------------------------
-# Run LVS on the user_analog_project_wrapper layout, comparing against the
-# top-level xschem subcircuit from the wrapper testbench.
-#
-#--------------------------------------------------------------------------------
-netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../xschem/analog_wrapper_tb.spice user_analog_project_wrapper" $PDK_ROOT/$PDK/libs.tech/netgen/$PDK\_setup.tcl comp.out
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index c3851a3..6776910 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -1,217 +1,120 @@
-* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+* partial top level spice netlist
 
-.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW c2_n3079_n3000# m4_n3179_n3100#
-X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.subckt ConnectedSRAM
+
 .ends
 
-.subckt sky130_fd_sc_hvl__buf_8 A VGND VPWR X VNB VPB
-X0 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X2 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X3 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X4 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X5 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X6 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X9 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X10 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X12 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X14 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X15 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X16 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X18 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X19 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X20 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X21 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.subckt ConnectedBandGap
+
 .ends
 
-.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ a_n683_n200# a_n189_n297# a_29_n297# a_189_n200#
-+ a_n901_n200# a_247_n297# a_n407_n297# a_465_n297# a_407_n200# a_n625_n297# a_683_n297#
-+ a_625_n200# a_n843_n297# w_n1101_n497# a_843_n200# a_n29_n200# a_n247_n200# a_n465_n200#
-X0 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X7 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
+.subckt user_analog_project_wrapper_empty gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
 
-.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n792_n200# a_298_n200# a_516_n200# a_734_n200#
-+ w_n962_n458# a_138_n288# a_n298_n288# a_80_n200# a_356_n288# a_n516_n288# a_574_n288#
-+ a_n734_n288# a_n138_n200# a_n356_n200# a_n574_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n1806_2500# a_n4122_n2932# a_n5280_2500#
-+ a_2054_n2932# a_896_n2932# a_4756_2500# a_3598_n2932# a_3212_2500# a_n3736_n2932#
-+ a_1668_n2932# a_n1806_n2932# a_5142_n2932# a_896_2500# a_510_n2932# a_n3350_2500#
-+ a_n4508_2500# a_3212_n2932# a_n4894_2500# a_1282_2500# w_n5446_n3098# a_4756_n2932#
-+ a_2826_2500# a_2826_n2932# a_n2192_n2932# a_n1034_2500# a_n2578_2500# a_n1420_2500#
-+ a_n2964_2500# a_n648_n2932# a_n648_2500# a_n5280_n2932# a_n3350_n2932# a_4370_2500#
-+ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_n4894_n2932# a_124_2500# a_n2964_n2932#
-+ a_n4122_2500# a_2054_2500# a_510_2500# a_n4508_n2932# a_4370_n2932# a_3598_2500#
-+ a_3984_2500# a_2440_n2932# a_2440_2500# a_3984_n2932# a_n2192_2500# a_n3736_2500#
-+ a_1668_2500# a_n262_n2932# a_n262_2500# a_n1034_n2932# a_5142_2500# a_n2578_n2932#
-X0 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X1 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
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-X4 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X5 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X6 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X7 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X8 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X9 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X10 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X11 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X12 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X13 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X14 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
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-X20 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
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-X23 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X24 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X25 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X26 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X27 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VPWR X VNB VPB
-X0 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X1 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-X2 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X3 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-X4 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
-X5 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
-X6 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X7 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X9 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW c1_n3036_n3000# m3_n3136_n3100#
-X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV a_n792_n200# a_138_n297# a_n298_n297#
-+ a_298_n200# a_356_n297# a_n516_n297# a_574_n297# a_516_n200# a_n734_n297# a_734_n200#
-+ a_n80_n297# a_80_n200# a_n138_n200# a_n356_n200# a_n574_n200# w_n992_n497#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-.ends
-
-.subckt sky130_fd_sc_hvl__inv_8 A VGND VPWR Y VNB VPB
-X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X1 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X2 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X3 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X4 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X5 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X6 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X7 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X9 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X10 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X11 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X13 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-.ends
-
-.subckt example_por vdd3v3 vss porb_h por_l porb_l vdd1v8
-Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_2_W5U4AW
-Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 porb_l vss vdd1v8
-+ sky130_fd_sc_hvl__buf_8
-Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653#
-+ vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653#
-+ m1_502_7653# vdd3v3 vdd3v3 vdd3v3 m1_502_7653# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
-Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss vss m1_721_6815#
-+ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
-+ m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
-Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_3322_5813# li_1391_165# vss li_7567_165#
-+ li_6023_165# vdd3v3 li_9111_165# li_8726_5813# li_1391_165# li_6795_165# li_3707_165#
-+ vss li_6410_5813# li_6023_165# li_1778_5813# li_1006_5813# li_8339_165# vss li_6410_5813#
-+ vss li_9883_165# li_7954_5813# li_8339_165# li_2935_165# li_4094_5813# li_2550_5813#
-+ li_4094_5813# li_2550_5813# li_4479_165# li_4866_5813# vss li_2163_165# li_9498_5813#
-+ li_6795_165# li_5251_165# li_3707_165# li_619_165# li_5638_5813# li_2163_165# li_1006_5813#
-+ li_7182_5813# li_5638_5813# li_619_165# li_9883_165# li_8726_5813# li_9498_5813#
-+ li_7567_165# li_7954_5813# li_9111_165# li_3322_5813# li_1778_5813# li_7182_5813#
-+ li_5251_165# li_4866_5813# li_4479_165# vss li_2935_165# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 m1_185_6573# m1_721_6815# vdd3v3 m1_2993_7658#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vdd3v3 sky130_fd_sc_hvl__inv_8_0/A
-+ vss vdd3v3 sky130_fd_sc_hvl__schmittbuf_1
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 m1_2756_6573# m1_4283_8081# vdd3v3 m1_2756_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 m1_2756_6573# sky130_fd_sc_hvl__schmittbuf_1_0/A
-+ vdd3v3 m1_6249_7690# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 m1_185_6573# m1_502_7653# vdd3v3 m1_185_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 m1_4283_8081# m1_6249_7690# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
-Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 vss m1_2756_6573# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
-Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 vss m1_185_6573# vss li_2550_5813# sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
-Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_1_WRT4AW
-Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
-+ m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
-+ vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 m1_502_7653# m1_2993_7658# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
-Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 por_l vss vdd1v8
-+ sky130_fd_sc_hvl__inv_8
-Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd3v3 porb_h vss vdd3v3
-+ sky130_fd_sc_hvl__buf_8
-.ends
-
-.subckt user_analog_proj_example example_por_0/por_l example_por_1/por_l example_por_1/vdd3v3
-+ example_por_1/porb_l example_por_0/vdd3v3 example_por_1/porb_h example_por_0/porb_l
-+ example_por_0/porb_h VSUBS example_por_0/vdd1v8 example_por_1/vdd1v8
-Xexample_por_0 example_por_0/vdd3v3 VSUBS example_por_0/porb_h example_por_0/por_l
-+ example_por_0/porb_l example_por_0/vdd1v8 example_por
-Xexample_por_1 example_por_1/vdd3v3 VSUBS example_por_1/porb_h example_por_1/por_l
-+ example_por_1/porb_l example_por_1/vdd1v8 example_por
 .ends
 
 .subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
@@ -320,17 +223,121 @@
 + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
 + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
 + wbs_stb_i wbs_we_i
-Xuser_analog_proj_example_0 io_out[16] io_out[12] vdda1 io_out[11] io_analog[4] gpio_analog[3]
-+ io_out[15] gpio_analog[7] vssa1 vccd1 vccd1 user_analog_proj_example
-R0 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R1 io_oeb[15] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=600000u
-R2 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R3 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 w=560000u l=580000u
-R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R5 io_oeb[16] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=310000u
-R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R7 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 w=560000u l=490000u
-R8 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R9 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-.ends
 
+Xsram io_in[0] io_in[1] io_out[2] io_in[3] io_out[4] io_in[5] io_out[6] io_in[7]
++ io_out[8] io_in[9] io_out[10] io_in[11] io_out[12] io_in[13] io_in[14] io_in[15]
++ io_in[16] io_in[17] io_in[18] io_in[19] io_in[20] io_in[21] io_in[22] io_in[23]
++ io_out[24] io_in[25] io_out[26]
++ io_analog[4] io_analog[5]
++ ConnectedSRAM
+
+Xbg io_analog[7] io_analog[9] io_analog[8] ConnectedBandGap
+
+Xempty gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i user_analog_project_wrapper_empty
+
+.ends
diff --git a/openlane/.gitignore b/openlane/.gitignore
deleted file mode 100644
index e4867d8..0000000
--- a/openlane/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-*/runs
-default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
deleted file mode 120000
index 48e5b4a..0000000
--- a/openlane/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/top.png b/top.png
new file mode 100644
index 0000000..ed47d60
--- /dev/null
+++ b/top.png
Binary files differ
diff --git a/user_analog_project_wrapper.png b/user_analog_project_wrapper.png
new file mode 100644
index 0000000..6d6c3cc
--- /dev/null
+++ b/user_analog_project_wrapper.png
Binary files differ
diff --git a/verilog/rtl/blocks.v b/verilog/rtl/blocks.v
new file mode 100644
index 0000000..f8a982d
--- /dev/null
+++ b/verilog/rtl/blocks.v
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: LGPL-2.1-or-later
+`timesacle 1 ns / 1 ps
+
+module ConnectedSRAM (
+    inout vss,
+    inout vdd
+);
+
+endmodule
+
+module ConnectedBandGap (
+    inout vss,
+    inout vdd,
+    out vref
+);
+
+endmodule
+
+
+module user_analog_project_wrapper_empty (
+    inout vdda1,
+    inout vdda2,
+    inout vssa1,
+    inout vssa2,
+    inout vccd1,
+    inout vccd2,
+    inout vssd1,
+    inout vssd2,
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    // GPIOs
+    input  [26:0] io_in,
+    input  [26:0] io_in_3v3,
+    output [26:0] io_out,
+    output [26:0] io_oeb,
+
+    // GPIO-analog
+    inout [17:0] gpio_analog,
+    inout [17:0] gpio_noesd,
+
+    // Dedicate analog
+    inout [10:0] io_analog,
+
+    // Additional power supply ESD clamps
+    inout [2:0] io_clamp_high,
+    inout [2:0] io_clamp_low,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+endmodule // user_analog_project_wrapper_empty
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
deleted file mode 100644
index d318fba..0000000
--- a/verilog/rtl/example_por.v
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-`timescale 1 ns / 1 ps
-
-// This is just a copy of simple_por.v from the Caravel project, used
-// as an analog user project example.
-
-module example_por(
-`ifdef USE_POWER_PINS
-    inout vdd3v3,
-    inout vdd1v8,
-    inout vss,
-`endif
-    output porb_h,
-    output porb_l,
-    output por_l
-);
-
-    wire mid, porb_h;
-    reg inode;
-
-    // This is a behavioral model!  Actual circuit is a resitor dumping
-    // current (slowly) from vdd3v3 onto a capacitor, and this fed into
-    // two schmitt triggers for strong hysteresis/glitch tolerance.
-
-    initial begin
-	inode <= 1'b0; 
-    end 
-
-    // Emulate current source on capacitor as a 500ns delay either up or
-    // down.  Note that this is sped way up for verilog simulation;  the
-    // actual circuit is set to a 15ms delay.
-
-    always @(posedge vdd3v3) begin
-	#500 inode <= 1'b1;
-    end
-    always @(negedge vdd3v3) begin
-	#500 inode <= 1'b0;
-    end
-
-    // Instantiate two shmitt trigger buffers in series
-
-    sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
-`ifdef USE_POWER_PINS
-	.VPWR(vdd3v3),
-	.VGND(vss),
-	.VPB(vdd3v3),
-	.VNB(vss),
-`endif
-	.A(inode),
-	.X(mid)
-    );
-
-    sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
-`ifdef USE_POWER_PINS
-	.VPWR(vdd3v3),
-	.VGND(vss),
-	.VPB(vdd3v3),
-	.VNB(vss),
-`endif
-	.A(mid),
-	.X(porb_h)
-    );
-
-    sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
-`ifdef USE_POWER_PINS
-	.VPWR(vdd3v3),
-	.VPB(vdd3v3),
-	.LVPWR(vdd1v8),
-	.VNB(vss),
-	.VGND(vss),
-`endif
-	.A(porb_h),
-	.X(porb_l)
-    );
-
-    // since this is behavioral anyway, but this should be
-    // replaced by a proper inverter
-    assign por_l = ~porb_l;
-endmodule
-`default_nettype wire
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v
index 062a873..907ecb5 100644
--- a/verilog/rtl/uprj_analog_netlists.v
+++ b/verilog/rtl/uprj_analog_netlists.v
@@ -31,8 +31,8 @@
     `default_nettype wire
     // Use behavorial model with gate-level simulation
     `include "rtl/user_analog_project_wrapper.v"
-    `include "rtl/user_analog_proj_example.v"
+    `include "rtl/blocks.v"
 `else
     `include "user_analog_project_wrapper.v"
-    `include "user_analog_proj_example.v"
+    `include "blocks.v"
 `endif
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
deleted file mode 100644
index 94412da..0000000
--- a/verilog/rtl/user_analog_proj_example.v
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`include "example_por.v"
-
-/*
- * I/O mapping for analog
- *
- * mprj_io[37]  io_in/out/oeb/in_3v3[26]  ---                    ---
- * mprj_io[36]  io_in/out/oeb/in_3v3[25]  ---                    ---
- * mprj_io[35]  io_in/out/oeb/in_3v3[24]  gpio_analog/noesd[17]  ---
- * mprj_io[34]  io_in/out/oeb/in_3v3[23]  gpio_analog/noesd[16]  ---
- * mprj_io[33]  io_in/out/oeb/in_3v3[22]  gpio_analog/noesd[15]  ---
- * mprj_io[32]  io_in/out/oeb/in_3v3[21]  gpio_analog/noesd[14]  ---
- * mprj_io[31]  io_in/out/oeb/in_3v3[20]  gpio_analog/noesd[13]  ---
- * mprj_io[30]  io_in/out/oeb/in_3v3[19]  gpio_analog/noesd[12]  ---
- * mprj_io[29]  io_in/out/oeb/in_3v3[18]  gpio_analog/noesd[11]  ---
- * mprj_io[28]  io_in/out/oeb/in_3v3[17]  gpio_analog/noesd[10]  ---
- * mprj_io[27]  io_in/out/oeb/in_3v3[16]  gpio_analog/noesd[9]   ---
- * mprj_io[26]  io_in/out/oeb/in_3v3[15]  gpio_analog/noesd[8]   ---
- * mprj_io[25]  io_in/out/oeb/in_3v3[14]  gpio_analog/noesd[7]   ---
- * mprj_io[24]  ---                       ---                    user_analog[10]
- * mprj_io[23]  ---                       ---                    user_analog[9]
- * mprj_io[22]  ---                       ---                    user_analog[8]
- * mprj_io[21]  ---                       ---                    user_analog[7]
- * mprj_io[20]  ---                       ---                    user_analog[6]  clamp[2]
- * mprj_io[19]  ---                       ---                    user_analog[5]  clamp[1]
- * mprj_io[18]  ---                       ---                    user_analog[4]  clamp[0]
- * mprj_io[17]  ---                       ---                    user_analog[3]
- * mprj_io[16]  ---                       ---                    user_analog[2]
- * mprj_io[15]  ---                       ---                    user_analog[1]
- * mprj_io[14]  ---                       ---                    user_analog[0]
- * mprj_io[13]  io_in/out/oeb/in_3v3[13]  gpio_analog/noesd[6]   ---
- * mprj_io[12]  io_in/out/oeb/in_3v3[12]  gpio_analog/noesd[5]   ---
- * mprj_io[11]  io_in/out/oeb/in_3v3[11]  gpio_analog/noesd[4]   ---
- * mprj_io[10]  io_in/out/oeb/in_3v3[10]  gpio_analog/noesd[3]   ---
- * mprj_io[9]   io_in/out/oeb/in_3v3[9]   gpio_analog/noesd[2]   ---
- * mprj_io[8]   io_in/out/oeb/in_3v3[8]   gpio_analog/noesd[1]   ---
- * mprj_io[7]   io_in/out/oeb/in_3v3[7]   gpio_analog/noesd[0]   ---
- * mprj_io[6]   io_in/out/oeb/in_3v3[6]   ---                    ---
- * mprj_io[5]   io_in/out/oeb/in_3v3[5]   ---                    ---
- * mprj_io[4]   io_in/out/oeb/in_3v3[4]   ---                    ---
- * mprj_io[3]   io_in/out/oeb/in_3v3[3]   ---                    ---
- * mprj_io[2]   io_in/out/oeb/in_3v3[2]   ---                    ---
- * mprj_io[1]   io_in/out/oeb/in_3v3[1]   ---                    ---
- * mprj_io[0]   io_in/out/oeb/in_3v3[0]   ---                    ---
- *
- */
-
-/*
- *----------------------------------------------------------------
- *
- * user_analog_proj_example
- *
- * This is an example of a (trivially simple) analog user project,
- * showing how the user project can connect to the I/O pads, both
- * the digital pads, the analog connection on the digital pads,
- * and the dedicated analog pins used as an additional power supply
- * input, with a connected ESD clamp.
- *
- * See the testbench in directory "mprj_por" for the example
- * program that drives this user project.
- *
- *----------------------------------------------------------------
- */
-
-module user_analog_proj_example (
-`ifdef USE_POWER_PINS
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
-    inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
-    inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
-`endif
-
-    // Wishbone Slave ports (WB MI A)
-    input wb_clk_i,
-    input wb_rst_i,
-    input wbs_stb_i,
-    input wbs_cyc_i,
-    input wbs_we_i,
-    input [3:0] wbs_sel_i,
-    input [31:0] wbs_dat_i,
-    input [31:0] wbs_adr_i,
-    output wbs_ack_o,
-    output [31:0] wbs_dat_o,
-
-    // Logic Analyzer Signals
-    input  [127:0] la_data_in,
-    output [127:0] la_data_out,
-    input  [127:0] la_oenb,
-
-    // IOs
-    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
-    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
-    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
-    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
-
-    // GPIO-analog
-    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
-    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
-
-    // Dedicated analog
-    inout [`ANALOG_PADS-1:0] io_analog,
-    inout [2:0] io_clamp_high,
-    inout [2:0] io_clamp_low,
-
-    // Clock
-    input   user_clock2,
-
-    // IRQ
-    output [2:0] irq
-);
-    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
-    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
-    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
-    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
-    wire [`ANALOG_PADS-1:0] io_analog;
-
-    // wire [31:0] rdata; 
-    // wire [31:0] wdata;
-
-    // wire valid;
-    // wire [3:0] wstrb;
-
-    wire isupply;	// Independent 3.3V supply
-    wire io16, io15, io12, io11;
-
-    // WB MI A
-    // assign valid = wbs_cyc_i && wbs_stb_i; 
-    // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
-    // assign wbs_dat_o = rdata;
-    // assign wdata = wbs_dat_i;
-
-    // IO --- unused (no need to connect to anything)
-    // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
-    // assign io_out[14:13] = 11'b0;
-    // assign io_out[10:0] = 11'b0;
-
-    // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
-    // assign io_oeb[14:13] = 11'b1;
-    // assign io_oeb[10:0] = 11'b1;
-
-    // IO --- enable outputs on 11, 12, 15, and 16
-    assign io_out[12:11] = {io12, io11};
-    assign io_oeb[12:11] = {vssd1, vssd1};
-
-    assign io_out[16:15] = {io16, io15};
-    assign io_oeb[16:15] = {vssd1, vssd1};
-
-    // IRQ
-    assign irq = 3'b000;	// Unused
-
-    // LA --- unused (no need to connect to anything)
-    // assign la_data_out = {128{1'b0}};	// Unused
-
-    // Instantiate the POR.  Connect the digital power to user area 1
-    // VCCD, and connect the analog power to user area 1 VDDA.
-
-    // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
-    // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
-
-    example_por por1 (
-	`ifdef USE_POWER_PINS
-	    .vdd3v3(vdda1),
-	    .vdd1v8(vccd1),
-	    .vss(vssa1),
-	`endif
-	.porb_h(gpio_analog[3]),	// 3.3V domain output
-	.porb_l(io11),			// 1.8V domain output
-	.por_l(io12)			// 1.8V domain output
-    );
-
-    // Instantiate 2nd POR with the analog power supply on one of the
-    // analog pins.  NOTE:  io_analog[4] = mproj_io[18] and is the same
-    // pad with io_clamp_high/low[0].
-
-    `ifdef USE_POWER_PINS
-	assign isupply = io_analog[4];
-    	assign io_clamp_high[0] = isupply;
-    	assign io_clamp_low[0] = vssa1;
-
-	// Tie off remaining clamps
-    	assign io_clamp_high[2:1] = vssa1;
-    	assign io_clamp_low[2:1] = vssa1;
-    `endif
-
-    // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
-    // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
-
-    example_por por2 (
-	`ifdef USE_POWER_PINS
-	    .vdd3v3(isupply),
-	    .vdd1v8(vccd1),
-	    .vss(vssa1),
-	`endif
-	.porb_h(gpio_analog[7]),	// 3.3V domain output
-	.porb_l(io15),			// 1.8V domain output
-	.por_l(io16)			// 1.8V domain output
-    );
-
-endmodule
-
-`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index 7a73f76..8798597 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -1,42 +1,14 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-/*
- *-------------------------------------------------------------
- *
- * user_analog_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user analog project.
- *
- *-------------------------------------------------------------
- */
+// SPDX-License-Identifier: LGPL-2.1-or-later
 
 module user_analog_project_wrapper (
-`ifdef USE_POWER_PINS
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
-    inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
-    inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
-`endif
+    inout vdda1,
+    inout vdda2,
+    inout vssa1,
+    inout vssa2,
+    inout vccd1,
+    inout vccd2,
+    inout vssd1,
+    inout vssd2,
 
     // Wishbone Slave ports (WB MI A)
     input wb_clk_i,
@@ -55,60 +27,20 @@
     output [127:0] la_data_out,
     input  [127:0] la_oenb,
 
-    /* GPIOs.  There are 27 GPIOs, on either side of the analog.
-     * These have the following mapping to the GPIO padframe pins
-     * and memory-mapped registers, since the numbering remains the
-     * same as caravel but skips over the analog I/O:
-     *
-     * io_in/out/oeb/in_3v3 [26:14]  <--->  mprj_io[37:25]
-     * io_in/out/oeb/in_3v3 [13:0]   <--->  mprj_io[13:0]	
-     *
-     * When the GPIOs are configured by the Management SoC for
-     * user use, they have three basic bidirectional controls:
-     * in, out, and oeb (output enable, sense inverted).  For
-     * analog projects, a 3.3V copy of the signal input is
-     * available.  out and oeb must be 1.8V signals.
-     */
+    // GPIOs
+    input  [26:0] io_in,
+    input  [26:0] io_in_3v3,
+    output [26:0] io_out,
+    output [26:0] io_oeb,
 
-    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
-    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
-    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
-    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+    // GPIO-analog
+    inout [17:0] gpio_analog,
+    inout [17:0] gpio_noesd,
 
-    /* Analog (direct connection to GPIO pad---not for high voltage or
-     * high frequency use).  The management SoC must turn off both
-     * input and output buffers on these GPIOs to allow analog access.
-     * These signals may drive a voltage up to the value of VDDIO
-     * (3.3V typical, 5.5V maximum).
-     * 
-     * Note that analog I/O is not available on the 7 lowest-numbered
-     * GPIO pads, and so the analog_io indexing is offset from the
-     * GPIO indexing by 7, as follows:
-     *
-     * gpio_analog/noesd [17:7]  <--->  mprj_io[35:25]
-     * gpio_analog/noesd [6:0]   <--->  mprj_io[13:7]	
-     *
-     */
-    
-    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
-    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+    // Dedicate analog
+    inout [10:0] io_analog,
 
-    /* Analog signals, direct through to pad.  These have no ESD at all,
-     * so ESD protection is the responsibility of the designer.
-     *
-     * user_analog[10:0]  <--->  mprj_io[24:14]
-     *
-     */
-    inout [`ANALOG_PADS-1:0] io_analog,
-
-    /* Additional power supply ESD clamps, one per analog pad.  The
-     * high side should be connected to a 3.3-5.5V power supply.
-     * The low side should be connected to ground.
-     *
-     * clamp_high[2:0]   <--->  mprj_io[20:18]
-     * clamp_low[2:0]    <--->  mprj_io[20:18]
-     *
-     */
+    // Additional power supply ESD clamps
     inout [2:0] io_clamp_high,
     inout [2:0] io_clamp_low,
 
@@ -119,64 +51,49 @@
     output [2:0] user_irq
 );
 
-/*--------------------------------------*/
-/* User project is instantiated  here   */
-/*--------------------------------------*/
-
-user_analog_proj_example mprj (
-    `ifdef USE_POWER_PINS
-        .vdda1(vdda1),  // User area 1 3.3V power
-        .vdda2(vdda2),  // User area 2 3.3V power
-        .vssa1(vssa1),  // User area 1 analog ground
-        .vssa2(vssa2),  // User area 2 analog ground
-        .vccd1(vccd1),  // User area 1 1.8V power
-        .vccd2(vccd2),  // User area 2 1.8V power
-        .vssd1(vssd1),  // User area 1 digital ground
-        .vssd2(vssd2),  // User area 2 digital ground
-    `endif
-
+user_analog_project_wrapper_empty empty (
+    .vdda1(vdda1),
+    .vdda2(vdda2),
+    .vssa1(vssa1),
+    .vssa2(vssa2),
+    .vccd1(vccd1),
+    .vccd2(vccd2),
+    .vssd1(vssd1),
+    .vssd2(vssd2),
     .wb_clk_i(wb_clk_i),
     .wb_rst_i(wb_rst_i),
-
-    // MGMT SoC Wishbone Slave
-
-    .wbs_cyc_i(wbs_cyc_i),
     .wbs_stb_i(wbs_stb_i),
+    .wbs_cyc_i(wbs_cyc_i),
     .wbs_we_i(wbs_we_i),
     .wbs_sel_i(wbs_sel_i),
-    .wbs_adr_i(wbs_adr_i),
     .wbs_dat_i(wbs_dat_i),
+    .wbs_adr_i(wbs_adr_i),
     .wbs_ack_o(wbs_ack_o),
     .wbs_dat_o(wbs_dat_o),
-
-    // Logic Analyzer
-
     .la_data_in(la_data_in),
     .la_data_out(la_data_out),
-    .la_oenb (la_oenb),
-
-    // IO Pads
-    .io_in (io_in),
-    .io_in_3v3 (io_in_3v3),
+    .la_oenb(la_oenb),
+    .io_in(io_in),
+    .io_in_3v3(io_in_3v3),
     .io_out(io_out),
     .io_oeb(io_oeb),
-
-    // GPIO-analog
     .gpio_analog(gpio_analog),
     .gpio_noesd(gpio_noesd),
-
-    // Dedicated analog
     .io_analog(io_analog),
     .io_clamp_high(io_clamp_high),
-    .io_clamp_low(io_clamp_low),
-
-    // Clock
+    .io_clamp_low(io_clam_low),
     .user_clock2(user_clock2),
+    .user_irq(user_irq)
+)
 
-    // IRQ
-    .irq(user_irq)
-);
+ConnectedSRAM sram (
+    .vss(io_analog[4]),
+    .vdd(io_analog[5])
+)
+
+ConnectedBandGap bg (
+    .vss(io_analog[7]),
+    .vdd(io_analog[9])
+)
 
 endmodule	// user_analog_project_wrapper
-
-`default_nettype wire