diff --git a/doitcode/sram.py b/doitcode/sram.py
index e3a590d..2e322fe 100644
--- a/doitcode/sram.py
+++ b/doitcode/sram.py
@@ -158,6 +158,7 @@
         m2pin = cast(_prm.Marker, prims["m2.pin"])
         via2 = cast(_prm.Via, prims.via2)
         m3 = cast(_prm.MetalWire, prims.m3)
+        m3pin = cast(_prm.Marker, prims["m3.pin"])
 
         layouter = self.new_circuitlayouter()
         layout = layouter.layout
@@ -204,6 +205,7 @@
         layouter.add_wire(net=net, wire=m3, shape=shape)
         shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
         layouter.add_wire(net=net, wire=m3, shape=shape)
+        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # vdd
         spec = io_sig2spec["vdd"]
@@ -237,6 +239,7 @@
         layouter.add_wire(net=net, wire=m3, shape=shape)
         shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
         layouter.add_wire(net=net, wire=m3, shape=shape)
+        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # a
         col = 0
@@ -280,6 +283,7 @@
             layouter.add_wire(net=net, wire=m2, shape=shape)
             shape = _geo.Rect.from_rect(rect=toppin_bb, right=via2_m3bb.right)
             layouter.add_wire(net=net, wire=m3, shape=shape)
+            layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # The rest of the pin on m2
         for sram_signame in (
@@ -313,6 +317,7 @@
             else:
                 shape = _geo.Rect.from_rect(rect=toppin_bb, right=via2_m3bb.right)
             layouter.add_wire(net=net, wire=m3, shape=shape)
+            layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # boundary
         layout.boundary = _frm.boundary
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index 12287f3..39be064 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ