)]}'
{
  "commit": "0c8851d1a58749ba36bbe1024446fab73198bd42",
  "tree": "950a0e4a96915c2eddfbcadd0e437aaa785a1ce2",
  "parents": [
    "bfd401a927a57d5ac3b629d20b369ee7b047ca34"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Nov 16 09:45:57 2022 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Nov 16 09:45:57 2022 -0500"
  },
  "message": "Corrected the comment lines in user_defines.v to denote the correct\nset of I/Os which are analog pins and unused in the configuration.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c5f1c757d9199615e661f6720648c75cf8abf85f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_defines.v",
      "new_id": "ee44b08843530ec77806ee6f6108e153f787af0e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_defines.v"
    }
  ]
}