diff --git a/README.md b/README.md
index a0c1f02..2e56b72 100644
--- a/README.md
+++ b/README.md
@@ -8,3 +8,22 @@
 |-----------------------------------------|
 
 Ahem! Testing? Testing? Everything seems to be in order...
+
+Todo:
+
+- Cell A: TW Amplifier + SET + Integrated Amplifier
+  - GUARD AMP.VIN AMP.VOP GND
+- Cell B: TW Amplifier + SET
+  - GUARD 
+
+- [x]  Configuration Register
+- [ ]  Digital lines wiring
+- [ ]  TWG top wiring
+- [x]  cell A top wiring
+- [ ]  cell B
+- [ ]  Opamp (400µA) DUTs
+- [ ]  Opamp (200µA, Gain Boosted) DUTs
+- [ ]  High Isolation 2-1 MUX DUTs
+- [ ]  Standalone SET DUTs
+- [ ]  
+
diff --git a/gds/FiveTransistors.gds b/gds/FiveTransistors.gds
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diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
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diff --git a/netgen/.user_analog_project_wrapper.spice.swp b/netgen/.user_analog_project_wrapper.spice.swp
deleted file mode 100644
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diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 9b9d3a7..e2fd603 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -13,6 +13,23 @@
 .subckt unitcell
 .ends
 
+
+.subckt cfgsr
+.ends
+.subckt dut_opa_top_2x
+.ends
+.subckt largecap
+.ends
+.subckt largecap1
+.ends
+.subckt logo
+.ends
+.subckt unitcell_2x
+.ends
+.subckt unitcell_simplify_2x
+.ends
+
+
 .subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
 + gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
 + gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
@@ -128,5 +145,13 @@
 X6 unitcell
 X7 pad_bond_CDNS_671661177921_1
 
+X8 cfgsr
+X9 dut_opa_top_2x
+X10 largecap
+X11 largecap1
+X12 logo
+X13 unitcell_2x
+X14 unitcell_simplify_2x
+
 .ends