From f9f5d6804186bab5b9f44c65bd7986cec5c77840 Mon Sep 17 00:00:00 2001
From: roman3017 <rbacik@hotmail.com>
Date: Tue, 20 Dec 2022 20:19:40 -0800
Subject: [PATCH] fix make targets

make PROJ=soc lint
make PROJ=soc sim
make PROJ=soc wave
make PROJ=soc clean all
make PROJ=soc prog
---
 examples/TinyFPGA-BX/OSS_CAD_Suite/Makefile | 6 +++---
 examples/common/hdl/sim_tasks.v             | 2 +-
 examples/common/hdl/usb_rx_tasks.v          | 8 +++++---
 examples/common/hdl/usb_tasks.v             | 2 +-
 usb_cdc/sie.v                               | 4 ++--
 5 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/examples/TinyFPGA-BX/OSS_CAD_Suite/Makefile b/examples/TinyFPGA-BX/OSS_CAD_Suite/Makefile
index 057b70c..1a31220 100644
--- a/examples/TinyFPGA-BX/OSS_CAD_Suite/Makefile
+++ b/examples/TinyFPGA-BX/OSS_CAD_Suite/Makefile
@@ -1,6 +1,6 @@
 
 # override the default with: make all PROJ=loopback
-PROJ = demo
+PROJ ?= demo
 
 PIN_DEF = pins.pcf
 DEVICE = lp8k
@@ -42,7 +42,7 @@ prog: $(OUT_DIR)/$(PROJ).bin
 	tinyprog -p $<
 
 lint: $(HDL_FILES)
-	verilator --lint-only --default-language 1364-2001 -Wall -Wno-UNUSED -Wno-UNDRIVEN -Wno-TIMESCALEMOD -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS --top $(PROJ) $(INC_DIRS) -v $(ICE40_LIB) $^
+	verilator --lint-only --default-language 1364-2001 -Wall -Wno-UNUSED -Wno-UNDRIVEN -Wno-TIMESCALEMOD -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS $(INC_DIRS) -v $(ICE40_LIB) $^
 
 $(OUT_DIR)/cells_sim.v:
 	patch $(ICE40_LIB) -o $(OUT_DIR)/cells_sim.v < ../../common/hdl/ice40/cells_sim.v.patch
@@ -56,7 +56,7 @@ $(OUT_DIR)/%.fst: $(OUT_DIR)/%.vvp
 sim: $(OUT_DIR)/$(PROJ).fst
 
 $(OUT_DIR)/%.xml: $(HDL_FILES) $(TB_HDL_FILES) | $(OUT_DIR) $(OUT_DIR)/cells_sim.v
-	verilator -xml-only --bbox-unsup --bbox-sys -Wno-lint -Wno-TIMESCALEMOD -Wno-STMTDLY -Wno-INFINITELOOP -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS --top tb_$(PROJ) $(INC_DIRS) -v $(OUT_DIR)/cells_sim.v $^ --xml-output $@
+	verilator -xml-only --bbox-unsup --bbox-sys -Wno-lint -Wno-TIMESCALEMOD -Wno-STMTDLY -Wno-INFINITELOOP -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS $(INC_DIRS) -v $(OUT_DIR)/cells_sim.v $^ --xml-output $@
 
 $(OUT_DIR)/%.stems: $(OUT_DIR)/%.xml
 	xml2stems $< $@
diff --git a/examples/common/hdl/sim_tasks.v b/examples/common/hdl/sim_tasks.v
index 6fbcd61..8df33cc 100644
--- a/examples/common/hdl/sim_tasks.v
+++ b/examples/common/hdl/sim_tasks.v
@@ -52,6 +52,6 @@
          if (end_ms > 0) \
             $write("  (%3d%%)", 100*time_ms/end_ms); \
          $write("\015"); \
-         $fflush(32'h8000_0001); // flush STDOUT \
+         $fflush(32'h8000_0001); \
       end \
    end
diff --git a/examples/common/hdl/usb_rx_tasks.v b/examples/common/hdl/usb_rx_tasks.v
index f3f6db5..ade5c4b 100644
--- a/examples/common/hdl/usb_rx_tasks.v
+++ b/examples/common/hdl/usb_rx_tasks.v
@@ -10,6 +10,7 @@ localparam [3:0] PID_OUT = 4'b0001,
                  PID_NAK = 4'b1010,
                  PID_STALL = 4'b1110;
 
+localparam [4:0] POLY5 = 5'b00101;
 function automatic [4:0] crc5;
    input [MAX_BITS-1:0] data;
    input integer        bits;
@@ -26,6 +27,7 @@ function automatic [4:0] crc5;
    end
 endfunction
 
+localparam [15:0] POLY16 = 16'h8005;
 function automatic [15:0] crc16;
    input [8*MAX_BYTES-1:0] data;
    input integer           bytes;
@@ -44,12 +46,12 @@ function automatic [15:0] crc16;
    end
 endfunction
 
+localparam real STABLE_RATIO = 0.5; // stable time / bit_time
 task automatic wait_bit
   (
    input time    bit_time,
    input integer timeout // number of bit_time periods
    );
-   localparam real STABLE_RATIO = 0.5; // stable time / bit_time
    time            start_time;
    time            wait_time;
    reg             exit;
@@ -210,6 +212,8 @@ task automatic raw_packet_rx
    end
 endtask
 
+localparam [4:0]         POLY5_RESIDUAL = 5'b01100;
+localparam [15:0]        POLY16_RESIDUAL = 16'b1000000000001101;
 task automatic packet_rx
   (
    output [3:0]             pid,
@@ -221,8 +225,6 @@ task automatic packet_rx
    input time               bit_time,
    input integer            timeout // number of bit_time periods
    );
-   localparam [4:0]         POLY5_RESIDUAL = 5'b01100;
-   localparam [15:0]        POLY16_RESIDUAL = 16'b1000000000001101;
    reg [8*MAX_BYTES-1:0]    raw_data;
    integer                  raw_bytes;
    integer                  i;
diff --git a/examples/common/hdl/usb_tasks.v b/examples/common/hdl/usb_tasks.v
index 9f35ffc..8488af7 100644
--- a/examples/common/hdl/usb_tasks.v
+++ b/examples/common/hdl/usb_tasks.v
@@ -358,6 +358,7 @@ task automatic test_sof_crc_error
    end
 endtask
 
+localparam              PACKET_TIMEOUT = 6; // TRSPIPD1 (USB2.0 Tab.7-14 pag.188)
 task automatic test_data_out
   (
    input [6:0]             address,
@@ -370,7 +371,6 @@ task automatic test_data_out
    input time              wait_time, 
    inout [15:0]            dataout_toggle
    );
-   localparam              PACKET_TIMEOUT = 6; // TRSPIPD1 (USB2.0 Tab.7-14 pag.188)
    reg                     zlp;
    reg [3:0]               packet_pid;
    time                    start_timeout;
diff --git a/usb_cdc/sie.v b/usb_cdc/sie.v
index 58390c6..c808882 100644
--- a/usb_cdc/sie.v
+++ b/usb_cdc/sie.v
@@ -122,9 +122,9 @@ module sie
       end
    endfunction
 
+   localparam [4:0] POLY5 = 5'b00101;
    function [4:0] crc5;
       input [10:0] data;
-      localparam [4:0] POLY5 = 5'b00101;
       reg [3:0]        i;
       begin
          crc5 = 5'b11111;
@@ -147,10 +147,10 @@ module sie
       end
    endfunction
 
+   localparam [15:0] POLY16 = 16'h8005;
    function [15:0] crc16;
       input [7:0] data;
       input [15:0] crc;
-      localparam [15:0] POLY16 = 16'h8005;
       reg [3:0]         i;
       begin
          crc16 = crc;
-- 
2.34.1