2023-01-01 03:55:04 - [INFO] - {{Project Git Info}} Repository: https://github.com/roman3017/caravel_mpw8.git | Branch: main | Commit: c9f83622d61d88341300cf957bdea86a116b1cea
2023-01-01 03:55:04 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: caravel_mpw8
2023-01-01 03:55:04 - [INFO] - {{Project Type Info}} digital
2023-01-01 03:55:04 - [INFO] - {{Project GDS Info}} user_project_wrapper: e0cfc43542e1e44bc7156c21654dab1b1059fea2
2023-01-01 03:55:05 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
2023-01-01 03:55:05 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
2023-01-01 03:55:05 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs'
2023-01-01 03:55:05 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2023-01-01 03:55:05 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2023-01-01 03:55:06 - [INFO] - An approved LICENSE (Apache-2.0) was found in caravel_mpw8.
2023-01-01 03:55:06 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2023-01-01 03:55:06 - [INFO] - An approved LICENSE (Apache-2.0) was found in caravel_mpw8.
2023-01-01 03:55:06 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/output/demo/demo.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/output/loopback/loopback.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/output/soc/soc.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo/usb_cdc_Implmnt/sbt/outputs/bitmap/demo_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo_allverilog/usb_cdc_Implmnt/sbt/outputs/bitmap/demo_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/loopback/usb_cdc_Implmnt/sbt/outputs/bitmap/loopback_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/bitmap/soc_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/bootloader/bootloader.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/bootloader/fw_bootloader.bin): 'utf-8' codec can't decode byte 0xaa in position 1: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/demo/demo.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/loopback/loopback.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:06 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/soc/soc.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:07 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/bootloader/usb_cdc_Implmnt/sbt/outputs/bitmap/bootloader_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:07 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo/usb_cdc_Implmnt/sbt/outputs/bitmap/demo_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:07 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo_allverilog/usb_cdc_Implmnt/sbt/outputs/bitmap/demo_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:07 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_Implmnt/sbt/outputs/bitmap/loopback_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:07 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/bitmap/soc_bitmap.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:07 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/bootloader/bootloader-1.0.1.bin): 'utf-8' codec can't decode byte 0xff in position 0: invalid start byte
2023-01-01 03:55:07 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (caravel_mpw8/verilog/rtl/usb_cdc/readme_files/usb_cdc.vsdx): 'utf-8' codec can't decode byte 0x80 in position 14: invalid start byte
2023-01-01 03:55:07 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 237 non-compliant file(s) with the SPDX Standard.
2023-01-01 03:55:07 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['caravel_mpw8/openlane/user_proj_example/config.json', 'caravel_mpw8/openlane/user_project_wrapper/config.json', 'caravel_mpw8/verilog/includes/includes.gl+sdf.caravel_user_project', 'caravel_mpw8/verilog/includes/includes.gl.caravel_user_project', 'caravel_mpw8/verilog/includes/includes.rtl.caravel_user_project', 'caravel_mpw8/verilog/rtl/0001-usb_cdc-fix-make-targets.patch', 'caravel_mpw8/verilog/rtl/usb2uart.v', 'caravel_mpw8/verilog/rtl/fpga/Makefile', 'caravel_mpw8/verilog/rtl/fpga/fpga_pins.pcf', 'caravel_mpw8/verilog/rtl/fpga/fpga_top.v', 'caravel_mpw8/verilog/rtl/fpga/pll.v', 'caravel_mpw8/verilog/rtl/fpga/test_uart.v', 'caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/Makefile', 'caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/demo/hdl_files.mk', 'caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/demo/pre-pack.py']
2023-01-01 03:55:07 - [INFO] - For the full SPDX compliance report check: caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs/spdx_compliance_report.log
2023-01-01 03:55:07 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
2023-01-01 03:55:07 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2023-01-01 03:55:07 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
2023-01-01 03:55:07 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2023-01-01 03:55:07 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2023-01-01 03:55:07 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
2023-01-01 03:55:07 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2023-01-01 03:55:07 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
2023-01-01 03:55:12 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2023-01-01 03:55:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2023-01-01 03:55:12 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2023-01-01 03:55:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances). 
2023-01-01 03:55:12 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2023-01-01 03:55:12 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2023-01-01 03:55:12 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2023-01-01 03:55:12 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2023-01-01 03:55:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2023-01-01 03:55:12 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2023-01-01 03:55:12 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
2023-01-01 03:55:12 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'caravel_mpw8/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
2023-01-01 03:55:13 - [INFO] - GPIO-DEFINES report path: caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/reports/gpio_defines.report
2023-01-01 03:55:13 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
2023-01-01 03:55:13 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2023-01-01 03:55:20 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/user_project_wrapper.xor.gds
2023-01-01 03:55:20 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2023-01-01 03:55:20 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
2023-01-01 03:55:21 - [INFO] - 0 DRC violations
2023-01-01 03:55:21 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2023-01-01 03:55:21 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
2023-01-01 03:55:21 - [INFO] - in CUSTOM klayout_gds_drc_check
2023-01-01 03:55:21 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=caravel_mpw8/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/reports/klayout_feol_check.xml -rd feol=true >& caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs/klayout_feol_check.log
2023-01-01 03:55:39 - [INFO] - No DRC Violations found
2023-01-01 03:55:39 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2023-01-01 03:55:39 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
2023-01-01 03:55:39 - [INFO] - in CUSTOM klayout_gds_drc_check
2023-01-01 03:55:39 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=caravel_mpw8/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/reports/klayout_beol_check.xml -rd beol=true >& caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs/klayout_beol_check.log
2023-01-01 03:57:30 - [INFO] - No DRC Violations found
2023-01-01 03:57:30 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2023-01-01 03:57:30 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
2023-01-01 03:57:30 - [INFO] - in CUSTOM klayout_gds_drc_check
2023-01-01 03:57:30 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=caravel_mpw8/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs/klayout_offgrid_check.log
2023-01-01 03:57:52 - [INFO] - No DRC Violations found
2023-01-01 03:57:52 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2023-01-01 03:57:52 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
2023-01-01 03:57:52 - [INFO] - in CUSTOM klayout_gds_drc_check
2023-01-01 03:57:52 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=caravel_mpw8/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/reports/klayout_met_min_ca_density_check.xml >& caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs/klayout_met_min_ca_density_check.log
2023-01-01 03:58:00 - [INFO] - No DRC Violations found
2023-01-01 03:58:00 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2023-01-01 03:58:00 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
2023-01-01 03:58:00 - [INFO] - in CUSTOM klayout_gds_drc_check
2023-01-01 03:58:00 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=caravel_mpw8/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
2023-01-01 03:58:05 - [INFO] - No DRC Violations found
2023-01-01 03:58:05 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2023-01-01 03:58:05 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
2023-01-01 03:58:05 - [INFO] - in CUSTOM klayout_gds_drc_check
2023-01-01 03:58:05 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=caravel_mpw8/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/outputs/user_project_wrapper_no_zero_areas.gds >& caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs/klayout_zeroarea_check.log
2023-01-01 03:58:07 - [INFO] - No DRC Violations found
2023-01-01 03:58:07 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2023-01-01 03:58:07 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'caravel_mpw8/jobs/mpw_precheck/db6b91bf-6a8d-4145-9e2e-e3e52d06f0a2/logs'
2023-01-01 03:58:07 - [INFO] - {{SUCCESS}} All Checks Passed !!!