)]}'
{
  "commit": "fe61626e031941acd1d2a04999c3aca78c356e8c",
  "tree": "c23ae0ae0167a7f42520c4465982fa2f4f68fab4",
  "parents": [
    "68c10dc9910b9e3d6af155846bcf72e665029101"
  ],
  "author": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Tue Dec 20 21:01:25 2022 -0800"
  },
  "committer": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Tue Dec 20 21:01:25 2022 -0800"
  },
  "message": "add sim tests\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "95cd1b8ea2ba46e66d5d01ff6671d726f4d6e4e7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/0001-fix-make-targets.patch"
    },
    {
      "type": "modify",
      "old_id": "e241c452fd08687bc9dff136b023ce5c0047b079",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/Makefile",
      "new_id": "d71710d53afbeb25698391e4ef9b5fb90e4ccf99",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/Makefile"
    },
    {
      "type": "modify",
      "old_id": "3fc86c581b49a7ee646f7a5c886f7328fb0d6f05",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/README.md",
      "new_id": "32fd384f49e83478d38c8c58597f043506c8f2f3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/README.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1b54548979f215380af12e4a5293b9493c99426d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/test_uart.v"
    }
  ]
}
