)]}'
{
  "commit": "dfc4f24f530a6a09d7f40c45ba0d5b3cbed48b07",
  "tree": "d9e2bb4d2f3697635a3351f8052a9f875e704910",
  "parents": [
    "79356d97734a54a42fb54ab55753e1bd193b6249"
  ],
  "author": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Tue Dec 13 01:01:36 2022 -0800"
  },
  "committer": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Tue Dec 13 01:01:36 2022 -0800"
  },
  "message": "add uart to fpga_top test\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "555204ec50677ccf0458f177049e9783b2bb56b9",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/Makefile",
      "new_id": "03bfe8aad63cac600ed0ad2642fb7abed34e68ee",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a3bb582a3df9bad8678ecad118c7f0e1c9cff01f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/README.md",
      "new_id": "3fc86c581b49a7ee646f7a5c886f7328fb0d6f05",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/README.md"
    },
    {
      "type": "modify",
      "old_id": "3674bae63c70ab7349f7c23943f34cf573b814f2",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/fpga_pins.pcf",
      "new_id": "afa9d4d06861d4b4d461400c22b30056d3f7bce7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/fpga_pins.pcf"
    },
    {
      "type": "modify",
      "old_id": "67da9e09219ff5aa8e1ae46d18e0d73e076e283b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/fpga_top.v",
      "new_id": "d704edd2ae2a4e4ff4c377e32dc03df545fba3b9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/fpga_top.v"
    }
  ]
}