)]}'
{
  "commit": "ad392229e8089c169bf7e4ae62d49889f93f28a5",
  "tree": "2616fa155860b57b73149fc5c2f982442a492c75",
  "parents": [
    "2b8cfb1a8cbcba4235763ea5d2e6d5fefd39e7b2"
  ],
  "author": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Sun Dec 11 14:41:14 2022 -0800"
  },
  "committer": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Sun Dec 11 14:41:14 2022 -0800"
  },
  "message": "add usb submodule\n",
  "tree_diff": [
    {
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      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "70540c8241a0efb32b1ed595347b58f3950194c7",
      "new_mode": 33188,
      "new_path": ".gitmodules"
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      "type": "add",
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      "old_path": "/dev/null",
      "new_id": "00608c23488a3e79325df997cc50148b94961861",
      "new_mode": 57344,
      "new_path": "verilog/rtl/tinyfpga_bx_usbserial"
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}