)]}'
{
  "commit": "889dfb08c510e7b3454c4a196a6f7467142ebd0f",
  "tree": "526361c35ca879a6e113832f208bd87c46951f09",
  "parents": [
    "fe61626e031941acd1d2a04999c3aca78c356e8c"
  ],
  "author": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Tue Dec 20 22:39:41 2022 -0800"
  },
  "committer": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Tue Dec 20 22:39:41 2022 -0800"
  },
  "message": "optimize fpga timing\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d71710d53afbeb25698391e4ef9b5fb90e4ccf99",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/Makefile",
      "new_id": "b29bd15d76b1b1994d1bdb3c5954ae617d0e4b4d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/Makefile"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/fpga_top.v",
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      "new_path": "verilog/rtl/fpga/fpga_top.v"
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}