/root/caravel_mpw8/openlane/user_proj_example/config.json
/root/caravel_mpw8/openlane/user_project_wrapper/config.json
/root/caravel_mpw8/verilog/includes/includes.gl+sdf.caravel_user_project
/root/caravel_mpw8/verilog/includes/includes.gl.caravel_user_project
/root/caravel_mpw8/verilog/includes/includes.rtl.caravel_user_project
/root/caravel_mpw8/verilog/rtl/0001-usb_cdc-fix-make-targets.patch
/root/caravel_mpw8/verilog/rtl/usb2uart.v
/root/caravel_mpw8/verilog/rtl/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/fpga/fpga_pins.pcf
/root/caravel_mpw8/verilog/rtl/fpga/fpga_top.v
/root/caravel_mpw8/verilog/rtl/fpga/pll.v
/root/caravel_mpw8/verilog/rtl/fpga/test_uart.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/Makefile
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/demo/hdl_files.mk
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/demo/pre-pack.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/demo/gtkwave/app.cmd.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/demo/gtkwave/app.state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/demo/gtkwave/procs.tcl
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/loopback/hdl_files.mk
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/loopback/pre-pack.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/soc/hdl_files.mk
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/input/soc/pre-pack.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/output/demo/demo.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/output/loopback/loopback.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/output/soc/soc.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/pcf/fomu-evt2.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/pcf/fomu-evt3.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/pcf/fomu-hacker.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/OSS_CAD_Suite/pcf/fomu-pvt.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/demo/app.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/demo/demo.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/demo/demo_fpga.vhd
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/demo/demo_tasks.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/demo/tb_demo.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/loopback/loopback.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/loopback/tb_loopback.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/soc/app.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/soc/soc.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/hdl/soc/tb_soc.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo/usb_cdc_Implmnt/sbt/outputs/demo_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo/usb_cdc_Implmnt/sbt/outputs/timer/demo_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo_allverilog/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo_allverilog/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo_allverilog/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo_allverilog/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo_allverilog/usb_cdc_Implmnt/sbt/outputs/demo_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/demo_allverilog/usb_cdc_Implmnt/sbt/outputs/timer/demo_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/loopback/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/loopback/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/loopback/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/loopback/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/loopback/usb_cdc_Implmnt/sbt/outputs/loopback_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/loopback/usb_cdc_Implmnt/sbt/outputs/timer/loopback_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/soc/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/soc/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/soc/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/soc/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/soc_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/timer/soc_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/python/demo/dump.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/python/demo/fomu.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/python/demo/run.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/python/loopback/fomu.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/Fomu/python/loopback/run.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/Makefile
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/hdl_files.mk
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/pre-pack.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/gtkwave/app.state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/gtkwave/procs.tcl
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/hdl_files.mk
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/pre-pack.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/gtkwave/app.cmd.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/gtkwave/app.state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/gtkwave/procs.tcl
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/hdl_files.mk
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/pre-pack.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/gtkwave/procs.tcl
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/soc/hdl_files.mk
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/soc/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/input/soc/pre-pack.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/bootloader/bootloader.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/demo/demo.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/loopback/loopback.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/output/soc/soc.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/bootloader/app.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/bootloader/bootloader.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/bootloader/bootloader_tasks.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/bootloader/tb_bootloader.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/demo/app.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/demo/demo.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/demo/demo_fpga.vhd
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/demo/demo_tasks.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/demo/tb_demo.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/loopback/loopback.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/loopback/tb_loopback.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/soc/app.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/soc/soc.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/hdl/soc/tb_soc.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/bootloader/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/bootloader/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/bootloader/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/bootloader/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/bootloader/usb_cdc_Implmnt/sbt/outputs/bootloader_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/bootloader/usb_cdc_Implmnt/sbt/outputs/timer/bootloader_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo/usb_cdc_Implmnt/sbt/outputs/demo_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo/usb_cdc_Implmnt/sbt/outputs/timer/demo_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo_allverilog/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo_allverilog/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo_allverilog/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo_allverilog/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo_allverilog/usb_cdc_Implmnt/sbt/outputs/demo_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/demo_allverilog/usb_cdc_Implmnt/sbt/outputs/timer/demo_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/loopback/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/loopback/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_Implmnt/sbt/outputs/loopback_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_Implmnt/sbt/outputs/timer/loopback_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_sbt.project
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_syn.prj
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/soc/constraints/clk.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/soc/constraints/pins.pcf
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/soc_sbt.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/timer/soc_timing.rpt
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/bootloader/dump.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/bootloader/run.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/bootloader/tinyfpga.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/demo/dump.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/demo/run.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/demo/tinyfpga.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/loopback/run.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/TinyFPGA-BX/python/loopback/tinyfpga.py
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/ctrl_endp.dev_state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/out_fifo.out_state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/phy_rx.nrzi.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/phy_rx.rx_state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/phy_tx.tx_state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/procs.tcl
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/sie.phy_state.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/gtkwave/sie.pid.map
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/fifo_if.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/prescaler.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/prescaler_rtl.vhd
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/sim_tasks.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/sync.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/usb_monitor.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/usb_rx_tasks.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/usb_tasks.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/flash/AT25SF081.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/flash/flash_spi.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/flash/spi.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/ice40/SB_PLL40_CORE.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/ice40/SB_RAM256x16.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/ice40/cells_sim.v.patch
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/ice40/ram.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/hdl/ice40/rom.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/examples/common/synplifypro/usb_cdc.sdc
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/bulk_endp.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/ctrl_endp.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/in_fifo.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/out_fifo.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/phy_rx.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/phy_tx.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/sie.v
/root/caravel_mpw8/verilog/rtl/usb_cdc/usb_cdc/usb_cdc.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/AUTHORS
/root/caravel_mpw8/verilog/rtl/verilog-uart/COPYING
/root/caravel_mpw8/verilog/rtl/verilog-uart/tox.ini
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/fpga.ucf
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/common/xilinx.mk
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/rtl/debounce_switch.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/rtl/fpga.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/rtl/fpga_core.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/rtl/sync_reset.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ATLYS/fpga/rtl/sync_signal.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/fpga.xdc
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/common/vivado.mk
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/rtl/debounce_switch.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/rtl/fpga.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/rtl/fpga_core.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/rtl/sync_reset.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/Arty/fpga/rtl/sync_signal.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/fpga.ucf
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/common/xilinx.mk
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/rtl/debounce_switch.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/rtl/fpga.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/rtl/fpga_core.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/rtl/sync_reset.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/ML605/fpga/rtl/sync_signal.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/fpga.xdc
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/common/vivado.mk
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/rtl/debounce_switch.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/rtl/fpga.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/rtl/fpga_core.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/rtl/sync_reset.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/NexysVideo/fpga/rtl/sync_signal.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/fpga.xdc
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/common/vivado.mk
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/fpga/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/rtl/debounce_switch.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/rtl/fpga.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/rtl/fpga_core.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/rtl/sync_reset.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/example/VCU108/fpga/rtl/sync_signal.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/rtl/uart.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/rtl/uart_rx.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/rtl/uart_tx.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/axis_ep.py
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/test_uart_rx.py
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/test_uart_rx.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/test_uart_tx.py
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/test_uart_tx.v
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/uart_ep.py
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/uart_rx/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/uart_rx/test_uart_rx.py
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/uart_tx/Makefile
/root/caravel_mpw8/verilog/rtl/verilog-uart/tb/uart_tx/test_uart_tx.py