# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/rtl/usb2uart.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/phy_tx.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/phy_rx.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/sie.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/ctrl_endp.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/in_fifo.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/out_fifo.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/bulk_endp.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/usb_cdc.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/examples/common/hdl/prescaler.v
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/examples/common/hdl/fifo_if.v
-v $(USER_PROJECT_VERILOG)/rtl/verilog-uart/rtl/uart_rx.v
-v $(USER_PROJECT_VERILOG)/rtl/verilog-uart/rtl/uart_tx.v
-v $(USER_PROJECT_VERILOG)/rtl/verilog/rtl/verilog-uart/rtl/uart.v