diff --git a/README.md b/README.md
index 4dc1b9b..91339d0 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,11 @@
-# MPW shuttle (WIP)
+# MPW shuttle
+
 ## USB2UART
 
+Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
+
+See verilog/rtl/fpga folder for FPGA tests.
+
 ```sh
 mkdir -p dependencies
 export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
@@ -15,6 +20,7 @@
 klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds
 
 make verify
+make SIM=GL verify
 #make extract-parasitics
 make create-spef-mapping
 #make caravel-sta
@@ -25,5 +31,9 @@
 ```
 
 ## References
-[QUICKSTART] (https://caravel-user-project.readthedocs.io/en/latest) for a QSG.
-[README](docs/source/index.rst) for a sample project documentation. 
+
+ - [QUICKSTART](https://caravel-user-project.readthedocs.io/en/latest) For a QSG.
+ - [README](docs/source/index.rst) For a sample project documentation.
+ - [USB CDC](https://github.com/ulixxe/usb_cdc) IP taken from ulixxe
+ - [UART](https://github.com/alexforencich/verilog-uart) IP taken from alexforencich
+ - [MPW shuttle](https://platform.efabless.com/shuttles/MPW-8) Submitted project 1758
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..585eae2 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,17 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-
- 
\ No newline at end of file
+-v $(USER_PROJECT_VERILOG)/rtl/usb2uart.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/phy_tx.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/phy_rx.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/sie.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/ctrl_endp.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/in_fifo.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/out_fifo.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/bulk_endp.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/usb_cdc/usb_cdc.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/examples/common/hdl/prescaler.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/examples/common/hdl/fifo_if.v
+-v $(USER_PROJECT_VERILOG)/rtl/verilog-uart/rtl/uart_rx.v
+-v $(USER_PROJECT_VERILOG)/rtl/verilog-uart/rtl/uart_tx.v
+-v $(USER_PROJECT_VERILOG)/rtl/verilog/rtl/verilog-uart/rtl/uart.v
diff --git a/verilog/rtl/fpga/README.md b/verilog/rtl/fpga/README.md
index e3fbd79..f3e5085 100644
--- a/verilog/rtl/fpga/README.md
+++ b/verilog/rtl/fpga/README.md
@@ -40,14 +40,14 @@
 
 ## USB2UART
 
-Attach another USB2UART to the first three pins on TinyFPGA_BX: GND, 1(RX), and 2(TX). One should see characters being passed between.
+Attach another USB-TTL device to the first three pins on TinyFPGA_BX: GND, 1(RX), and 2(TX). One should see characters being passed between.
 
 ```sh
 tinyprog -l
-make clean all
-make prog
-tinyprog -b
+make clean prog
+#tinyprog -b
 
+#open two terminals and connect them to usb2serial ports to see characters passed between them
 minicom -D /dev/ttyACM0
 minicom -D /dev/ttyUSB0
 ```
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..703f4f1 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,4 +25,18 @@
 `else
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
+    `include "usb2uart.v"
+    `include "usb_cdc/usb_cdc/phy_tx.v",
+    `include "usb_cdc/usb_cdc/phy_rx.v",
+    `include "usb_cdc/usb_cdc/sie.v",
+    `include "usb_cdc/usb_cdc/ctrl_endp.v",
+    `include "usb_cdc/usb_cdc/in_fifo.v",
+    `include "usb_cdc/usb_cdc/out_fifo.v",
+    `include "usb_cdc/usb_cdc/bulk_endp.v",
+    `include "usb_cdc/usb_cdc/usb_cdc.v",
+    `include "usb_cdc/examples/common/hdl/prescaler.v",
+    `include "usb_cdc/examples/common/hdl/fifo_if.v",
+    `include "verilog-uart/rtl/uart_rx.v",
+    `include "verilog-uart/rtl/uart_tx.v",
+    `include "verilog/rtl/verilog-uart/rtl/uart.v"
 `endif
\ No newline at end of file