tree c5b9cc6e1881ad154fbeaa42a20600f60b83cc7c
parent dfc4f24f530a6a09d7f40c45ba0d5b3cbed48b07
author roman3017 <rbacik@hotmail.com> 1671519378 -0800
committer roman3017 <rbacik@hotmail.com> 1671519378 -0800

update fpga test
 - usb->ttl looks ok
 - ttl->usb has some errors
 - timing is not met
 - max clk_pll is 44mhz but needs 48mhz