)]}'
{
  "commit": "68c10dc9910b9e3d6af155846bcf72e665029101",
  "tree": "c5b9cc6e1881ad154fbeaa42a20600f60b83cc7c",
  "parents": [
    "dfc4f24f530a6a09d7f40c45ba0d5b3cbed48b07"
  ],
  "author": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Mon Dec 19 22:56:18 2022 -0800"
  },
  "committer": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Mon Dec 19 22:56:18 2022 -0800"
  },
  "message": "update fpga test\n - usb-\u003ettl looks ok\n - ttl-\u003eusb has some errors\n - timing is not met\n - max clk_pll is 44mhz but needs 48mhz\n",
  "tree_diff": [
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      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/fpga_pins.pcf"
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      "new_path": "verilog/rtl/fpga/fpga_top.v"
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    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "cb436f94b5765797892efb60f91ebd8f5199701b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/pll.v"
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}