diff --git a/verilog/rtl/fpga/Makefile b/verilog/rtl/fpga/Makefile
index 03bfe8a..e241c45 100644
--- a/verilog/rtl/fpga/Makefile
+++ b/verilog/rtl/fpga/Makefile
@@ -16,10 +16,10 @@
 ../usb_cdc/usb_cdc/usb_cdc.v \
 ../usb_cdc/examples/common/hdl/prescaler.v \
 ../usb_cdc/examples/common/hdl/fifo_if.v \
+pll.v \
 ../verilog-uart/rtl/uart_rx.v \
 ../verilog-uart/rtl/uart_tx.v \
-../verilog-uart/rtl/uart.v \
-../usb_cdc/examples/TinyFPGA-BX/hdl/soc/app.v
+../verilog-uart/rtl/uart.v
 PIN_DEF = fpga_pins.pcf
 
 # TinyFPGA-BX
diff --git a/verilog/rtl/fpga/fpga_pins.pcf b/verilog/rtl/fpga/fpga_pins.pcf
index afa9d4d..5c83f73 100644
--- a/verilog/rtl/fpga/fpga_pins.pcf
+++ b/verilog/rtl/fpga/fpga_pins.pcf
@@ -5,7 +5,7 @@
 set_io usb_pu A3
 set_io usb_n A4
 set_io usb_p B4
-set_io uart_rx C2
-set_io uart_tx D2
+set_io uart_rx A2
+set_io uart_tx A1
 set_io led B3
 set_io clk B2
diff --git a/verilog/rtl/fpga/fpga_top.v b/verilog/rtl/fpga/fpga_top.v
index d704edd..f0aac5e 100644
--- a/verilog/rtl/fpga/fpga_top.v
+++ b/verilog/rtl/fpga/fpga_top.v
@@ -1,4 +1,3 @@
-
 module fpga_top (
    input  clk, // 16MHz Clock
    output led, // User LED ON=1, OFF=0
@@ -7,74 +6,40 @@
    inout  usb_p, // USB+
    inout  usb_n, // USB-
    output usb_pu  // USB 1.5kOhm Pullup EN
-   );
+);
 
-   localparam BIT_SAMPLES = 'd4;
-   localparam [6:0] DIVF = 12*BIT_SAMPLES-1;
+   localparam BIT_SAMPLES       = 4;
+   localparam c_CLOCK_MHZ       = BIT_SAMPLES*12;
+   localparam c_UART_SPEED      = 115200;
+   localparam c_CLKS_PER_BIT    = c_CLOCK_MHZ*1000000/c_UART_SPEED;
+   localparam c_CLKS_PER_BYTE   = (c_CLOCK_MHZ*1000000+c_UART_SPEED*8-1)/(c_UART_SPEED*8);
 
-   wire             clk_pll;
-   wire             clk_1mhz;
-   wire             clk_2mhz;
-   wire             clk_4mhz;
-   wire             clk_8mhz;
+   wire             clk_pll; //48MHz clock
    wire             lock;
+
    wire             dp_pu;
    wire             dp_rx;
    wire             dn_rx;
    wire             dp_tx;
    wire             dn_tx;
    wire             tx_en;
-   wire [7:0]       out_data;
-   wire             out_valid;
-   wire             in_ready;
+
+   reg              in_ready;
    wire [7:0]       in_data;
    wire             in_valid;
    wire             out_ready;
+   reg [7:0]        out_data;
+   reg              out_valid;
 
-   // if FEEDBACK_PATH = SIMPLE:
-   // clk_freq = (ref_freq * (DIVF + 1)) / (2**DIVQ * (DIVR + 1));
-   SB_PLL40_CORE #(
-      .DIVR(4'd0),
-      .DIVF(DIVF),
-      .DIVQ(3'd4),
-      .FILTER_RANGE(3'b001),
-      .FEEDBACK_PATH("SIMPLE"),
-      .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
-      .FDA_FEEDBACK(4'b0000),
-      .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
-      .FDA_RELATIVE(4'b0000),
-      .SHIFTREG_DIV_MODE(2'b00),
-      .PLLOUT_SELECT("GENCLK"),
-      .ENABLE_ICEGATE(1'b0))
-   u_pll (
-      .REFERENCECLK(clk), // 16MHz
-      .PLLOUTCORE(),
-      .PLLOUTGLOBAL(clk_pll), // 48MHz
-      .EXTFEEDBACK(1'b0),
-      .DYNAMICDELAY(8'd0),
-      .LOCK(lock),
-      .BYPASS(1'b0),
-      .RESETB(1'b1),
-      .SDI(1'b0),
-      .SDO(),
-      .SCLK(1'b0),
-      .LATCHINPUTVALUE(1'b1));
+   pll pll48( .clock_in(clk), .clock_out(clk_pll), .locked( lock ) );
 
-   prescaler u_prescaler (
-      .clk_i(clk),
-      .rstn_i(lock),
-      .clk_div16_o(clk_1mhz),
-      .clk_div8_o(clk_2mhz),
-      .clk_div4_o(clk_4mhz),
-      .clk_div2_o(clk_8mhz));
+   assign led = 1'b1;
+   //assign usb_pu = dp_pu;
 
    reg [1:0]        rstn_sync;
-
    wire             rstn;
-
    assign rstn = rstn_sync[0];
-
-   always @(posedge clk_1mhz or negedge lock) begin
+   always @(posedge clk_pll or negedge lock) begin
       if (~lock) begin
          rstn_sync <= 2'd0;
       end else begin
@@ -82,87 +47,57 @@
       end
    end
 
-   reg [20:0]       up_cnt;
-   reg [1:0]        sleep_sq;
-
-   wire             sleep;
-
-   always @(posedge clk_1mhz or negedge rstn) begin
-      if (~rstn) begin
-         up_cnt <= 'd0;
-         sleep_sq <= 2'b00;
-      end else begin
-         sleep_sq <= {sleep, sleep_sq[1]};
-         if (up_cnt[20] == 1'b0)
-           up_cnt <= up_cnt + 1;
-         else if (~sleep_sq[0])
-           up_cnt <= 21'hE0000;
-      end
-   end
-
-   assign led = ~dp_pu | ~up_cnt[20];
-/*
-   app u_app (
-      .clk_i(clk_2mhz),
-      .rstn_i(rstn),
-      .sleep_o(sleep),
-      .out_data_i(out_data),
-      .out_valid_i(out_valid),
-      .in_ready_i(in_ready),
-      .out_ready_o(out_ready),
-      .in_data_o(in_data),
-      .in_valid_o(in_valid));
-//*/
-//*
-   uart u_uart (
-      .clk(clk_2mhz),
+   uart # (
+      .DATA_WIDTH(8)
+   ) u_uart (
+      .clk(clk_pll),
       .rst(~rstn),
+
       .s_axis_tdata(out_data),
       .s_axis_tvalid(out_valid),
       .s_axis_tready(out_ready),
+      .txd(uart_tx),
+
       .m_axis_tdata(in_data),
       .m_axis_tvalid(in_valid),
       .m_axis_tready(in_ready),
       .rxd(uart_rx),
-      .txd(uart_tx),
-      //.tx_busy(),
-      //.rx_busy(),
-      //.rx_overrun_error(),
-      //.rx_frame_error(),
-      .prescale(16'h0002) //2000000÷(115200*8)=2.17
+
+      .prescale(c_CLKS_PER_BYTE)
    );
-//*/
+
    usb_cdc #(
       .VENDORID(16'h1D50),
       .PRODUCTID(16'h6130),
       .IN_BULK_MAXPACKETSIZE('d8),
       .OUT_BULK_MAXPACKETSIZE('d8),
       .BIT_SAMPLES(BIT_SAMPLES),
-      .USE_APP_CLK(1),
-      .APP_CLK_RATIO(BIT_SAMPLES*12/2))  // BIT_SAMPLES * 12MHz / 2MHz
-   u_usb_cdc (
-      .frame_o(),
-      .configured_o(),
-      .app_clk_i(clk_2mhz),
-      .clk_i(clk_pll),
+      .USE_APP_CLK(0),
+      .APP_CLK_RATIO(c_CLKS_PER_BIT)
+   ) u_usb_cdc (
+      .clk_i(clk_pll), // 48MHz
       .rstn_i(rstn),
+      .app_clk_i(),
+      .out_data_o(out_data),
+      .out_valid_o(out_valid),
       .out_ready_i(out_ready),
       .in_data_i(in_data),
       .in_valid_i(in_valid),
-      .dp_rx_i(dp_rx),
-      .dn_rx_i(dn_rx),
-      .out_data_o(out_data),
-      .out_valid_o(out_valid),
       .in_ready_o(in_ready),
+      .frame_o(),
+      .configured_o(),
       .dp_pu_o(dp_pu),
       .tx_en_o(tx_en),
       .dp_tx_o(dp_tx),
-      .dn_tx_o(dn_tx));
+      .dn_tx_o(dn_tx),
+      .dp_rx_i(dp_rx),
+      .dn_rx_i(dn_rx)
+   );
 
    SB_IO #(
       .PIN_TYPE(6'b101001),
-      .PULLUP(1'b0))
-   u_usb_p (
+      .PULLUP(1'b0)
+   ) u_usb_p (
       .PACKAGE_PIN(usb_p),
       .OUTPUT_ENABLE(tx_en),
       .D_OUT_0(dp_tx),
@@ -176,8 +111,8 @@
 
    SB_IO #(
       .PIN_TYPE(6'b101001),
-      .PULLUP(1'b0))
-   u_usb_n (
+      .PULLUP(1'b0)
+   ) u_usb_n (
       .PACKAGE_PIN(usb_n),
       .OUTPUT_ENABLE(tx_en),
       .D_OUT_0(dn_tx),
diff --git a/verilog/rtl/fpga/pll.v b/verilog/rtl/fpga/pll.v
new file mode 100644
index 0000000..cb436f9
--- /dev/null
+++ b/verilog/rtl/fpga/pll.v
@@ -0,0 +1,33 @@
+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:        16.000 MHz
+ * Requested output frequency:   48.000 MHz
+ * Achieved output frequency:    48.000 MHz
+ */
+
+module pll(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0000),		// DIVR =  0
+		.DIVF(7'b0101111),	// DIVF = 47
+		.DIVQ(3'b100),		// DIVQ =  4
+		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule