)]}'
{
  "commit": "50e9fcb9cf5c23e1ad812b835f8c9c4d91e04b77",
  "tree": "fe587a2d97b1ff71077f1fefea9c978ea8798e5c",
  "parents": [
    "3914fd62b6ded00fbea84171bb075ed0a2d72ed0"
  ],
  "author": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Sat Dec 24 18:23:51 2022 -0800"
  },
  "committer": {
    "name": "roman3017",
    "email": "rbacik@hotmail.com",
    "time": "Sat Dec 24 18:23:51 2022 -0800"
  },
  "message": "add usb2uart to user_proj_example\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f2512493721c96e7e909762ee8f94430293ea730",
      "old_mode": 33188,
      "old_path": "README.md",
      "new_id": "4dc1b9b59121143ea8f2dab42f2c0ba5d0ce973f",
      "new_mode": 33188,
      "new_path": "README.md"
    },
    {
      "type": "modify",
      "old_id": "370d74cd464b7befbc6c610f1f065b472187cb54",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_example/config.json",
      "new_id": "9f05696048160396c88667b2764e619d498a553c",
      "new_mode": 33188,
      "new_path": "openlane/user_proj_example/config.json"
    },
    {
      "type": "modify",
      "old_id": "2fda806ab62cbe43d3a6b2844e4bab975333e67b",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_example/pin_order.cfg",
      "new_id": "35255bfd9a57711579d5cbf299135fed5a0f731e",
      "new_mode": 33188,
      "new_path": "openlane/user_proj_example/pin_order.cfg"
    },
    {
      "type": "rename",
      "old_id": "95cd1b8ea2ba46e66d5d01ff6671d726f4d6e4e7",
      "old_mode": 33188,
      "old_path": "verilog/rtl/0001-fix-make-targets.patch",
      "new_id": "95cd1b8ea2ba46e66d5d01ff6671d726f4d6e4e7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/0001-usb_cdc-fix-make-targets.patch",
      "score": 100
    },
    {
      "type": "modify",
      "old_id": "7946b02c42f4a25c42ba0cb34edb9c94a7f82d0f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/Makefile",
      "new_id": "d3028e58ae26f5826a99b5dd7ccfe5d9ce761e77",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/Makefile"
    },
    {
      "type": "modify",
      "old_id": "58964bb256f7a9152dc23156baca2aa607dbc217",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/README.md",
      "new_id": "e3fbd79f220feec0e5f4064a891b0bc692495a28",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/README.md"
    },
    {
      "type": "modify",
      "old_id": "df4e9864a5744bbc0a81e83652d67f241f8ae9ca",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga/fpga_top.v",
      "new_id": "72de9c945e9a6d01840f0a88ddaf30630604b515",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga/fpga_top.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6acd066733b2b7b5cf786c8da4bc06b54736a3fb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/usb2uart.v"
    },
    {
      "type": "modify",
      "old_id": "8533e2f27181403248ff1334b4881693308f84f1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_defines.v",
      "new_id": "74f545978bf6cef074698df22cd6fa7cadffde64",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_defines.v"
    },
    {
      "type": "modify",
      "old_id": "26081e98ecdd98ac1a677c29dfbd5fb0dbc4ee53",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "efd4938b139536b11d11d4ceacf46a6b7aaed7c3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    },
    {
      "type": "modify",
      "old_id": "5ee1ceecfb5f08335c33a73de2e09ef869af17a9",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "2bbb1e295a050bcb84a9e804f02bd504d3cae19b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}